NCR_Q720.c 9.1 KB

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  1. /* -*- mode: c; c-basic-offset: 8 -*- */
  2. /* NCR Quad 720 MCA SCSI Driver
  3. *
  4. * Copyright (C) 2003 by James.Bottomley@HansenPartnership.com
  5. */
  6. #include <linux/blkdev.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/mca.h>
  11. #include <linux/types.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <asm/io.h>
  15. #include "scsi.h"
  16. #include <scsi/scsi_host.h>
  17. #include "ncr53c8xx.h"
  18. #include "NCR_Q720.h"
  19. static struct ncr_chip q720_chip __initdata = {
  20. .revision_id = 0x0f,
  21. .burst_max = 3,
  22. .offset_max = 8,
  23. .nr_divisor = 4,
  24. .features = FE_WIDE | FE_DIFF | FE_VARCLK,
  25. };
  26. MODULE_AUTHOR("James Bottomley");
  27. MODULE_DESCRIPTION("NCR Quad 720 SCSI Driver");
  28. MODULE_LICENSE("GPL");
  29. #define NCR_Q720_VERSION "0.9"
  30. /* We needs this helper because we have up to four hosts per struct device */
  31. struct NCR_Q720_private {
  32. struct device *dev;
  33. void __iomem * mem_base;
  34. __u32 phys_mem_base;
  35. __u32 mem_size;
  36. __u8 irq;
  37. __u8 siops;
  38. __u8 irq_enable;
  39. struct Scsi_Host *hosts[4];
  40. };
  41. static struct scsi_host_template NCR_Q720_tpnt = {
  42. .module = THIS_MODULE,
  43. .proc_name = "NCR_Q720",
  44. };
  45. static irqreturn_t
  46. NCR_Q720_intr(int irq, void *data)
  47. {
  48. struct NCR_Q720_private *p = (struct NCR_Q720_private *)data;
  49. __u8 sir = (readb(p->mem_base + 0x0d) & 0xf0) >> 4;
  50. __u8 siop;
  51. sir |= ~p->irq_enable;
  52. if(sir == 0xff)
  53. return IRQ_NONE;
  54. while((siop = ffz(sir)) < p->siops) {
  55. sir |= 1<<siop;
  56. ncr53c8xx_intr(irq, p->hosts[siop]);
  57. }
  58. return IRQ_HANDLED;
  59. }
  60. static int __init
  61. NCR_Q720_probe_one(struct NCR_Q720_private *p, int siop,
  62. int irq, int slot, __u32 paddr, void __iomem *vaddr)
  63. {
  64. struct ncr_device device;
  65. __u8 scsi_id;
  66. static int unit = 0;
  67. __u8 scsr1 = readb(vaddr + NCR_Q720_SCSR_OFFSET + 1);
  68. __u8 differential = readb(vaddr + NCR_Q720_SCSR_OFFSET) & 0x20;
  69. __u8 version;
  70. int error;
  71. scsi_id = scsr1 >> 4;
  72. /* enable burst length 16 (FIXME: should allow this) */
  73. scsr1 |= 0x02;
  74. /* force a siop reset */
  75. scsr1 |= 0x04;
  76. writeb(scsr1, vaddr + NCR_Q720_SCSR_OFFSET + 1);
  77. udelay(10);
  78. version = readb(vaddr + 0x18) >> 4;
  79. memset(&device, 0, sizeof(struct ncr_device));
  80. /* Initialise ncr_device structure with items required by ncr_attach. */
  81. device.chip = q720_chip;
  82. device.chip.revision_id = version;
  83. device.host_id = scsi_id;
  84. device.dev = p->dev;
  85. device.slot.base = paddr;
  86. device.slot.base_c = paddr;
  87. device.slot.base_v = vaddr;
  88. device.slot.irq = irq;
  89. device.differential = differential ? 2 : 0;
  90. printk("Q720 probe unit %d (siop%d) at 0x%lx, diff = %d, vers = %d\n", unit, siop,
  91. (unsigned long)paddr, differential, version);
  92. p->hosts[siop] = ncr_attach(&NCR_Q720_tpnt, unit++, &device);
  93. if (!p->hosts[siop])
  94. goto fail;
  95. p->irq_enable |= (1<<siop);
  96. scsr1 = readb(vaddr + NCR_Q720_SCSR_OFFSET + 1);
  97. /* clear the disable interrupt bit */
  98. scsr1 &= ~0x01;
  99. writeb(scsr1, vaddr + NCR_Q720_SCSR_OFFSET + 1);
  100. error = scsi_add_host(p->hosts[siop], p->dev);
  101. if (error)
  102. ncr53c8xx_release(p->hosts[siop]);
  103. else
  104. scsi_scan_host(p->hosts[siop]);
  105. return error;
  106. fail:
  107. return -ENODEV;
  108. }
  109. /* Detect a Q720 card. Note, because of the setup --- the chips are
  110. * essentially connectecd to the MCA bus independently, it is easier
  111. * to set them up as two separate host adapters, rather than one
  112. * adapter with two channels */
  113. static int __init
  114. NCR_Q720_probe(struct device *dev)
  115. {
  116. struct NCR_Q720_private *p;
  117. static int banner = 1;
  118. struct mca_device *mca_dev = to_mca_device(dev);
  119. int slot = mca_dev->slot;
  120. int found = 0;
  121. int irq, i, siops;
  122. __u8 pos2, pos4, asr2, asr9, asr10;
  123. __u16 io_base;
  124. __u32 base_addr, mem_size;
  125. void __iomem *mem_base;
  126. p = kzalloc(sizeof(*p), GFP_KERNEL);
  127. if (!p)
  128. return -ENOMEM;
  129. pos2 = mca_device_read_pos(mca_dev, 2);
  130. /* enable device */
  131. pos2 |= NCR_Q720_POS2_BOARD_ENABLE | NCR_Q720_POS2_INTERRUPT_ENABLE;
  132. mca_device_write_pos(mca_dev, 2, pos2);
  133. io_base = (pos2 & NCR_Q720_POS2_IO_MASK) << NCR_Q720_POS2_IO_SHIFT;
  134. if(banner) {
  135. printk(KERN_NOTICE "NCR Q720: Driver Version " NCR_Q720_VERSION "\n"
  136. "NCR Q720: Copyright (c) 2003 by James.Bottomley@HansenPartnership.com\n"
  137. "NCR Q720:\n");
  138. banner = 0;
  139. }
  140. io_base = mca_device_transform_ioport(mca_dev, io_base);
  141. /* OK, this is phase one of the bootstrap, we now know the
  142. * I/O space base address. All the configuration registers
  143. * are mapped here (including pos) */
  144. /* sanity check I/O mapping */
  145. i = inb(io_base) | (inb(io_base+1)<<8);
  146. if(i != NCR_Q720_MCA_ID) {
  147. printk(KERN_ERR "NCR_Q720, adapter failed to I/O map registers correctly at 0x%x(0x%x)\n", io_base, i);
  148. kfree(p);
  149. return -ENODEV;
  150. }
  151. /* Phase II, find the ram base and memory map the board register */
  152. pos4 = inb(io_base + 4);
  153. /* enable streaming data */
  154. pos4 |= 0x01;
  155. outb(pos4, io_base + 4);
  156. base_addr = (pos4 & 0x7e) << 20;
  157. base_addr += (pos4 & 0x80) << 23;
  158. asr10 = inb(io_base + 0x12);
  159. base_addr += (asr10 & 0x80) << 24;
  160. base_addr += (asr10 & 0x70) << 23;
  161. /* OK, got the base addr, now we need to find the ram size,
  162. * enable and map it */
  163. asr9 = inb(io_base + 0x11);
  164. i = (asr9 & 0xc0) >> 6;
  165. if(i == 0)
  166. mem_size = 1024;
  167. else
  168. mem_size = 1 << (19 + i);
  169. /* enable the sram mapping */
  170. asr9 |= 0x20;
  171. /* disable the rom mapping */
  172. asr9 &= ~0x10;
  173. outb(asr9, io_base + 0x11);
  174. if(!request_mem_region(base_addr, mem_size, "NCR_Q720")) {
  175. printk(KERN_ERR "NCR_Q720: Failed to claim memory region 0x%lx\n-0x%lx",
  176. (unsigned long)base_addr,
  177. (unsigned long)(base_addr + mem_size));
  178. goto out_free;
  179. }
  180. if (dma_declare_coherent_memory(dev, base_addr, base_addr,
  181. mem_size, DMA_MEMORY_MAP)
  182. != DMA_MEMORY_MAP) {
  183. printk(KERN_ERR "NCR_Q720: DMA declare memory failed\n");
  184. goto out_release_region;
  185. }
  186. /* The first 1k of the memory buffer is a memory map of the registers
  187. */
  188. mem_base = dma_mark_declared_memory_occupied(dev, base_addr,
  189. 1024);
  190. if (IS_ERR(mem_base)) {
  191. printk("NCR_Q720 failed to reserve memory mapped region\n");
  192. goto out_release;
  193. }
  194. /* now also enable accesses in asr 2 */
  195. asr2 = inb(io_base + 0x0a);
  196. asr2 |= 0x01;
  197. outb(asr2, io_base + 0x0a);
  198. /* get the number of SIOPs (this should be 2 or 4) */
  199. siops = ((asr2 & 0xe0) >> 5) + 1;
  200. /* sanity check mapping (again) */
  201. i = readw(mem_base);
  202. if(i != NCR_Q720_MCA_ID) {
  203. printk(KERN_ERR "NCR_Q720, adapter failed to memory map registers correctly at 0x%lx(0x%x)\n", (unsigned long)base_addr, i);
  204. goto out_release;
  205. }
  206. irq = readb(mem_base + 5) & 0x0f;
  207. /* now do the bus related transforms */
  208. irq = mca_device_transform_irq(mca_dev, irq);
  209. printk(KERN_NOTICE "NCR Q720: found in slot %d irq = %d mem base = 0x%lx siops = %d\n", slot, irq, (unsigned long)base_addr, siops);
  210. printk(KERN_NOTICE "NCR Q720: On board ram %dk\n", mem_size/1024);
  211. p->dev = dev;
  212. p->mem_base = mem_base;
  213. p->phys_mem_base = base_addr;
  214. p->mem_size = mem_size;
  215. p->irq = irq;
  216. p->siops = siops;
  217. if (request_irq(irq, NCR_Q720_intr, IRQF_SHARED, "NCR_Q720", p)) {
  218. printk(KERN_ERR "NCR_Q720: request irq %d failed\n", irq);
  219. goto out_release;
  220. }
  221. /* disable all the siop interrupts */
  222. for(i = 0; i < siops; i++) {
  223. void __iomem *reg_scsr1 = mem_base + NCR_Q720_CHIP_REGISTER_OFFSET
  224. + i*NCR_Q720_SIOP_SHIFT + NCR_Q720_SCSR_OFFSET + 1;
  225. __u8 scsr1 = readb(reg_scsr1);
  226. scsr1 |= 0x01;
  227. writeb(scsr1, reg_scsr1);
  228. }
  229. /* plumb in all 720 chips */
  230. for (i = 0; i < siops; i++) {
  231. void __iomem *siop_v_base = mem_base + NCR_Q720_CHIP_REGISTER_OFFSET
  232. + i*NCR_Q720_SIOP_SHIFT;
  233. __u32 siop_p_base = base_addr + NCR_Q720_CHIP_REGISTER_OFFSET
  234. + i*NCR_Q720_SIOP_SHIFT;
  235. __u16 port = io_base + NCR_Q720_CHIP_REGISTER_OFFSET
  236. + i*NCR_Q720_SIOP_SHIFT;
  237. int err;
  238. outb(0xff, port + 0x40);
  239. outb(0x07, port + 0x41);
  240. if ((err = NCR_Q720_probe_one(p, i, irq, slot,
  241. siop_p_base, siop_v_base)) != 0)
  242. printk("Q720: SIOP%d: probe failed, error = %d\n",
  243. i, err);
  244. else
  245. found++;
  246. }
  247. if (!found) {
  248. kfree(p);
  249. return -ENODEV;
  250. }
  251. mca_device_set_claim(mca_dev, 1);
  252. mca_device_set_name(mca_dev, "NCR_Q720");
  253. dev_set_drvdata(dev, p);
  254. return 0;
  255. out_release:
  256. dma_release_declared_memory(dev);
  257. out_release_region:
  258. release_mem_region(base_addr, mem_size);
  259. out_free:
  260. kfree(p);
  261. return -ENODEV;
  262. }
  263. static void __exit
  264. NCR_Q720_remove_one(struct Scsi_Host *host)
  265. {
  266. scsi_remove_host(host);
  267. ncr53c8xx_release(host);
  268. }
  269. static int __exit
  270. NCR_Q720_remove(struct device *dev)
  271. {
  272. struct NCR_Q720_private *p = dev_get_drvdata(dev);
  273. int i;
  274. for (i = 0; i < p->siops; i++)
  275. if(p->hosts[i])
  276. NCR_Q720_remove_one(p->hosts[i]);
  277. dma_release_declared_memory(dev);
  278. release_mem_region(p->phys_mem_base, p->mem_size);
  279. free_irq(p->irq, p);
  280. kfree(p);
  281. return 0;
  282. }
  283. static short NCR_Q720_id_table[] = { NCR_Q720_MCA_ID, 0 };
  284. static struct mca_driver NCR_Q720_driver = {
  285. .id_table = NCR_Q720_id_table,
  286. .driver = {
  287. .name = "NCR_Q720",
  288. .bus = &mca_bus_type,
  289. .probe = NCR_Q720_probe,
  290. .remove = __devexit_p(NCR_Q720_remove),
  291. },
  292. };
  293. static int __init
  294. NCR_Q720_init(void)
  295. {
  296. int ret = ncr53c8xx_init();
  297. if (!ret)
  298. ret = mca_register_driver(&NCR_Q720_driver);
  299. if (ret)
  300. ncr53c8xx_exit();
  301. return ret;
  302. }
  303. static void __exit
  304. NCR_Q720_exit(void)
  305. {
  306. mca_unregister_driver(&NCR_Q720_driver);
  307. ncr53c8xx_exit();
  308. }
  309. module_init(NCR_Q720_init);
  310. module_exit(NCR_Q720_exit);