rtc-vr41xx.c 10 KB

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  1. /*
  2. * Driver for NEC VR4100 series Real Time Clock unit.
  3. *
  4. * Copyright (C) 2003-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #include <linux/err.h>
  21. #include <linux/fs.h>
  22. #include <linux/init.h>
  23. #include <linux/ioport.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/module.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/rtc.h>
  28. #include <linux/spinlock.h>
  29. #include <linux/types.h>
  30. #include <asm/div64.h>
  31. #include <asm/io.h>
  32. #include <asm/uaccess.h>
  33. MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
  34. MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
  35. MODULE_LICENSE("GPL v2");
  36. /* RTC 1 registers */
  37. #define ETIMELREG 0x00
  38. #define ETIMEMREG 0x02
  39. #define ETIMEHREG 0x04
  40. /* RFU */
  41. #define ECMPLREG 0x08
  42. #define ECMPMREG 0x0a
  43. #define ECMPHREG 0x0c
  44. /* RFU */
  45. #define RTCL1LREG 0x10
  46. #define RTCL1HREG 0x12
  47. #define RTCL1CNTLREG 0x14
  48. #define RTCL1CNTHREG 0x16
  49. #define RTCL2LREG 0x18
  50. #define RTCL2HREG 0x1a
  51. #define RTCL2CNTLREG 0x1c
  52. #define RTCL2CNTHREG 0x1e
  53. /* RTC 2 registers */
  54. #define TCLKLREG 0x00
  55. #define TCLKHREG 0x02
  56. #define TCLKCNTLREG 0x04
  57. #define TCLKCNTHREG 0x06
  58. /* RFU */
  59. #define RTCINTREG 0x1e
  60. #define TCLOCK_INT 0x08
  61. #define RTCLONG2_INT 0x04
  62. #define RTCLONG1_INT 0x02
  63. #define ELAPSEDTIME_INT 0x01
  64. #define RTC_FREQUENCY 32768
  65. #define MAX_PERIODIC_RATE 6553
  66. static void __iomem *rtc1_base;
  67. static void __iomem *rtc2_base;
  68. #define rtc1_read(offset) readw(rtc1_base + (offset))
  69. #define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
  70. #define rtc2_read(offset) readw(rtc2_base + (offset))
  71. #define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
  72. static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
  73. static DEFINE_SPINLOCK(rtc_lock);
  74. static char rtc_name[] = "RTC";
  75. static unsigned long periodic_count;
  76. static unsigned int alarm_enabled;
  77. static int aie_irq = -1;
  78. static int pie_irq = -1;
  79. static inline unsigned long read_elapsed_second(void)
  80. {
  81. unsigned long first_low, first_mid, first_high;
  82. unsigned long second_low, second_mid, second_high;
  83. do {
  84. first_low = rtc1_read(ETIMELREG);
  85. first_mid = rtc1_read(ETIMEMREG);
  86. first_high = rtc1_read(ETIMEHREG);
  87. second_low = rtc1_read(ETIMELREG);
  88. second_mid = rtc1_read(ETIMEMREG);
  89. second_high = rtc1_read(ETIMEHREG);
  90. } while (first_low != second_low || first_mid != second_mid ||
  91. first_high != second_high);
  92. return (first_high << 17) | (first_mid << 1) | (first_low >> 15);
  93. }
  94. static inline void write_elapsed_second(unsigned long sec)
  95. {
  96. spin_lock_irq(&rtc_lock);
  97. rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
  98. rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
  99. rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
  100. spin_unlock_irq(&rtc_lock);
  101. }
  102. static void vr41xx_rtc_release(struct device *dev)
  103. {
  104. spin_lock_irq(&rtc_lock);
  105. rtc1_write(ECMPLREG, 0);
  106. rtc1_write(ECMPMREG, 0);
  107. rtc1_write(ECMPHREG, 0);
  108. rtc1_write(RTCL1LREG, 0);
  109. rtc1_write(RTCL1HREG, 0);
  110. spin_unlock_irq(&rtc_lock);
  111. disable_irq(aie_irq);
  112. disable_irq(pie_irq);
  113. }
  114. static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
  115. {
  116. unsigned long epoch_sec, elapsed_sec;
  117. epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
  118. elapsed_sec = read_elapsed_second();
  119. rtc_time_to_tm(epoch_sec + elapsed_sec, time);
  120. return 0;
  121. }
  122. static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
  123. {
  124. unsigned long epoch_sec, current_sec;
  125. epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
  126. current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
  127. time->tm_hour, time->tm_min, time->tm_sec);
  128. write_elapsed_second(current_sec - epoch_sec);
  129. return 0;
  130. }
  131. static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  132. {
  133. unsigned long low, mid, high;
  134. struct rtc_time *time = &wkalrm->time;
  135. spin_lock_irq(&rtc_lock);
  136. low = rtc1_read(ECMPLREG);
  137. mid = rtc1_read(ECMPMREG);
  138. high = rtc1_read(ECMPHREG);
  139. wkalrm->enabled = alarm_enabled;
  140. spin_unlock_irq(&rtc_lock);
  141. rtc_time_to_tm((high << 17) | (mid << 1) | (low >> 15), time);
  142. return 0;
  143. }
  144. static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  145. {
  146. unsigned long alarm_sec;
  147. struct rtc_time *time = &wkalrm->time;
  148. alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
  149. time->tm_hour, time->tm_min, time->tm_sec);
  150. spin_lock_irq(&rtc_lock);
  151. if (alarm_enabled)
  152. disable_irq(aie_irq);
  153. rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
  154. rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
  155. rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
  156. if (wkalrm->enabled)
  157. enable_irq(aie_irq);
  158. alarm_enabled = wkalrm->enabled;
  159. spin_unlock_irq(&rtc_lock);
  160. return 0;
  161. }
  162. static int vr41xx_rtc_irq_set_freq(struct device *dev, int freq)
  163. {
  164. unsigned long count;
  165. count = RTC_FREQUENCY;
  166. do_div(count, freq);
  167. periodic_count = count;
  168. spin_lock_irq(&rtc_lock);
  169. rtc1_write(RTCL1LREG, count);
  170. rtc1_write(RTCL1HREG, count >> 16);
  171. spin_unlock_irq(&rtc_lock);
  172. return 0;
  173. }
  174. static int vr41xx_rtc_irq_set_state(struct device *dev, int enabled)
  175. {
  176. if (enabled)
  177. enable_irq(pie_irq);
  178. else
  179. disable_irq(pie_irq);
  180. return 0;
  181. }
  182. static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
  183. {
  184. switch (cmd) {
  185. case RTC_AIE_ON:
  186. spin_lock_irq(&rtc_lock);
  187. if (!alarm_enabled) {
  188. enable_irq(aie_irq);
  189. alarm_enabled = 1;
  190. }
  191. spin_unlock_irq(&rtc_lock);
  192. break;
  193. case RTC_AIE_OFF:
  194. spin_lock_irq(&rtc_lock);
  195. if (alarm_enabled) {
  196. disable_irq(aie_irq);
  197. alarm_enabled = 0;
  198. }
  199. spin_unlock_irq(&rtc_lock);
  200. break;
  201. case RTC_EPOCH_READ:
  202. return put_user(epoch, (unsigned long __user *)arg);
  203. case RTC_EPOCH_SET:
  204. /* Doesn't support before 1900 */
  205. if (arg < 1900)
  206. return -EINVAL;
  207. epoch = arg;
  208. break;
  209. default:
  210. return -ENOIOCTLCMD;
  211. }
  212. return 0;
  213. }
  214. static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
  215. {
  216. struct platform_device *pdev = (struct platform_device *)dev_id;
  217. struct rtc_device *rtc = platform_get_drvdata(pdev);
  218. rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
  219. rtc_update_irq(rtc, 1, RTC_AF);
  220. return IRQ_HANDLED;
  221. }
  222. static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
  223. {
  224. struct platform_device *pdev = (struct platform_device *)dev_id;
  225. struct rtc_device *rtc = platform_get_drvdata(pdev);
  226. unsigned long count = periodic_count;
  227. rtc2_write(RTCINTREG, RTCLONG1_INT);
  228. rtc1_write(RTCL1LREG, count);
  229. rtc1_write(RTCL1HREG, count >> 16);
  230. rtc_update_irq(rtc, 1, RTC_PF);
  231. return IRQ_HANDLED;
  232. }
  233. static const struct rtc_class_ops vr41xx_rtc_ops = {
  234. .release = vr41xx_rtc_release,
  235. .ioctl = vr41xx_rtc_ioctl,
  236. .read_time = vr41xx_rtc_read_time,
  237. .set_time = vr41xx_rtc_set_time,
  238. .read_alarm = vr41xx_rtc_read_alarm,
  239. .set_alarm = vr41xx_rtc_set_alarm,
  240. .irq_set_freq = vr41xx_rtc_irq_set_freq,
  241. .irq_set_state = vr41xx_rtc_irq_set_state,
  242. };
  243. static int __devinit rtc_probe(struct platform_device *pdev)
  244. {
  245. struct resource *res;
  246. struct rtc_device *rtc;
  247. int retval;
  248. if (pdev->num_resources != 4)
  249. return -EBUSY;
  250. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  251. if (!res)
  252. return -EBUSY;
  253. rtc1_base = ioremap(res->start, res->end - res->start + 1);
  254. if (!rtc1_base)
  255. return -EBUSY;
  256. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  257. if (!res) {
  258. retval = -EBUSY;
  259. goto err_rtc1_iounmap;
  260. }
  261. rtc2_base = ioremap(res->start, res->end - res->start + 1);
  262. if (!rtc2_base) {
  263. retval = -EBUSY;
  264. goto err_rtc1_iounmap;
  265. }
  266. rtc = rtc_device_register(rtc_name, &pdev->dev, &vr41xx_rtc_ops, THIS_MODULE);
  267. if (IS_ERR(rtc)) {
  268. retval = PTR_ERR(rtc);
  269. goto err_iounmap_all;
  270. }
  271. rtc->max_user_freq = MAX_PERIODIC_RATE;
  272. spin_lock_irq(&rtc_lock);
  273. rtc1_write(ECMPLREG, 0);
  274. rtc1_write(ECMPMREG, 0);
  275. rtc1_write(ECMPHREG, 0);
  276. rtc1_write(RTCL1LREG, 0);
  277. rtc1_write(RTCL1HREG, 0);
  278. spin_unlock_irq(&rtc_lock);
  279. aie_irq = platform_get_irq(pdev, 0);
  280. if (aie_irq < 0 || aie_irq >= NR_IRQS) {
  281. retval = -EBUSY;
  282. goto err_device_unregister;
  283. }
  284. retval = request_irq(aie_irq, elapsedtime_interrupt, IRQF_DISABLED,
  285. "elapsed_time", pdev);
  286. if (retval < 0)
  287. goto err_device_unregister;
  288. pie_irq = platform_get_irq(pdev, 1);
  289. if (pie_irq < 0 || pie_irq >= NR_IRQS)
  290. goto err_free_irq;
  291. retval = request_irq(pie_irq, rtclong1_interrupt, IRQF_DISABLED,
  292. "rtclong1", pdev);
  293. if (retval < 0)
  294. goto err_free_irq;
  295. platform_set_drvdata(pdev, rtc);
  296. disable_irq(aie_irq);
  297. disable_irq(pie_irq);
  298. printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n");
  299. return 0;
  300. err_free_irq:
  301. free_irq(aie_irq, pdev);
  302. err_device_unregister:
  303. rtc_device_unregister(rtc);
  304. err_iounmap_all:
  305. iounmap(rtc2_base);
  306. rtc2_base = NULL;
  307. err_rtc1_iounmap:
  308. iounmap(rtc1_base);
  309. rtc1_base = NULL;
  310. return retval;
  311. }
  312. static int __devexit rtc_remove(struct platform_device *pdev)
  313. {
  314. struct rtc_device *rtc;
  315. rtc = platform_get_drvdata(pdev);
  316. if (rtc)
  317. rtc_device_unregister(rtc);
  318. platform_set_drvdata(pdev, NULL);
  319. free_irq(aie_irq, pdev);
  320. free_irq(pie_irq, pdev);
  321. if (rtc1_base)
  322. iounmap(rtc1_base);
  323. if (rtc2_base)
  324. iounmap(rtc2_base);
  325. return 0;
  326. }
  327. /* work with hotplug and coldplug */
  328. MODULE_ALIAS("platform:RTC");
  329. static struct platform_driver rtc_platform_driver = {
  330. .probe = rtc_probe,
  331. .remove = __devexit_p(rtc_remove),
  332. .driver = {
  333. .name = rtc_name,
  334. .owner = THIS_MODULE,
  335. },
  336. };
  337. static int __init vr41xx_rtc_init(void)
  338. {
  339. return platform_driver_register(&rtc_platform_driver);
  340. }
  341. static void __exit vr41xx_rtc_exit(void)
  342. {
  343. platform_driver_unregister(&rtc_platform_driver);
  344. }
  345. module_init(vr41xx_rtc_init);
  346. module_exit(vr41xx_rtc_exit);