i82092.c 18 KB

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  1. /*
  2. * Driver for Intel I82092AA PCI-PCMCIA bridge.
  3. *
  4. * (C) 2001 Red Hat, Inc.
  5. *
  6. * Author: Arjan Van De Ven <arjanv@redhat.com>
  7. * Loosly based on i82365.c from the pcmcia-cs package
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/pci.h>
  12. #include <linux/init.h>
  13. #include <linux/workqueue.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/device.h>
  16. #include <pcmcia/cs_types.h>
  17. #include <pcmcia/ss.h>
  18. #include <pcmcia/cs.h>
  19. #include <asm/system.h>
  20. #include <asm/io.h>
  21. #include "i82092aa.h"
  22. #include "i82365.h"
  23. MODULE_LICENSE("GPL");
  24. /* PCI core routines */
  25. static struct pci_device_id i82092aa_pci_ids[] = {
  26. {
  27. .vendor = PCI_VENDOR_ID_INTEL,
  28. .device = PCI_DEVICE_ID_INTEL_82092AA_0,
  29. .subvendor = PCI_ANY_ID,
  30. .subdevice = PCI_ANY_ID,
  31. },
  32. {}
  33. };
  34. MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids);
  35. #ifdef CONFIG_PM
  36. static int i82092aa_socket_suspend (struct pci_dev *dev, pm_message_t state)
  37. {
  38. return pcmcia_socket_dev_suspend(&dev->dev, state);
  39. }
  40. static int i82092aa_socket_resume (struct pci_dev *dev)
  41. {
  42. return pcmcia_socket_dev_resume(&dev->dev);
  43. }
  44. #endif
  45. static struct pci_driver i82092aa_pci_driver = {
  46. .name = "i82092aa",
  47. .id_table = i82092aa_pci_ids,
  48. .probe = i82092aa_pci_probe,
  49. .remove = __devexit_p(i82092aa_pci_remove),
  50. #ifdef CONFIG_PM
  51. .suspend = i82092aa_socket_suspend,
  52. .resume = i82092aa_socket_resume,
  53. #endif
  54. };
  55. /* the pccard structure and its functions */
  56. static struct pccard_operations i82092aa_operations = {
  57. .init = i82092aa_init,
  58. .get_status = i82092aa_get_status,
  59. .set_socket = i82092aa_set_socket,
  60. .set_io_map = i82092aa_set_io_map,
  61. .set_mem_map = i82092aa_set_mem_map,
  62. };
  63. /* The card can do upto 4 sockets, allocate a structure for each of them */
  64. struct socket_info {
  65. int number;
  66. int card_state; /* 0 = no socket,
  67. 1 = empty socket,
  68. 2 = card but not initialized,
  69. 3 = operational card */
  70. unsigned int io_base; /* base io address of the socket */
  71. struct pcmcia_socket socket;
  72. struct pci_dev *dev; /* The PCI device for the socket */
  73. };
  74. #define MAX_SOCKETS 4
  75. static struct socket_info sockets[MAX_SOCKETS];
  76. static int socket_count; /* shortcut */
  77. static int __devinit i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
  78. {
  79. unsigned char configbyte;
  80. int i, ret;
  81. enter("i82092aa_pci_probe");
  82. if ((ret = pci_enable_device(dev)))
  83. return ret;
  84. pci_read_config_byte(dev, 0x40, &configbyte); /* PCI Configuration Control */
  85. switch(configbyte&6) {
  86. case 0:
  87. socket_count = 2;
  88. break;
  89. case 2:
  90. socket_count = 1;
  91. break;
  92. case 4:
  93. case 6:
  94. socket_count = 4;
  95. break;
  96. default:
  97. printk(KERN_ERR "i82092aa: Oops, you did something we didn't think of.\n");
  98. ret = -EIO;
  99. goto err_out_disable;
  100. }
  101. printk(KERN_INFO "i82092aa: configured as a %d socket device.\n", socket_count);
  102. if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) {
  103. ret = -EBUSY;
  104. goto err_out_disable;
  105. }
  106. for (i = 0;i<socket_count;i++) {
  107. sockets[i].card_state = 1; /* 1 = present but empty */
  108. sockets[i].io_base = pci_resource_start(dev, 0);
  109. sockets[i].socket.features |= SS_CAP_PCCARD;
  110. sockets[i].socket.map_size = 0x1000;
  111. sockets[i].socket.irq_mask = 0;
  112. sockets[i].socket.pci_irq = dev->irq;
  113. sockets[i].socket.owner = THIS_MODULE;
  114. sockets[i].number = i;
  115. if (card_present(i)) {
  116. sockets[i].card_state = 3;
  117. dprintk(KERN_DEBUG "i82092aa: slot %i is occupied\n",i);
  118. } else {
  119. dprintk(KERN_DEBUG "i82092aa: slot %i is vacant\n",i);
  120. }
  121. }
  122. /* Now, specifiy that all interrupts are to be done as PCI interrupts */
  123. configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */
  124. pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */
  125. /* Register the interrupt handler */
  126. dprintk(KERN_DEBUG "Requesting interrupt %i \n",dev->irq);
  127. if ((ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED, "i82092aa", i82092aa_interrupt))) {
  128. printk(KERN_ERR "i82092aa: Failed to register IRQ %d, aborting\n", dev->irq);
  129. goto err_out_free_res;
  130. }
  131. pci_set_drvdata(dev, &sockets[i].socket);
  132. for (i = 0; i<socket_count; i++) {
  133. sockets[i].socket.dev.parent = &dev->dev;
  134. sockets[i].socket.ops = &i82092aa_operations;
  135. sockets[i].socket.resource_ops = &pccard_nonstatic_ops;
  136. ret = pcmcia_register_socket(&sockets[i].socket);
  137. if (ret) {
  138. goto err_out_free_sockets;
  139. }
  140. }
  141. leave("i82092aa_pci_probe");
  142. return 0;
  143. err_out_free_sockets:
  144. if (i) {
  145. for (i--;i>=0;i--) {
  146. pcmcia_unregister_socket(&sockets[i].socket);
  147. }
  148. }
  149. free_irq(dev->irq, i82092aa_interrupt);
  150. err_out_free_res:
  151. release_region(pci_resource_start(dev, 0), 2);
  152. err_out_disable:
  153. pci_disable_device(dev);
  154. return ret;
  155. }
  156. static void __devexit i82092aa_pci_remove(struct pci_dev *dev)
  157. {
  158. struct pcmcia_socket *socket = pci_get_drvdata(dev);
  159. enter("i82092aa_pci_remove");
  160. free_irq(dev->irq, i82092aa_interrupt);
  161. if (socket)
  162. pcmcia_unregister_socket(socket);
  163. leave("i82092aa_pci_remove");
  164. }
  165. static DEFINE_SPINLOCK(port_lock);
  166. /* basic value read/write functions */
  167. static unsigned char indirect_read(int socket, unsigned short reg)
  168. {
  169. unsigned short int port;
  170. unsigned char val;
  171. unsigned long flags;
  172. spin_lock_irqsave(&port_lock,flags);
  173. reg += socket * 0x40;
  174. port = sockets[socket].io_base;
  175. outb(reg,port);
  176. val = inb(port+1);
  177. spin_unlock_irqrestore(&port_lock,flags);
  178. return val;
  179. }
  180. #if 0
  181. static unsigned short indirect_read16(int socket, unsigned short reg)
  182. {
  183. unsigned short int port;
  184. unsigned short tmp;
  185. unsigned long flags;
  186. spin_lock_irqsave(&port_lock,flags);
  187. reg = reg + socket * 0x40;
  188. port = sockets[socket].io_base;
  189. outb(reg,port);
  190. tmp = inb(port+1);
  191. reg++;
  192. outb(reg,port);
  193. tmp = tmp | (inb(port+1)<<8);
  194. spin_unlock_irqrestore(&port_lock,flags);
  195. return tmp;
  196. }
  197. #endif
  198. static void indirect_write(int socket, unsigned short reg, unsigned char value)
  199. {
  200. unsigned short int port;
  201. unsigned long flags;
  202. spin_lock_irqsave(&port_lock,flags);
  203. reg = reg + socket * 0x40;
  204. port = sockets[socket].io_base;
  205. outb(reg,port);
  206. outb(value,port+1);
  207. spin_unlock_irqrestore(&port_lock,flags);
  208. }
  209. static void indirect_setbit(int socket, unsigned short reg, unsigned char mask)
  210. {
  211. unsigned short int port;
  212. unsigned char val;
  213. unsigned long flags;
  214. spin_lock_irqsave(&port_lock,flags);
  215. reg = reg + socket * 0x40;
  216. port = sockets[socket].io_base;
  217. outb(reg,port);
  218. val = inb(port+1);
  219. val |= mask;
  220. outb(reg,port);
  221. outb(val,port+1);
  222. spin_unlock_irqrestore(&port_lock,flags);
  223. }
  224. static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask)
  225. {
  226. unsigned short int port;
  227. unsigned char val;
  228. unsigned long flags;
  229. spin_lock_irqsave(&port_lock,flags);
  230. reg = reg + socket * 0x40;
  231. port = sockets[socket].io_base;
  232. outb(reg,port);
  233. val = inb(port+1);
  234. val &= ~mask;
  235. outb(reg,port);
  236. outb(val,port+1);
  237. spin_unlock_irqrestore(&port_lock,flags);
  238. }
  239. static void indirect_write16(int socket, unsigned short reg, unsigned short value)
  240. {
  241. unsigned short int port;
  242. unsigned char val;
  243. unsigned long flags;
  244. spin_lock_irqsave(&port_lock,flags);
  245. reg = reg + socket * 0x40;
  246. port = sockets[socket].io_base;
  247. outb(reg,port);
  248. val = value & 255;
  249. outb(val,port+1);
  250. reg++;
  251. outb(reg,port);
  252. val = value>>8;
  253. outb(val,port+1);
  254. spin_unlock_irqrestore(&port_lock,flags);
  255. }
  256. /* simple helper functions */
  257. /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */
  258. static int cycle_time = 120;
  259. static int to_cycles(int ns)
  260. {
  261. if (cycle_time!=0)
  262. return ns/cycle_time;
  263. else
  264. return 0;
  265. }
  266. /* Interrupt handler functionality */
  267. static irqreturn_t i82092aa_interrupt(int irq, void *dev)
  268. {
  269. int i;
  270. int loopcount = 0;
  271. int handled = 0;
  272. unsigned int events, active=0;
  273. /* enter("i82092aa_interrupt");*/
  274. while (1) {
  275. loopcount++;
  276. if (loopcount>20) {
  277. printk(KERN_ERR "i82092aa: infinite eventloop in interrupt \n");
  278. break;
  279. }
  280. active = 0;
  281. for (i=0;i<socket_count;i++) {
  282. int csc;
  283. if (sockets[i].card_state==0) /* Inactive socket, should not happen */
  284. continue;
  285. csc = indirect_read(i,I365_CSC); /* card status change register */
  286. if (csc==0) /* no events on this socket */
  287. continue;
  288. handled = 1;
  289. events = 0;
  290. if (csc & I365_CSC_DETECT) {
  291. events |= SS_DETECT;
  292. printk("Card detected in socket %i!\n",i);
  293. }
  294. if (indirect_read(i,I365_INTCTL) & I365_PC_IOCARD) {
  295. /* For IO/CARDS, bit 0 means "read the card" */
  296. events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
  297. } else {
  298. /* Check for battery/ready events */
  299. events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
  300. events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
  301. events |= (csc & I365_CSC_READY) ? SS_READY : 0;
  302. }
  303. if (events) {
  304. pcmcia_parse_events(&sockets[i].socket, events);
  305. }
  306. active |= events;
  307. }
  308. if (active==0) /* no more events to handle */
  309. break;
  310. }
  311. return IRQ_RETVAL(handled);
  312. /* leave("i82092aa_interrupt");*/
  313. }
  314. /* socket functions */
  315. static int card_present(int socketno)
  316. {
  317. unsigned int val;
  318. enter("card_present");
  319. if ((socketno<0) || (socketno >= MAX_SOCKETS))
  320. return 0;
  321. if (sockets[socketno].io_base == 0)
  322. return 0;
  323. val = indirect_read(socketno, 1); /* Interface status register */
  324. if ((val&12)==12) {
  325. leave("card_present 1");
  326. return 1;
  327. }
  328. leave("card_present 0");
  329. return 0;
  330. }
  331. static void set_bridge_state(int sock)
  332. {
  333. enter("set_bridge_state");
  334. indirect_write(sock, I365_GBLCTL,0x00);
  335. indirect_write(sock, I365_GENCTL,0x00);
  336. indirect_setbit(sock, I365_INTCTL,0x08);
  337. leave("set_bridge_state");
  338. }
  339. static int i82092aa_init(struct pcmcia_socket *sock)
  340. {
  341. int i;
  342. struct resource res = { .start = 0, .end = 0x0fff };
  343. pccard_io_map io = { 0, 0, 0, 0, 1 };
  344. pccard_mem_map mem = { .res = &res, };
  345. enter("i82092aa_init");
  346. for (i = 0; i < 2; i++) {
  347. io.map = i;
  348. i82092aa_set_io_map(sock, &io);
  349. }
  350. for (i = 0; i < 5; i++) {
  351. mem.map = i;
  352. i82092aa_set_mem_map(sock, &mem);
  353. }
  354. leave("i82092aa_init");
  355. return 0;
  356. }
  357. static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value)
  358. {
  359. unsigned int sock = container_of(socket, struct socket_info, socket)->number;
  360. unsigned int status;
  361. enter("i82092aa_get_status");
  362. status = indirect_read(sock,I365_STATUS); /* Interface Status Register */
  363. *value = 0;
  364. if ((status & I365_CS_DETECT) == I365_CS_DETECT) {
  365. *value |= SS_DETECT;
  366. }
  367. /* IO cards have a different meaning of bits 0,1 */
  368. /* Also notice the inverse-logic on the bits */
  369. if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) {
  370. /* IO card */
  371. if (!(status & I365_CS_STSCHG))
  372. *value |= SS_STSCHG;
  373. } else { /* non I/O card */
  374. if (!(status & I365_CS_BVD1))
  375. *value |= SS_BATDEAD;
  376. if (!(status & I365_CS_BVD2))
  377. *value |= SS_BATWARN;
  378. }
  379. if (status & I365_CS_WRPROT)
  380. (*value) |= SS_WRPROT; /* card is write protected */
  381. if (status & I365_CS_READY)
  382. (*value) |= SS_READY; /* card is not busy */
  383. if (status & I365_CS_POWERON)
  384. (*value) |= SS_POWERON; /* power is applied to the card */
  385. leave("i82092aa_get_status");
  386. return 0;
  387. }
  388. static int i82092aa_set_socket(struct pcmcia_socket *socket, socket_state_t *state)
  389. {
  390. unsigned int sock = container_of(socket, struct socket_info, socket)->number;
  391. unsigned char reg;
  392. enter("i82092aa_set_socket");
  393. /* First, set the global controller options */
  394. set_bridge_state(sock);
  395. /* Values for the IGENC register */
  396. reg = 0;
  397. if (!(state->flags & SS_RESET)) /* The reset bit has "inverse" logic */
  398. reg = reg | I365_PC_RESET;
  399. if (state->flags & SS_IOCARD)
  400. reg = reg | I365_PC_IOCARD;
  401. indirect_write(sock,I365_INTCTL,reg); /* IGENC, Interrupt and General Control Register */
  402. /* Power registers */
  403. reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */
  404. if (state->flags & SS_PWR_AUTO) {
  405. printk("Auto power\n");
  406. reg |= I365_PWR_AUTO; /* automatic power mngmnt */
  407. }
  408. if (state->flags & SS_OUTPUT_ENA) {
  409. printk("Power Enabled \n");
  410. reg |= I365_PWR_OUT; /* enable power */
  411. }
  412. switch (state->Vcc) {
  413. case 0:
  414. break;
  415. case 50:
  416. printk("setting voltage to Vcc to 5V on socket %i\n",sock);
  417. reg |= I365_VCC_5V;
  418. break;
  419. default:
  420. printk("i82092aa: i82092aa_set_socket called with invalid VCC power value: %i ", state->Vcc);
  421. leave("i82092aa_set_socket");
  422. return -EINVAL;
  423. }
  424. switch (state->Vpp) {
  425. case 0:
  426. printk("not setting Vpp on socket %i\n",sock);
  427. break;
  428. case 50:
  429. printk("setting Vpp to 5.0 for socket %i\n",sock);
  430. reg |= I365_VPP1_5V | I365_VPP2_5V;
  431. break;
  432. case 120:
  433. printk("setting Vpp to 12.0\n");
  434. reg |= I365_VPP1_12V | I365_VPP2_12V;
  435. break;
  436. default:
  437. printk("i82092aa: i82092aa_set_socket called with invalid VPP power value: %i ", state->Vcc);
  438. leave("i82092aa_set_socket");
  439. return -EINVAL;
  440. }
  441. if (reg != indirect_read(sock,I365_POWER)) /* only write if changed */
  442. indirect_write(sock,I365_POWER,reg);
  443. /* Enable specific interrupt events */
  444. reg = 0x00;
  445. if (state->csc_mask & SS_DETECT) {
  446. reg |= I365_CSC_DETECT;
  447. }
  448. if (state->flags & SS_IOCARD) {
  449. if (state->csc_mask & SS_STSCHG)
  450. reg |= I365_CSC_STSCHG;
  451. } else {
  452. if (state->csc_mask & SS_BATDEAD)
  453. reg |= I365_CSC_BVD1;
  454. if (state->csc_mask & SS_BATWARN)
  455. reg |= I365_CSC_BVD2;
  456. if (state->csc_mask & SS_READY)
  457. reg |= I365_CSC_READY;
  458. }
  459. /* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/
  460. indirect_write(sock,I365_CSCINT,reg);
  461. (void)indirect_read(sock,I365_CSC);
  462. leave("i82092aa_set_socket");
  463. return 0;
  464. }
  465. static int i82092aa_set_io_map(struct pcmcia_socket *socket, struct pccard_io_map *io)
  466. {
  467. unsigned int sock = container_of(socket, struct socket_info, socket)->number;
  468. unsigned char map, ioctl;
  469. enter("i82092aa_set_io_map");
  470. map = io->map;
  471. /* Check error conditions */
  472. if (map > 1) {
  473. leave("i82092aa_set_io_map with invalid map");
  474. return -EINVAL;
  475. }
  476. if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)){
  477. leave("i82092aa_set_io_map with invalid io");
  478. return -EINVAL;
  479. }
  480. /* Turn off the window before changing anything */
  481. if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map))
  482. indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map));
  483. /* printk("set_io_map: Setting range to %x - %x \n",io->start,io->stop); */
  484. /* write the new values */
  485. indirect_write16(sock,I365_IO(map)+I365_W_START,io->start);
  486. indirect_write16(sock,I365_IO(map)+I365_W_STOP,io->stop);
  487. ioctl = indirect_read(sock,I365_IOCTL) & ~I365_IOCTL_MASK(map);
  488. if (io->flags & (MAP_16BIT|MAP_AUTOSZ))
  489. ioctl |= I365_IOCTL_16BIT(map);
  490. indirect_write(sock,I365_IOCTL,ioctl);
  491. /* Turn the window back on if needed */
  492. if (io->flags & MAP_ACTIVE)
  493. indirect_setbit(sock,I365_ADDRWIN,I365_ENA_IO(map));
  494. leave("i82092aa_set_io_map");
  495. return 0;
  496. }
  497. static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_map *mem)
  498. {
  499. struct socket_info *sock_info = container_of(socket, struct socket_info, socket);
  500. unsigned int sock = sock_info->number;
  501. struct pci_bus_region region;
  502. unsigned short base, i;
  503. unsigned char map;
  504. enter("i82092aa_set_mem_map");
  505. pcibios_resource_to_bus(sock_info->dev, &region, mem->res);
  506. map = mem->map;
  507. if (map > 4) {
  508. leave("i82092aa_set_mem_map: invalid map");
  509. return -EINVAL;
  510. }
  511. if ( (mem->card_start > 0x3ffffff) || (region.start > region.end) ||
  512. (mem->speed > 1000) ) {
  513. leave("i82092aa_set_mem_map: invalid address / speed");
  514. printk("invalid mem map for socket %i: %llx to %llx with a "
  515. "start of %x\n",
  516. sock,
  517. (unsigned long long)region.start,
  518. (unsigned long long)region.end,
  519. mem->card_start);
  520. return -EINVAL;
  521. }
  522. /* Turn off the window before changing anything */
  523. if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
  524. indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
  525. /* printk("set_mem_map: Setting map %i range to %x - %x on socket %i, speed is %i, active = %i \n",map, region.start,region.end,sock,mem->speed,mem->flags & MAP_ACTIVE); */
  526. /* write the start address */
  527. base = I365_MEM(map);
  528. i = (region.start >> 12) & 0x0fff;
  529. if (mem->flags & MAP_16BIT)
  530. i |= I365_MEM_16BIT;
  531. if (mem->flags & MAP_0WS)
  532. i |= I365_MEM_0WS;
  533. indirect_write16(sock,base+I365_W_START,i);
  534. /* write the stop address */
  535. i= (region.end >> 12) & 0x0fff;
  536. switch (to_cycles(mem->speed)) {
  537. case 0:
  538. break;
  539. case 1:
  540. i |= I365_MEM_WS0;
  541. break;
  542. case 2:
  543. i |= I365_MEM_WS1;
  544. break;
  545. default:
  546. i |= I365_MEM_WS1 | I365_MEM_WS0;
  547. break;
  548. }
  549. indirect_write16(sock,base+I365_W_STOP,i);
  550. /* card start */
  551. i = ((mem->card_start - region.start) >> 12) & 0x3fff;
  552. if (mem->flags & MAP_WRPROT)
  553. i |= I365_MEM_WRPROT;
  554. if (mem->flags & MAP_ATTRIB) {
  555. /* printk("requesting attribute memory for socket %i\n",sock);*/
  556. i |= I365_MEM_REG;
  557. } else {
  558. /* printk("requesting normal memory for socket %i\n",sock);*/
  559. }
  560. indirect_write16(sock,base+I365_W_OFF,i);
  561. /* Enable the window if necessary */
  562. if (mem->flags & MAP_ACTIVE)
  563. indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
  564. leave("i82092aa_set_mem_map");
  565. return 0;
  566. }
  567. static int i82092aa_module_init(void)
  568. {
  569. return pci_register_driver(&i82092aa_pci_driver);
  570. }
  571. static void i82092aa_module_exit(void)
  572. {
  573. enter("i82092aa_module_exit");
  574. pci_unregister_driver(&i82092aa_pci_driver);
  575. if (sockets[0].io_base>0)
  576. release_region(sockets[0].io_base, 2);
  577. leave("i82092aa_module_exit");
  578. }
  579. module_init(i82092aa_module_init);
  580. module_exit(i82092aa_module_exit);