p54pci.c 16 KB

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  1. /*
  2. * Linux device driver for PCI based Prism54
  3. *
  4. * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
  5. * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
  6. *
  7. * Based on the islsm (softmac prism54) driver, which is:
  8. * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <linux/firmware.h>
  17. #include <linux/etherdevice.h>
  18. #include <linux/delay.h>
  19. #include <linux/completion.h>
  20. #include <net/mac80211.h>
  21. #include "p54.h"
  22. #include "p54pci.h"
  23. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  24. MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  25. MODULE_LICENSE("GPL");
  26. MODULE_ALIAS("prism54pci");
  27. static struct pci_device_id p54p_table[] __devinitdata = {
  28. /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  29. { PCI_DEVICE(0x1260, 0x3890) },
  30. /* 3COM 3CRWE154G72 Wireless LAN adapter */
  31. { PCI_DEVICE(0x10b7, 0x6001) },
  32. /* Intersil PRISM Indigo Wireless LAN adapter */
  33. { PCI_DEVICE(0x1260, 0x3877) },
  34. /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  35. { PCI_DEVICE(0x1260, 0x3886) },
  36. { },
  37. };
  38. MODULE_DEVICE_TABLE(pci, p54p_table);
  39. static int p54p_upload_firmware(struct ieee80211_hw *dev)
  40. {
  41. struct p54p_priv *priv = dev->priv;
  42. const struct firmware *fw_entry = NULL;
  43. __le32 reg;
  44. int err;
  45. __le32 *data;
  46. u32 remains, left, device_addr;
  47. P54P_WRITE(int_enable, cpu_to_le32(0));
  48. P54P_READ(int_enable);
  49. udelay(10);
  50. reg = P54P_READ(ctrl_stat);
  51. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  52. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  53. P54P_WRITE(ctrl_stat, reg);
  54. P54P_READ(ctrl_stat);
  55. udelay(10);
  56. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  57. P54P_WRITE(ctrl_stat, reg);
  58. wmb();
  59. udelay(10);
  60. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  61. P54P_WRITE(ctrl_stat, reg);
  62. wmb();
  63. err = request_firmware(&fw_entry, "isl3886", &priv->pdev->dev);
  64. if (err) {
  65. printk(KERN_ERR "%s (p54pci): cannot find firmware "
  66. "(isl3886)\n", pci_name(priv->pdev));
  67. return err;
  68. }
  69. err = p54_parse_firmware(dev, fw_entry);
  70. if (err) {
  71. release_firmware(fw_entry);
  72. return err;
  73. }
  74. data = (__le32 *) fw_entry->data;
  75. remains = fw_entry->size;
  76. device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  77. while (remains) {
  78. u32 i = 0;
  79. left = min((u32)0x1000, remains);
  80. P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  81. P54P_READ(int_enable);
  82. device_addr += 0x1000;
  83. while (i < left) {
  84. P54P_WRITE(direct_mem_win[i], *data++);
  85. i += sizeof(u32);
  86. }
  87. remains -= left;
  88. P54P_READ(int_enable);
  89. }
  90. release_firmware(fw_entry);
  91. reg = P54P_READ(ctrl_stat);
  92. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
  93. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  94. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
  95. P54P_WRITE(ctrl_stat, reg);
  96. P54P_READ(ctrl_stat);
  97. udelay(10);
  98. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  99. P54P_WRITE(ctrl_stat, reg);
  100. wmb();
  101. udelay(10);
  102. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  103. P54P_WRITE(ctrl_stat, reg);
  104. wmb();
  105. udelay(10);
  106. /* wait for the firmware to boot properly */
  107. mdelay(100);
  108. return 0;
  109. }
  110. static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
  111. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  112. struct sk_buff **rx_buf)
  113. {
  114. struct p54p_priv *priv = dev->priv;
  115. struct p54p_ring_control *ring_control = priv->ring_control;
  116. u32 limit, idx, i;
  117. idx = le32_to_cpu(ring_control->host_idx[ring_index]);
  118. limit = idx;
  119. limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
  120. limit = ring_limit - limit;
  121. i = idx % ring_limit;
  122. while (limit-- > 1) {
  123. struct p54p_desc *desc = &ring[i];
  124. if (!desc->host_addr) {
  125. struct sk_buff *skb;
  126. dma_addr_t mapping;
  127. skb = dev_alloc_skb(priv->common.rx_mtu + 32);
  128. if (!skb)
  129. break;
  130. mapping = pci_map_single(priv->pdev,
  131. skb_tail_pointer(skb),
  132. priv->common.rx_mtu + 32,
  133. PCI_DMA_FROMDEVICE);
  134. desc->host_addr = cpu_to_le32(mapping);
  135. desc->device_addr = 0; // FIXME: necessary?
  136. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  137. desc->flags = 0;
  138. rx_buf[i] = skb;
  139. }
  140. i++;
  141. idx++;
  142. i %= ring_limit;
  143. }
  144. wmb();
  145. ring_control->host_idx[ring_index] = cpu_to_le32(idx);
  146. }
  147. static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
  148. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  149. struct sk_buff **rx_buf)
  150. {
  151. struct p54p_priv *priv = dev->priv;
  152. struct p54p_ring_control *ring_control = priv->ring_control;
  153. struct p54p_desc *desc;
  154. u32 idx, i;
  155. i = (*index) % ring_limit;
  156. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  157. idx %= ring_limit;
  158. while (i != idx) {
  159. u16 len;
  160. struct sk_buff *skb;
  161. desc = &ring[i];
  162. len = le16_to_cpu(desc->len);
  163. skb = rx_buf[i];
  164. if (!skb) {
  165. i++;
  166. i %= ring_limit;
  167. continue;
  168. }
  169. skb_put(skb, len);
  170. if (p54_rx(dev, skb)) {
  171. pci_unmap_single(priv->pdev,
  172. le32_to_cpu(desc->host_addr),
  173. priv->common.rx_mtu + 32,
  174. PCI_DMA_FROMDEVICE);
  175. rx_buf[i] = NULL;
  176. desc->host_addr = 0;
  177. } else {
  178. skb_trim(skb, 0);
  179. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  180. }
  181. i++;
  182. i %= ring_limit;
  183. }
  184. p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
  185. }
  186. /* caller must hold priv->lock */
  187. static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
  188. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  189. void **tx_buf)
  190. {
  191. struct p54p_priv *priv = dev->priv;
  192. struct p54p_ring_control *ring_control = priv->ring_control;
  193. struct p54p_desc *desc;
  194. u32 idx, i;
  195. i = (*index) % ring_limit;
  196. (*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
  197. idx %= ring_limit;
  198. while (i != idx) {
  199. desc = &ring[i];
  200. kfree(tx_buf[i]);
  201. tx_buf[i] = NULL;
  202. pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
  203. le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
  204. desc->host_addr = 0;
  205. desc->device_addr = 0;
  206. desc->len = 0;
  207. desc->flags = 0;
  208. i++;
  209. i %= ring_limit;
  210. }
  211. }
  212. static void p54p_rx_tasklet(unsigned long dev_id)
  213. {
  214. struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
  215. struct p54p_priv *priv = dev->priv;
  216. struct p54p_ring_control *ring_control = priv->ring_control;
  217. p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
  218. ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
  219. p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
  220. ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
  221. wmb();
  222. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  223. }
  224. static irqreturn_t p54p_interrupt(int irq, void *dev_id)
  225. {
  226. struct ieee80211_hw *dev = dev_id;
  227. struct p54p_priv *priv = dev->priv;
  228. struct p54p_ring_control *ring_control = priv->ring_control;
  229. __le32 reg;
  230. spin_lock(&priv->lock);
  231. reg = P54P_READ(int_ident);
  232. if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
  233. spin_unlock(&priv->lock);
  234. return IRQ_HANDLED;
  235. }
  236. P54P_WRITE(int_ack, reg);
  237. reg &= P54P_READ(int_enable);
  238. if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
  239. p54p_check_tx_ring(dev, &priv->tx_idx_mgmt,
  240. 3, ring_control->tx_mgmt,
  241. ARRAY_SIZE(ring_control->tx_mgmt),
  242. priv->tx_buf_mgmt);
  243. p54p_check_tx_ring(dev, &priv->tx_idx_data,
  244. 1, ring_control->tx_data,
  245. ARRAY_SIZE(ring_control->tx_data),
  246. priv->tx_buf_data);
  247. tasklet_schedule(&priv->rx_tasklet);
  248. } else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
  249. complete(&priv->boot_comp);
  250. spin_unlock(&priv->lock);
  251. return reg ? IRQ_HANDLED : IRQ_NONE;
  252. }
  253. static void p54p_tx(struct ieee80211_hw *dev, struct p54_control_hdr *data,
  254. size_t len, int free_on_tx)
  255. {
  256. struct p54p_priv *priv = dev->priv;
  257. struct p54p_ring_control *ring_control = priv->ring_control;
  258. unsigned long flags;
  259. struct p54p_desc *desc;
  260. dma_addr_t mapping;
  261. u32 device_idx, idx, i;
  262. spin_lock_irqsave(&priv->lock, flags);
  263. device_idx = le32_to_cpu(ring_control->device_idx[1]);
  264. idx = le32_to_cpu(ring_control->host_idx[1]);
  265. i = idx % ARRAY_SIZE(ring_control->tx_data);
  266. mapping = pci_map_single(priv->pdev, data, len, PCI_DMA_TODEVICE);
  267. desc = &ring_control->tx_data[i];
  268. desc->host_addr = cpu_to_le32(mapping);
  269. desc->device_addr = data->req_id;
  270. desc->len = cpu_to_le16(len);
  271. desc->flags = 0;
  272. wmb();
  273. ring_control->host_idx[1] = cpu_to_le32(idx + 1);
  274. if (free_on_tx)
  275. priv->tx_buf_data[i] = data;
  276. spin_unlock_irqrestore(&priv->lock, flags);
  277. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  278. P54P_READ(dev_int);
  279. /* FIXME: unlikely to happen because the device usually runs out of
  280. memory before we fill the ring up, but we can make it impossible */
  281. if (idx - device_idx > ARRAY_SIZE(ring_control->tx_data) - 2)
  282. printk(KERN_INFO "%s: tx overflow.\n", wiphy_name(dev->wiphy));
  283. }
  284. static int p54p_open(struct ieee80211_hw *dev)
  285. {
  286. struct p54p_priv *priv = dev->priv;
  287. int err;
  288. init_completion(&priv->boot_comp);
  289. err = request_irq(priv->pdev->irq, &p54p_interrupt,
  290. IRQF_SHARED, "p54pci", dev);
  291. if (err) {
  292. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  293. wiphy_name(dev->wiphy));
  294. return err;
  295. }
  296. memset(priv->ring_control, 0, sizeof(*priv->ring_control));
  297. err = p54p_upload_firmware(dev);
  298. if (err) {
  299. free_irq(priv->pdev->irq, dev);
  300. return err;
  301. }
  302. priv->rx_idx_data = priv->tx_idx_data = 0;
  303. priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
  304. p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
  305. ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
  306. p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
  307. ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
  308. P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
  309. P54P_READ(ring_control_base);
  310. wmb();
  311. udelay(10);
  312. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
  313. P54P_READ(int_enable);
  314. wmb();
  315. udelay(10);
  316. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  317. P54P_READ(dev_int);
  318. if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
  319. printk(KERN_ERR "%s: Cannot boot firmware!\n",
  320. wiphy_name(dev->wiphy));
  321. free_irq(priv->pdev->irq, dev);
  322. return -ETIMEDOUT;
  323. }
  324. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
  325. P54P_READ(int_enable);
  326. wmb();
  327. udelay(10);
  328. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  329. P54P_READ(dev_int);
  330. wmb();
  331. udelay(10);
  332. return 0;
  333. }
  334. static void p54p_stop(struct ieee80211_hw *dev)
  335. {
  336. struct p54p_priv *priv = dev->priv;
  337. struct p54p_ring_control *ring_control = priv->ring_control;
  338. unsigned int i;
  339. struct p54p_desc *desc;
  340. tasklet_kill(&priv->rx_tasklet);
  341. P54P_WRITE(int_enable, cpu_to_le32(0));
  342. P54P_READ(int_enable);
  343. udelay(10);
  344. free_irq(priv->pdev->irq, dev);
  345. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  346. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
  347. desc = &ring_control->rx_data[i];
  348. if (desc->host_addr)
  349. pci_unmap_single(priv->pdev,
  350. le32_to_cpu(desc->host_addr),
  351. priv->common.rx_mtu + 32,
  352. PCI_DMA_FROMDEVICE);
  353. kfree_skb(priv->rx_buf_data[i]);
  354. priv->rx_buf_data[i] = NULL;
  355. }
  356. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
  357. desc = &ring_control->rx_mgmt[i];
  358. if (desc->host_addr)
  359. pci_unmap_single(priv->pdev,
  360. le32_to_cpu(desc->host_addr),
  361. priv->common.rx_mtu + 32,
  362. PCI_DMA_FROMDEVICE);
  363. kfree_skb(priv->rx_buf_mgmt[i]);
  364. priv->rx_buf_mgmt[i] = NULL;
  365. }
  366. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
  367. desc = &ring_control->tx_data[i];
  368. if (desc->host_addr)
  369. pci_unmap_single(priv->pdev,
  370. le32_to_cpu(desc->host_addr),
  371. le16_to_cpu(desc->len),
  372. PCI_DMA_TODEVICE);
  373. kfree(priv->tx_buf_data[i]);
  374. priv->tx_buf_data[i] = NULL;
  375. }
  376. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
  377. desc = &ring_control->tx_mgmt[i];
  378. if (desc->host_addr)
  379. pci_unmap_single(priv->pdev,
  380. le32_to_cpu(desc->host_addr),
  381. le16_to_cpu(desc->len),
  382. PCI_DMA_TODEVICE);
  383. kfree(priv->tx_buf_mgmt[i]);
  384. priv->tx_buf_mgmt[i] = NULL;
  385. }
  386. memset(ring_control, 0, sizeof(*ring_control));
  387. }
  388. static int __devinit p54p_probe(struct pci_dev *pdev,
  389. const struct pci_device_id *id)
  390. {
  391. struct p54p_priv *priv;
  392. struct ieee80211_hw *dev;
  393. unsigned long mem_addr, mem_len;
  394. int err;
  395. DECLARE_MAC_BUF(mac);
  396. err = pci_enable_device(pdev);
  397. if (err) {
  398. printk(KERN_ERR "%s (p54pci): Cannot enable new PCI device\n",
  399. pci_name(pdev));
  400. return err;
  401. }
  402. mem_addr = pci_resource_start(pdev, 0);
  403. mem_len = pci_resource_len(pdev, 0);
  404. if (mem_len < sizeof(struct p54p_csr)) {
  405. printk(KERN_ERR "%s (p54pci): Too short PCI resources\n",
  406. pci_name(pdev));
  407. pci_disable_device(pdev);
  408. return err;
  409. }
  410. err = pci_request_regions(pdev, "p54pci");
  411. if (err) {
  412. printk(KERN_ERR "%s (p54pci): Cannot obtain PCI resources\n",
  413. pci_name(pdev));
  414. return err;
  415. }
  416. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
  417. pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
  418. printk(KERN_ERR "%s (p54pci): No suitable DMA available\n",
  419. pci_name(pdev));
  420. goto err_free_reg;
  421. }
  422. pci_set_master(pdev);
  423. pci_try_set_mwi(pdev);
  424. pci_write_config_byte(pdev, 0x40, 0);
  425. pci_write_config_byte(pdev, 0x41, 0);
  426. dev = p54_init_common(sizeof(*priv));
  427. if (!dev) {
  428. printk(KERN_ERR "%s (p54pci): ieee80211 alloc failed\n",
  429. pci_name(pdev));
  430. err = -ENOMEM;
  431. goto err_free_reg;
  432. }
  433. priv = dev->priv;
  434. priv->pdev = pdev;
  435. SET_IEEE80211_DEV(dev, &pdev->dev);
  436. pci_set_drvdata(pdev, dev);
  437. priv->map = ioremap(mem_addr, mem_len);
  438. if (!priv->map) {
  439. printk(KERN_ERR "%s (p54pci): Cannot map device memory\n",
  440. pci_name(pdev));
  441. err = -EINVAL; // TODO: use a better error code?
  442. goto err_free_dev;
  443. }
  444. priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
  445. &priv->ring_control_dma);
  446. if (!priv->ring_control) {
  447. printk(KERN_ERR "%s (p54pci): Cannot allocate rings\n",
  448. pci_name(pdev));
  449. err = -ENOMEM;
  450. goto err_iounmap;
  451. }
  452. priv->common.open = p54p_open;
  453. priv->common.stop = p54p_stop;
  454. priv->common.tx = p54p_tx;
  455. spin_lock_init(&priv->lock);
  456. tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev);
  457. p54p_open(dev);
  458. err = p54_read_eeprom(dev);
  459. p54p_stop(dev);
  460. if (err)
  461. goto err_free_desc;
  462. err = ieee80211_register_hw(dev);
  463. if (err) {
  464. printk(KERN_ERR "%s (p54pci): Cannot register netdevice\n",
  465. pci_name(pdev));
  466. goto err_free_common;
  467. }
  468. return 0;
  469. err_free_common:
  470. p54_free_common(dev);
  471. err_free_desc:
  472. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  473. priv->ring_control, priv->ring_control_dma);
  474. err_iounmap:
  475. iounmap(priv->map);
  476. err_free_dev:
  477. pci_set_drvdata(pdev, NULL);
  478. ieee80211_free_hw(dev);
  479. err_free_reg:
  480. pci_release_regions(pdev);
  481. pci_disable_device(pdev);
  482. return err;
  483. }
  484. static void __devexit p54p_remove(struct pci_dev *pdev)
  485. {
  486. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  487. struct p54p_priv *priv;
  488. if (!dev)
  489. return;
  490. ieee80211_unregister_hw(dev);
  491. priv = dev->priv;
  492. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  493. priv->ring_control, priv->ring_control_dma);
  494. p54_free_common(dev);
  495. iounmap(priv->map);
  496. pci_release_regions(pdev);
  497. pci_disable_device(pdev);
  498. ieee80211_free_hw(dev);
  499. }
  500. #ifdef CONFIG_PM
  501. static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
  502. {
  503. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  504. struct p54p_priv *priv = dev->priv;
  505. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  506. ieee80211_stop_queues(dev);
  507. p54p_stop(dev);
  508. }
  509. pci_save_state(pdev);
  510. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  511. return 0;
  512. }
  513. static int p54p_resume(struct pci_dev *pdev)
  514. {
  515. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  516. struct p54p_priv *priv = dev->priv;
  517. pci_set_power_state(pdev, PCI_D0);
  518. pci_restore_state(pdev);
  519. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  520. p54p_open(dev);
  521. ieee80211_wake_queues(dev);
  522. }
  523. return 0;
  524. }
  525. #endif /* CONFIG_PM */
  526. static struct pci_driver p54p_driver = {
  527. .name = "p54pci",
  528. .id_table = p54p_table,
  529. .probe = p54p_probe,
  530. .remove = __devexit_p(p54p_remove),
  531. #ifdef CONFIG_PM
  532. .suspend = p54p_suspend,
  533. .resume = p54p_resume,
  534. #endif /* CONFIG_PM */
  535. };
  536. static int __init p54p_init(void)
  537. {
  538. return pci_register_driver(&p54p_driver);
  539. }
  540. static void __exit p54p_exit(void)
  541. {
  542. pci_unregister_driver(&p54p_driver);
  543. }
  544. module_init(p54p_init);
  545. module_exit(p54p_exit);