main.c 47 KB

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  1. /*
  2. * Copyright (c) 2008 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. /* mac80211 and PCI callbacks */
  17. #include <linux/nl80211.h>
  18. #include "core.h"
  19. #define ATH_PCI_VERSION "0.1"
  20. #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
  21. static char *dev_info = "ath9k";
  22. MODULE_AUTHOR("Atheros Communications");
  23. MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  24. MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  25. MODULE_LICENSE("Dual BSD/GPL");
  26. static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  27. { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
  28. { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  29. { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
  30. { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
  31. { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  32. { 0 }
  33. };
  34. static int ath_get_channel(struct ath_softc *sc,
  35. struct ieee80211_channel *chan)
  36. {
  37. int i;
  38. for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
  39. if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
  40. return i;
  41. }
  42. return -1;
  43. }
  44. static u32 ath_get_extchanmode(struct ath_softc *sc,
  45. struct ieee80211_channel *chan)
  46. {
  47. u32 chanmode = 0;
  48. u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
  49. enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
  50. switch (chan->band) {
  51. case IEEE80211_BAND_2GHZ:
  52. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) &&
  53. (tx_chan_width == ATH9K_HT_MACMODE_20))
  54. chanmode = CHANNEL_G_HT20;
  55. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
  56. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  57. chanmode = CHANNEL_G_HT40PLUS;
  58. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) &&
  59. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  60. chanmode = CHANNEL_G_HT40MINUS;
  61. break;
  62. case IEEE80211_BAND_5GHZ:
  63. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE) &&
  64. (tx_chan_width == ATH9K_HT_MACMODE_20))
  65. chanmode = CHANNEL_A_HT20;
  66. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE) &&
  67. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  68. chanmode = CHANNEL_A_HT40PLUS;
  69. if ((ext_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW) &&
  70. (tx_chan_width == ATH9K_HT_MACMODE_2040))
  71. chanmode = CHANNEL_A_HT40MINUS;
  72. break;
  73. default:
  74. break;
  75. }
  76. return chanmode;
  77. }
  78. static int ath_setkey_tkip(struct ath_softc *sc,
  79. struct ieee80211_key_conf *key,
  80. struct ath9k_keyval *hk,
  81. const u8 *addr)
  82. {
  83. u8 *key_rxmic = NULL;
  84. u8 *key_txmic = NULL;
  85. key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  86. key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  87. if (addr == NULL) {
  88. /* Group key installation */
  89. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  90. return ath_keyset(sc, key->keyidx, hk, addr);
  91. }
  92. if (!sc->sc_splitmic) {
  93. /*
  94. * data key goes at first index,
  95. * the hal handles the MIC keys at index+64.
  96. */
  97. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  98. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  99. return ath_keyset(sc, key->keyidx, hk, addr);
  100. }
  101. /*
  102. * TX key goes at first index, RX key at +32.
  103. * The hal handles the MIC keys at index+64.
  104. */
  105. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  106. if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
  107. /* Txmic entry failed. No need to proceed further */
  108. DPRINTF(sc, ATH_DBG_KEYCACHE,
  109. "%s Setting TX MIC Key Failed\n", __func__);
  110. return 0;
  111. }
  112. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  113. /* XXX delete tx key on failure? */
  114. return ath_keyset(sc, key->keyidx+32, hk, addr);
  115. }
  116. static int ath_key_config(struct ath_softc *sc,
  117. const u8 *addr,
  118. struct ieee80211_key_conf *key)
  119. {
  120. struct ieee80211_vif *vif;
  121. struct ath9k_keyval hk;
  122. const u8 *mac = NULL;
  123. int ret = 0;
  124. enum nl80211_iftype opmode;
  125. memset(&hk, 0, sizeof(hk));
  126. switch (key->alg) {
  127. case ALG_WEP:
  128. hk.kv_type = ATH9K_CIPHER_WEP;
  129. break;
  130. case ALG_TKIP:
  131. hk.kv_type = ATH9K_CIPHER_TKIP;
  132. break;
  133. case ALG_CCMP:
  134. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  135. break;
  136. default:
  137. return -EINVAL;
  138. }
  139. hk.kv_len = key->keylen;
  140. memcpy(hk.kv_val, key->key, key->keylen);
  141. if (!sc->sc_vaps[0])
  142. return -EIO;
  143. vif = sc->sc_vaps[0]->av_if_data;
  144. opmode = vif->type;
  145. /*
  146. * Strategy:
  147. * For _M_STA mc tx, we will not setup a key at all since we never
  148. * tx mc.
  149. * _M_STA mc rx, we will use the keyID.
  150. * for _M_IBSS mc tx, we will use the keyID, and no macaddr.
  151. * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
  152. * peer node. BUT we will plumb a cleartext key so that we can do
  153. * perSta default key table lookup in software.
  154. */
  155. if (is_broadcast_ether_addr(addr)) {
  156. switch (opmode) {
  157. case NL80211_IFTYPE_STATION:
  158. /* default key: could be group WPA key
  159. * or could be static WEP key */
  160. mac = NULL;
  161. break;
  162. case NL80211_IFTYPE_ADHOC:
  163. break;
  164. case NL80211_IFTYPE_AP:
  165. break;
  166. default:
  167. ASSERT(0);
  168. break;
  169. }
  170. } else {
  171. mac = addr;
  172. }
  173. if (key->alg == ALG_TKIP)
  174. ret = ath_setkey_tkip(sc, key, &hk, mac);
  175. else
  176. ret = ath_keyset(sc, key->keyidx, &hk, mac);
  177. if (!ret)
  178. return -EIO;
  179. return 0;
  180. }
  181. static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
  182. {
  183. int freeslot;
  184. freeslot = (key->keyidx >= 4) ? 1 : 0;
  185. ath_key_reset(sc, key->keyidx, freeslot);
  186. }
  187. static void setup_ht_cap(struct ieee80211_ht_info *ht_info)
  188. {
  189. #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
  190. #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
  191. ht_info->ht_supported = 1;
  192. ht_info->cap = (u16)IEEE80211_HT_CAP_SUP_WIDTH
  193. |(u16)IEEE80211_HT_CAP_SM_PS
  194. |(u16)IEEE80211_HT_CAP_SGI_40
  195. |(u16)IEEE80211_HT_CAP_DSSSCCK40;
  196. ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
  197. ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
  198. /* setup supported mcs set */
  199. memset(ht_info->supp_mcs_set, 0, 16);
  200. ht_info->supp_mcs_set[0] = 0xff;
  201. ht_info->supp_mcs_set[1] = 0xff;
  202. ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
  203. }
  204. static int ath_rate2idx(struct ath_softc *sc, int rate)
  205. {
  206. int i = 0, cur_band, n_rates;
  207. struct ieee80211_hw *hw = sc->hw;
  208. cur_band = hw->conf.channel->band;
  209. n_rates = sc->sbands[cur_band].n_bitrates;
  210. for (i = 0; i < n_rates; i++) {
  211. if (sc->sbands[cur_band].bitrates[i].bitrate == rate)
  212. break;
  213. }
  214. /*
  215. * NB:mac80211 validates rx rate index against the supported legacy rate
  216. * index only (should be done against ht rates also), return the highest
  217. * legacy rate index for rx rate which does not match any one of the
  218. * supported basic and extended rates to make mac80211 happy.
  219. * The following hack will be cleaned up once the issue with
  220. * the rx rate index validation in mac80211 is fixed.
  221. */
  222. if (i == n_rates)
  223. return n_rates - 1;
  224. return i;
  225. }
  226. static void ath9k_rx_prepare(struct ath_softc *sc,
  227. struct sk_buff *skb,
  228. struct ath_recv_status *status,
  229. struct ieee80211_rx_status *rx_status)
  230. {
  231. struct ieee80211_hw *hw = sc->hw;
  232. struct ieee80211_channel *curchan = hw->conf.channel;
  233. memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
  234. rx_status->mactime = status->tsf;
  235. rx_status->band = curchan->band;
  236. rx_status->freq = curchan->center_freq;
  237. rx_status->noise = sc->sc_ani.sc_noise_floor;
  238. rx_status->signal = rx_status->noise + status->rssi;
  239. rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100));
  240. rx_status->antenna = status->antenna;
  241. /* XXX Fix me, 64 cannot be the max rssi value, rigure it out */
  242. rx_status->qual = status->rssi * 100 / 64;
  243. if (status->flags & ATH_RX_MIC_ERROR)
  244. rx_status->flag |= RX_FLAG_MMIC_ERROR;
  245. if (status->flags & ATH_RX_FCS_ERROR)
  246. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  247. rx_status->flag |= RX_FLAG_TSFT;
  248. }
  249. static u8 parse_mpdudensity(u8 mpdudensity)
  250. {
  251. /*
  252. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  253. * 0 for no restriction
  254. * 1 for 1/4 us
  255. * 2 for 1/2 us
  256. * 3 for 1 us
  257. * 4 for 2 us
  258. * 5 for 4 us
  259. * 6 for 8 us
  260. * 7 for 16 us
  261. */
  262. switch (mpdudensity) {
  263. case 0:
  264. return 0;
  265. case 1:
  266. case 2:
  267. case 3:
  268. /* Our lower layer calculations limit our precision to
  269. 1 microsecond */
  270. return 1;
  271. case 4:
  272. return 2;
  273. case 5:
  274. return 4;
  275. case 6:
  276. return 8;
  277. case 7:
  278. return 16;
  279. default:
  280. return 0;
  281. }
  282. }
  283. static void ath9k_ht_conf(struct ath_softc *sc,
  284. struct ieee80211_bss_conf *bss_conf)
  285. {
  286. #define IEEE80211_HT_CAP_40MHZ_INTOLERANT BIT(14)
  287. struct ath_ht_info *ht_info = &sc->sc_ht_info;
  288. if (bss_conf->assoc_ht) {
  289. ht_info->ext_chan_offset =
  290. bss_conf->ht_bss_conf->bss_cap &
  291. IEEE80211_HT_IE_CHA_SEC_OFFSET;
  292. if (!(bss_conf->ht_conf->cap &
  293. IEEE80211_HT_CAP_40MHZ_INTOLERANT) &&
  294. (bss_conf->ht_bss_conf->bss_cap &
  295. IEEE80211_HT_IE_CHA_WIDTH))
  296. ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
  297. else
  298. ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
  299. ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
  300. ht_info->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
  301. bss_conf->ht_conf->ampdu_factor);
  302. ht_info->mpdudensity =
  303. parse_mpdudensity(bss_conf->ht_conf->ampdu_density);
  304. }
  305. #undef IEEE80211_HT_CAP_40MHZ_INTOLERANT
  306. }
  307. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  308. struct ieee80211_bss_conf *bss_conf)
  309. {
  310. struct ieee80211_hw *hw = sc->hw;
  311. struct ieee80211_channel *curchan = hw->conf.channel;
  312. struct ath_vap *avp;
  313. int pos;
  314. DECLARE_MAC_BUF(mac);
  315. if (bss_conf->assoc) {
  316. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
  317. __func__,
  318. bss_conf->aid);
  319. avp = sc->sc_vaps[0];
  320. if (avp == NULL) {
  321. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  322. __func__);
  323. return;
  324. }
  325. /* New association, store aid */
  326. if (avp->av_opmode == ATH9K_M_STA) {
  327. sc->sc_curaid = bss_conf->aid;
  328. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  329. sc->sc_curaid);
  330. }
  331. /* Configure the beacon */
  332. ath_beacon_config(sc, 0);
  333. sc->sc_flags |= SC_OP_BEACONS;
  334. /* Reset rssi stats */
  335. sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
  336. sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
  337. sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
  338. sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
  339. /* Update chainmask */
  340. ath_update_chainmask(sc, bss_conf->assoc_ht);
  341. DPRINTF(sc, ATH_DBG_CONFIG,
  342. "%s: bssid %s aid 0x%x\n",
  343. __func__,
  344. print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
  345. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  346. __func__,
  347. curchan->center_freq);
  348. pos = ath_get_channel(sc, curchan);
  349. if (pos == -1) {
  350. DPRINTF(sc, ATH_DBG_FATAL,
  351. "%s: Invalid channel\n", __func__);
  352. return;
  353. }
  354. if (hw->conf.ht_conf.ht_supported)
  355. sc->sc_ah->ah_channels[pos].chanmode =
  356. ath_get_extchanmode(sc, curchan);
  357. else
  358. sc->sc_ah->ah_channels[pos].chanmode =
  359. (curchan->band == IEEE80211_BAND_2GHZ) ?
  360. CHANNEL_G : CHANNEL_A;
  361. /* set h/w channel */
  362. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  363. DPRINTF(sc, ATH_DBG_FATAL,
  364. "%s: Unable to set channel\n",
  365. __func__);
  366. ath_rate_newstate(sc, avp);
  367. /* Update ratectrl about the new state */
  368. ath_rc_node_update(hw, avp->rc_node);
  369. /* Start ANI */
  370. mod_timer(&sc->sc_ani.timer,
  371. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  372. } else {
  373. DPRINTF(sc, ATH_DBG_CONFIG,
  374. "%s: Bss Info DISSOC\n", __func__);
  375. sc->sc_curaid = 0;
  376. }
  377. }
  378. void ath_get_beaconconfig(struct ath_softc *sc,
  379. int if_id,
  380. struct ath_beacon_config *conf)
  381. {
  382. struct ieee80211_hw *hw = sc->hw;
  383. /* fill in beacon config data */
  384. conf->beacon_interval = hw->conf.beacon_int;
  385. conf->listen_interval = 100;
  386. conf->dtim_count = 1;
  387. conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
  388. }
  389. void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  390. struct ath_xmit_status *tx_status, struct ath_node *an)
  391. {
  392. struct ieee80211_hw *hw = sc->hw;
  393. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  394. DPRINTF(sc, ATH_DBG_XMIT,
  395. "%s: TX complete: skb: %p\n", __func__, skb);
  396. if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
  397. tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
  398. /* free driver's private data area of tx_info */
  399. if (tx_info->driver_data[0] != NULL)
  400. kfree(tx_info->driver_data[0]);
  401. tx_info->driver_data[0] = NULL;
  402. }
  403. if (tx_status->flags & ATH_TX_BAR) {
  404. tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
  405. tx_status->flags &= ~ATH_TX_BAR;
  406. }
  407. if (tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY)) {
  408. if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  409. /* Frame was not ACKed, but an ACK was expected */
  410. tx_info->status.excessive_retries = 1;
  411. }
  412. } else {
  413. /* Frame was ACKed */
  414. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  415. }
  416. tx_info->status.retry_count = tx_status->retries;
  417. ieee80211_tx_status(hw, skb);
  418. if (an)
  419. ath_node_put(sc, an, ATH9K_BH_STATUS_CHANGE);
  420. }
  421. int _ath_rx_indicate(struct ath_softc *sc,
  422. struct sk_buff *skb,
  423. struct ath_recv_status *status,
  424. u16 keyix)
  425. {
  426. struct ieee80211_hw *hw = sc->hw;
  427. struct ath_node *an = NULL;
  428. struct ieee80211_rx_status rx_status;
  429. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  430. int hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  431. int padsize;
  432. enum ATH_RX_TYPE st;
  433. /* see if any padding is done by the hw and remove it */
  434. if (hdrlen & 3) {
  435. padsize = hdrlen % 4;
  436. memmove(skb->data + padsize, skb->data, hdrlen);
  437. skb_pull(skb, padsize);
  438. }
  439. /* Prepare rx status */
  440. ath9k_rx_prepare(sc, skb, status, &rx_status);
  441. if (!(keyix == ATH9K_RXKEYIX_INVALID) &&
  442. !(status->flags & ATH_RX_DECRYPT_ERROR)) {
  443. rx_status.flag |= RX_FLAG_DECRYPTED;
  444. } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
  445. && !(status->flags & ATH_RX_DECRYPT_ERROR)
  446. && skb->len >= hdrlen + 4) {
  447. keyix = skb->data[hdrlen + 3] >> 6;
  448. if (test_bit(keyix, sc->sc_keymap))
  449. rx_status.flag |= RX_FLAG_DECRYPTED;
  450. }
  451. spin_lock_bh(&sc->node_lock);
  452. an = ath_node_find(sc, hdr->addr2);
  453. spin_unlock_bh(&sc->node_lock);
  454. if (an) {
  455. ath_rx_input(sc, an,
  456. hw->conf.ht_conf.ht_supported,
  457. skb, status, &st);
  458. }
  459. if (!an || (st != ATH_RX_CONSUMED))
  460. __ieee80211_rx(hw, skb, &rx_status);
  461. return 0;
  462. }
  463. int ath_rx_subframe(struct ath_node *an,
  464. struct sk_buff *skb,
  465. struct ath_recv_status *status)
  466. {
  467. struct ath_softc *sc = an->an_sc;
  468. struct ieee80211_hw *hw = sc->hw;
  469. struct ieee80211_rx_status rx_status;
  470. /* Prepare rx status */
  471. ath9k_rx_prepare(sc, skb, status, &rx_status);
  472. if (!(status->flags & ATH_RX_DECRYPT_ERROR))
  473. rx_status.flag |= RX_FLAG_DECRYPTED;
  474. __ieee80211_rx(hw, skb, &rx_status);
  475. return 0;
  476. }
  477. /********************************/
  478. /* LED functions */
  479. /********************************/
  480. static void ath_led_brightness(struct led_classdev *led_cdev,
  481. enum led_brightness brightness)
  482. {
  483. struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
  484. struct ath_softc *sc = led->sc;
  485. switch (brightness) {
  486. case LED_OFF:
  487. if (led->led_type == ATH_LED_ASSOC ||
  488. led->led_type == ATH_LED_RADIO)
  489. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  490. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
  491. (led->led_type == ATH_LED_RADIO) ? 1 :
  492. !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
  493. break;
  494. case LED_FULL:
  495. if (led->led_type == ATH_LED_ASSOC)
  496. sc->sc_flags |= SC_OP_LED_ASSOCIATED;
  497. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
  498. break;
  499. default:
  500. break;
  501. }
  502. }
  503. static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
  504. char *trigger)
  505. {
  506. int ret;
  507. led->sc = sc;
  508. led->led_cdev.name = led->name;
  509. led->led_cdev.default_trigger = trigger;
  510. led->led_cdev.brightness_set = ath_led_brightness;
  511. ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
  512. if (ret)
  513. DPRINTF(sc, ATH_DBG_FATAL,
  514. "Failed to register led:%s", led->name);
  515. else
  516. led->registered = 1;
  517. return ret;
  518. }
  519. static void ath_unregister_led(struct ath_led *led)
  520. {
  521. if (led->registered) {
  522. led_classdev_unregister(&led->led_cdev);
  523. led->registered = 0;
  524. }
  525. }
  526. static void ath_deinit_leds(struct ath_softc *sc)
  527. {
  528. ath_unregister_led(&sc->assoc_led);
  529. sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
  530. ath_unregister_led(&sc->tx_led);
  531. ath_unregister_led(&sc->rx_led);
  532. ath_unregister_led(&sc->radio_led);
  533. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  534. }
  535. static void ath_init_leds(struct ath_softc *sc)
  536. {
  537. char *trigger;
  538. int ret;
  539. /* Configure gpio 1 for output */
  540. ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
  541. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  542. /* LED off, active low */
  543. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  544. trigger = ieee80211_get_radio_led_name(sc->hw);
  545. snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
  546. "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
  547. ret = ath_register_led(sc, &sc->radio_led, trigger);
  548. sc->radio_led.led_type = ATH_LED_RADIO;
  549. if (ret)
  550. goto fail;
  551. trigger = ieee80211_get_assoc_led_name(sc->hw);
  552. snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
  553. "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
  554. ret = ath_register_led(sc, &sc->assoc_led, trigger);
  555. sc->assoc_led.led_type = ATH_LED_ASSOC;
  556. if (ret)
  557. goto fail;
  558. trigger = ieee80211_get_tx_led_name(sc->hw);
  559. snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
  560. "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
  561. ret = ath_register_led(sc, &sc->tx_led, trigger);
  562. sc->tx_led.led_type = ATH_LED_TX;
  563. if (ret)
  564. goto fail;
  565. trigger = ieee80211_get_rx_led_name(sc->hw);
  566. snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
  567. "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
  568. ret = ath_register_led(sc, &sc->rx_led, trigger);
  569. sc->rx_led.led_type = ATH_LED_RX;
  570. if (ret)
  571. goto fail;
  572. return;
  573. fail:
  574. ath_deinit_leds(sc);
  575. }
  576. #ifdef CONFIG_RFKILL
  577. /*******************/
  578. /* Rfkill */
  579. /*******************/
  580. static void ath_radio_enable(struct ath_softc *sc)
  581. {
  582. struct ath_hal *ah = sc->sc_ah;
  583. int status;
  584. spin_lock_bh(&sc->sc_resetlock);
  585. if (!ath9k_hw_reset(ah, ah->ah_curchan,
  586. sc->sc_ht_info.tx_chan_width,
  587. sc->sc_tx_chainmask,
  588. sc->sc_rx_chainmask,
  589. sc->sc_ht_extprotspacing,
  590. false, &status)) {
  591. DPRINTF(sc, ATH_DBG_FATAL,
  592. "%s: unable to reset channel %u (%uMhz) "
  593. "flags 0x%x hal status %u\n", __func__,
  594. ath9k_hw_mhz2ieee(ah,
  595. ah->ah_curchan->channel,
  596. ah->ah_curchan->channelFlags),
  597. ah->ah_curchan->channel,
  598. ah->ah_curchan->channelFlags, status);
  599. }
  600. spin_unlock_bh(&sc->sc_resetlock);
  601. ath_update_txpow(sc);
  602. if (ath_startrecv(sc) != 0) {
  603. DPRINTF(sc, ATH_DBG_FATAL,
  604. "%s: unable to restart recv logic\n", __func__);
  605. return;
  606. }
  607. if (sc->sc_flags & SC_OP_BEACONS)
  608. ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
  609. /* Re-Enable interrupts */
  610. ath9k_hw_set_interrupts(ah, sc->sc_imask);
  611. /* Enable LED */
  612. ath9k_hw_cfg_output(ah, ATH_LED_PIN,
  613. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  614. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
  615. ieee80211_wake_queues(sc->hw);
  616. }
  617. static void ath_radio_disable(struct ath_softc *sc)
  618. {
  619. struct ath_hal *ah = sc->sc_ah;
  620. int status;
  621. ieee80211_stop_queues(sc->hw);
  622. /* Disable LED */
  623. ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
  624. ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
  625. /* Disable interrupts */
  626. ath9k_hw_set_interrupts(ah, 0);
  627. ath_draintxq(sc, false); /* clear pending tx frames */
  628. ath_stoprecv(sc); /* turn off frame recv */
  629. ath_flushrecv(sc); /* flush recv queue */
  630. spin_lock_bh(&sc->sc_resetlock);
  631. if (!ath9k_hw_reset(ah, ah->ah_curchan,
  632. sc->sc_ht_info.tx_chan_width,
  633. sc->sc_tx_chainmask,
  634. sc->sc_rx_chainmask,
  635. sc->sc_ht_extprotspacing,
  636. false, &status)) {
  637. DPRINTF(sc, ATH_DBG_FATAL,
  638. "%s: unable to reset channel %u (%uMhz) "
  639. "flags 0x%x hal status %u\n", __func__,
  640. ath9k_hw_mhz2ieee(ah,
  641. ah->ah_curchan->channel,
  642. ah->ah_curchan->channelFlags),
  643. ah->ah_curchan->channel,
  644. ah->ah_curchan->channelFlags, status);
  645. }
  646. spin_unlock_bh(&sc->sc_resetlock);
  647. ath9k_hw_phy_disable(ah);
  648. ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
  649. }
  650. static bool ath_is_rfkill_set(struct ath_softc *sc)
  651. {
  652. struct ath_hal *ah = sc->sc_ah;
  653. return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
  654. ah->ah_rfkill_polarity;
  655. }
  656. /* h/w rfkill poll function */
  657. static void ath_rfkill_poll(struct work_struct *work)
  658. {
  659. struct ath_softc *sc = container_of(work, struct ath_softc,
  660. rf_kill.rfkill_poll.work);
  661. bool radio_on;
  662. if (sc->sc_flags & SC_OP_INVALID)
  663. return;
  664. radio_on = !ath_is_rfkill_set(sc);
  665. /*
  666. * enable/disable radio only when there is a
  667. * state change in RF switch
  668. */
  669. if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
  670. enum rfkill_state state;
  671. if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
  672. state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
  673. : RFKILL_STATE_HARD_BLOCKED;
  674. } else if (radio_on) {
  675. ath_radio_enable(sc);
  676. state = RFKILL_STATE_UNBLOCKED;
  677. } else {
  678. ath_radio_disable(sc);
  679. state = RFKILL_STATE_HARD_BLOCKED;
  680. }
  681. if (state == RFKILL_STATE_HARD_BLOCKED)
  682. sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
  683. else
  684. sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
  685. rfkill_force_state(sc->rf_kill.rfkill, state);
  686. }
  687. queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
  688. msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
  689. }
  690. /* s/w rfkill handler */
  691. static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
  692. {
  693. struct ath_softc *sc = data;
  694. switch (state) {
  695. case RFKILL_STATE_SOFT_BLOCKED:
  696. if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
  697. SC_OP_RFKILL_SW_BLOCKED)))
  698. ath_radio_disable(sc);
  699. sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
  700. return 0;
  701. case RFKILL_STATE_UNBLOCKED:
  702. if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
  703. sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
  704. if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
  705. DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
  706. "radio as it is disabled by h/w \n");
  707. return -EPERM;
  708. }
  709. ath_radio_enable(sc);
  710. }
  711. return 0;
  712. default:
  713. return -EINVAL;
  714. }
  715. }
  716. /* Init s/w rfkill */
  717. static int ath_init_sw_rfkill(struct ath_softc *sc)
  718. {
  719. sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
  720. RFKILL_TYPE_WLAN);
  721. if (!sc->rf_kill.rfkill) {
  722. DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
  723. return -ENOMEM;
  724. }
  725. snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
  726. "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
  727. sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
  728. sc->rf_kill.rfkill->data = sc;
  729. sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
  730. sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
  731. sc->rf_kill.rfkill->user_claim_unsupported = 1;
  732. return 0;
  733. }
  734. /* Deinitialize rfkill */
  735. static void ath_deinit_rfkill(struct ath_softc *sc)
  736. {
  737. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  738. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  739. if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
  740. rfkill_unregister(sc->rf_kill.rfkill);
  741. sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
  742. sc->rf_kill.rfkill = NULL;
  743. }
  744. }
  745. #endif /* CONFIG_RFKILL */
  746. static int ath_detach(struct ath_softc *sc)
  747. {
  748. struct ieee80211_hw *hw = sc->hw;
  749. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
  750. /* Deinit LED control */
  751. ath_deinit_leds(sc);
  752. #ifdef CONFIG_RFKILL
  753. /* deinit rfkill */
  754. ath_deinit_rfkill(sc);
  755. #endif
  756. /* Unregister hw */
  757. ieee80211_unregister_hw(hw);
  758. /* unregister Rate control */
  759. ath_rate_control_unregister();
  760. /* tx/rx cleanup */
  761. ath_rx_cleanup(sc);
  762. ath_tx_cleanup(sc);
  763. /* Deinit */
  764. ath_deinit(sc);
  765. return 0;
  766. }
  767. static int ath_attach(u16 devid,
  768. struct ath_softc *sc)
  769. {
  770. struct ieee80211_hw *hw = sc->hw;
  771. int error = 0;
  772. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
  773. error = ath_init(devid, sc);
  774. if (error != 0)
  775. return error;
  776. /* Init nodes */
  777. INIT_LIST_HEAD(&sc->node_list);
  778. spin_lock_init(&sc->node_lock);
  779. /* get mac address from hardware and set in mac80211 */
  780. SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
  781. /* setup channels and rates */
  782. sc->sbands[IEEE80211_BAND_2GHZ].channels =
  783. sc->channels[IEEE80211_BAND_2GHZ];
  784. sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
  785. sc->rates[IEEE80211_BAND_2GHZ];
  786. sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
  787. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
  788. /* Setup HT capabilities for 2.4Ghz*/
  789. setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_info);
  790. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  791. &sc->sbands[IEEE80211_BAND_2GHZ];
  792. if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
  793. sc->sbands[IEEE80211_BAND_5GHZ].channels =
  794. sc->channels[IEEE80211_BAND_5GHZ];
  795. sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
  796. sc->rates[IEEE80211_BAND_5GHZ];
  797. sc->sbands[IEEE80211_BAND_5GHZ].band =
  798. IEEE80211_BAND_5GHZ;
  799. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
  800. /* Setup HT capabilities for 5Ghz*/
  801. setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_info);
  802. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  803. &sc->sbands[IEEE80211_BAND_5GHZ];
  804. }
  805. /* FIXME: Have to figure out proper hw init values later */
  806. hw->queues = 4;
  807. hw->ampdu_queues = 1;
  808. /* Register rate control */
  809. hw->rate_control_algorithm = "ath9k_rate_control";
  810. error = ath_rate_control_register();
  811. if (error != 0) {
  812. DPRINTF(sc, ATH_DBG_FATAL,
  813. "%s: Unable to register rate control "
  814. "algorithm:%d\n", __func__, error);
  815. ath_rate_control_unregister();
  816. goto bad;
  817. }
  818. error = ieee80211_register_hw(hw);
  819. if (error != 0) {
  820. ath_rate_control_unregister();
  821. goto bad;
  822. }
  823. /* Initialize LED control */
  824. ath_init_leds(sc);
  825. #ifdef CONFIG_RFKILL
  826. /* Initialze h/w Rfkill */
  827. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  828. INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
  829. /* Initialize s/w rfkill */
  830. if (ath_init_sw_rfkill(sc))
  831. goto detach;
  832. #endif
  833. /* initialize tx/rx engine */
  834. error = ath_tx_init(sc, ATH_TXBUF);
  835. if (error != 0)
  836. goto detach;
  837. error = ath_rx_init(sc, ATH_RXBUF);
  838. if (error != 0)
  839. goto detach;
  840. return 0;
  841. detach:
  842. ath_detach(sc);
  843. bad:
  844. return error;
  845. }
  846. static int ath9k_start(struct ieee80211_hw *hw)
  847. {
  848. struct ath_softc *sc = hw->priv;
  849. struct ieee80211_channel *curchan = hw->conf.channel;
  850. int error = 0, pos;
  851. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
  852. "initial channel: %d MHz\n", __func__, curchan->center_freq);
  853. /* setup initial channel */
  854. pos = ath_get_channel(sc, curchan);
  855. if (pos == -1) {
  856. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  857. return -EINVAL;
  858. }
  859. sc->sc_ah->ah_channels[pos].chanmode =
  860. (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
  861. /* open ath_dev */
  862. error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
  863. if (error) {
  864. DPRINTF(sc, ATH_DBG_FATAL,
  865. "%s: Unable to complete ath_open\n", __func__);
  866. return error;
  867. }
  868. #ifdef CONFIG_RFKILL
  869. /* Start rfkill polling */
  870. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  871. queue_delayed_work(sc->hw->workqueue,
  872. &sc->rf_kill.rfkill_poll, 0);
  873. if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
  874. if (rfkill_register(sc->rf_kill.rfkill)) {
  875. DPRINTF(sc, ATH_DBG_FATAL,
  876. "Unable to register rfkill\n");
  877. rfkill_free(sc->rf_kill.rfkill);
  878. /* Deinitialize the device */
  879. if (sc->pdev->irq)
  880. free_irq(sc->pdev->irq, sc);
  881. ath_detach(sc);
  882. pci_iounmap(sc->pdev, sc->mem);
  883. pci_release_region(sc->pdev, 0);
  884. pci_disable_device(sc->pdev);
  885. ieee80211_free_hw(hw);
  886. return -EIO;
  887. } else {
  888. sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
  889. }
  890. }
  891. #endif
  892. ieee80211_wake_queues(hw);
  893. return 0;
  894. }
  895. static int ath9k_tx(struct ieee80211_hw *hw,
  896. struct sk_buff *skb)
  897. {
  898. struct ath_softc *sc = hw->priv;
  899. int hdrlen, padsize;
  900. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  901. /*
  902. * As a temporary workaround, assign seq# here; this will likely need
  903. * to be cleaned up to work better with Beacon transmission and virtual
  904. * BSSes.
  905. */
  906. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  907. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  908. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  909. sc->seq_no += 0x10;
  910. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  911. hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
  912. }
  913. /* Add the padding after the header if this is not already done */
  914. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  915. if (hdrlen & 3) {
  916. padsize = hdrlen % 4;
  917. if (skb_headroom(skb) < padsize)
  918. return -1;
  919. skb_push(skb, padsize);
  920. memmove(skb->data, skb->data + padsize, hdrlen);
  921. }
  922. DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
  923. __func__,
  924. skb);
  925. if (ath_tx_start(sc, skb) != 0) {
  926. DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
  927. dev_kfree_skb_any(skb);
  928. /* FIXME: Check for proper return value from ATH_DEV */
  929. return 0;
  930. }
  931. return 0;
  932. }
  933. static void ath9k_stop(struct ieee80211_hw *hw)
  934. {
  935. struct ath_softc *sc = hw->priv;
  936. int error;
  937. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
  938. error = ath_suspend(sc);
  939. if (error)
  940. DPRINTF(sc, ATH_DBG_CONFIG,
  941. "%s: Device is no longer present\n", __func__);
  942. ieee80211_stop_queues(hw);
  943. #ifdef CONFIG_RFKILL
  944. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  945. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  946. #endif
  947. }
  948. static int ath9k_add_interface(struct ieee80211_hw *hw,
  949. struct ieee80211_if_init_conf *conf)
  950. {
  951. struct ath_softc *sc = hw->priv;
  952. int error, ic_opmode = 0;
  953. /* Support only vap for now */
  954. if (sc->sc_nvaps)
  955. return -ENOBUFS;
  956. switch (conf->type) {
  957. case NL80211_IFTYPE_STATION:
  958. ic_opmode = ATH9K_M_STA;
  959. break;
  960. case NL80211_IFTYPE_ADHOC:
  961. ic_opmode = ATH9K_M_IBSS;
  962. break;
  963. case NL80211_IFTYPE_AP:
  964. ic_opmode = ATH9K_M_HOSTAP;
  965. break;
  966. default:
  967. DPRINTF(sc, ATH_DBG_FATAL,
  968. "%s: Interface type %d not yet supported\n",
  969. __func__, conf->type);
  970. return -EOPNOTSUPP;
  971. }
  972. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
  973. __func__,
  974. ic_opmode);
  975. error = ath_vap_attach(sc, 0, conf->vif, ic_opmode);
  976. if (error) {
  977. DPRINTF(sc, ATH_DBG_FATAL,
  978. "%s: Unable to attach vap, error: %d\n",
  979. __func__, error);
  980. return error;
  981. }
  982. if (conf->type == NL80211_IFTYPE_AP) {
  983. /* TODO: is this a suitable place to start ANI for AP mode? */
  984. /* Start ANI */
  985. mod_timer(&sc->sc_ani.timer,
  986. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  987. }
  988. return 0;
  989. }
  990. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  991. struct ieee80211_if_init_conf *conf)
  992. {
  993. struct ath_softc *sc = hw->priv;
  994. struct ath_vap *avp;
  995. int error;
  996. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
  997. avp = sc->sc_vaps[0];
  998. if (avp == NULL) {
  999. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  1000. __func__);
  1001. return;
  1002. }
  1003. #ifdef CONFIG_SLOW_ANT_DIV
  1004. ath_slow_ant_div_stop(&sc->sc_antdiv);
  1005. #endif
  1006. /* Stop ANI */
  1007. del_timer_sync(&sc->sc_ani.timer);
  1008. /* Update ratectrl */
  1009. ath_rate_newstate(sc, avp);
  1010. /* Reclaim beacon resources */
  1011. if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
  1012. sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
  1013. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  1014. ath_beacon_return(sc, avp);
  1015. }
  1016. /* Set interrupt mask */
  1017. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  1018. ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~ATH9K_INT_GLOBAL);
  1019. sc->sc_flags &= ~SC_OP_BEACONS;
  1020. error = ath_vap_detach(sc, 0);
  1021. if (error)
  1022. DPRINTF(sc, ATH_DBG_FATAL,
  1023. "%s: Unable to detach vap, error: %d\n",
  1024. __func__, error);
  1025. }
  1026. static int ath9k_config(struct ieee80211_hw *hw,
  1027. struct ieee80211_conf *conf)
  1028. {
  1029. struct ath_softc *sc = hw->priv;
  1030. struct ieee80211_channel *curchan = hw->conf.channel;
  1031. int pos;
  1032. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
  1033. __func__,
  1034. curchan->center_freq);
  1035. pos = ath_get_channel(sc, curchan);
  1036. if (pos == -1) {
  1037. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
  1038. return -EINVAL;
  1039. }
  1040. sc->sc_ah->ah_channels[pos].chanmode =
  1041. (curchan->band == IEEE80211_BAND_2GHZ) ?
  1042. CHANNEL_G : CHANNEL_A;
  1043. if (sc->sc_curaid && hw->conf.ht_conf.ht_supported)
  1044. sc->sc_ah->ah_channels[pos].chanmode =
  1045. ath_get_extchanmode(sc, curchan);
  1046. sc->sc_config.txpowlimit = 2 * conf->power_level;
  1047. /* set h/w channel */
  1048. if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
  1049. DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
  1050. __func__);
  1051. return 0;
  1052. }
  1053. static int ath9k_config_interface(struct ieee80211_hw *hw,
  1054. struct ieee80211_vif *vif,
  1055. struct ieee80211_if_conf *conf)
  1056. {
  1057. struct ath_softc *sc = hw->priv;
  1058. struct ath_hal *ah = sc->sc_ah;
  1059. struct ath_vap *avp;
  1060. u32 rfilt = 0;
  1061. int error, i;
  1062. DECLARE_MAC_BUF(mac);
  1063. avp = sc->sc_vaps[0];
  1064. if (avp == NULL) {
  1065. DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
  1066. __func__);
  1067. return -EINVAL;
  1068. }
  1069. /* TODO: Need to decide which hw opmode to use for multi-interface
  1070. * cases */
  1071. if (vif->type == NL80211_IFTYPE_AP &&
  1072. ah->ah_opmode != ATH9K_M_HOSTAP) {
  1073. ah->ah_opmode = ATH9K_M_HOSTAP;
  1074. ath9k_hw_setopmode(ah);
  1075. ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
  1076. /* Request full reset to get hw opmode changed properly */
  1077. sc->sc_flags |= SC_OP_FULL_RESET;
  1078. }
  1079. if ((conf->changed & IEEE80211_IFCC_BSSID) &&
  1080. !is_zero_ether_addr(conf->bssid)) {
  1081. switch (vif->type) {
  1082. case NL80211_IFTYPE_STATION:
  1083. case NL80211_IFTYPE_ADHOC:
  1084. /* Update ratectrl about the new state */
  1085. ath_rate_newstate(sc, avp);
  1086. /* Set BSSID */
  1087. memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
  1088. sc->sc_curaid = 0;
  1089. ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
  1090. sc->sc_curaid);
  1091. /* Set aggregation protection mode parameters */
  1092. sc->sc_config.ath_aggr_prot = 0;
  1093. /*
  1094. * Reset our TSF so that its value is lower than the
  1095. * beacon that we are trying to catch.
  1096. * Only then hw will update its TSF register with the
  1097. * new beacon. Reset the TSF before setting the BSSID
  1098. * to avoid allowing in any frames that would update
  1099. * our TSF only to have us clear it
  1100. * immediately thereafter.
  1101. */
  1102. ath9k_hw_reset_tsf(sc->sc_ah);
  1103. /* Disable BMISS interrupt when we're not associated */
  1104. ath9k_hw_set_interrupts(sc->sc_ah,
  1105. sc->sc_imask &
  1106. ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
  1107. sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  1108. DPRINTF(sc, ATH_DBG_CONFIG,
  1109. "%s: RX filter 0x%x bssid %s aid 0x%x\n",
  1110. __func__, rfilt,
  1111. print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
  1112. /* need to reconfigure the beacon */
  1113. sc->sc_flags &= ~SC_OP_BEACONS ;
  1114. break;
  1115. default:
  1116. break;
  1117. }
  1118. }
  1119. if ((conf->changed & IEEE80211_IFCC_BEACON) &&
  1120. ((vif->type == NL80211_IFTYPE_ADHOC) ||
  1121. (vif->type == NL80211_IFTYPE_AP))) {
  1122. /*
  1123. * Allocate and setup the beacon frame.
  1124. *
  1125. * Stop any previous beacon DMA. This may be
  1126. * necessary, for example, when an ibss merge
  1127. * causes reconfiguration; we may be called
  1128. * with beacon transmission active.
  1129. */
  1130. ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
  1131. error = ath_beacon_alloc(sc, 0);
  1132. if (error != 0)
  1133. return error;
  1134. ath_beacon_sync(sc, 0);
  1135. }
  1136. /* Check for WLAN_CAPABILITY_PRIVACY ? */
  1137. if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
  1138. for (i = 0; i < IEEE80211_WEP_NKID; i++)
  1139. if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
  1140. ath9k_hw_keysetmac(sc->sc_ah,
  1141. (u16)i,
  1142. sc->sc_curbssid);
  1143. }
  1144. /* Only legacy IBSS for now */
  1145. if (vif->type == NL80211_IFTYPE_ADHOC)
  1146. ath_update_chainmask(sc, 0);
  1147. return 0;
  1148. }
  1149. #define SUPPORTED_FILTERS \
  1150. (FIF_PROMISC_IN_BSS | \
  1151. FIF_ALLMULTI | \
  1152. FIF_CONTROL | \
  1153. FIF_OTHER_BSS | \
  1154. FIF_BCN_PRBRESP_PROMISC | \
  1155. FIF_FCSFAIL)
  1156. /* FIXME: sc->sc_full_reset ? */
  1157. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1158. unsigned int changed_flags,
  1159. unsigned int *total_flags,
  1160. int mc_count,
  1161. struct dev_mc_list *mclist)
  1162. {
  1163. struct ath_softc *sc = hw->priv;
  1164. u32 rfilt;
  1165. changed_flags &= SUPPORTED_FILTERS;
  1166. *total_flags &= SUPPORTED_FILTERS;
  1167. sc->rx_filter = *total_flags;
  1168. rfilt = ath_calcrxfilter(sc);
  1169. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1170. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1171. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1172. ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
  1173. }
  1174. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n",
  1175. __func__, sc->rx_filter);
  1176. }
  1177. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1178. struct ieee80211_vif *vif,
  1179. enum sta_notify_cmd cmd,
  1180. struct ieee80211_sta *sta)
  1181. {
  1182. struct ath_softc *sc = hw->priv;
  1183. struct ath_node *an;
  1184. unsigned long flags;
  1185. DECLARE_MAC_BUF(mac);
  1186. spin_lock_irqsave(&sc->node_lock, flags);
  1187. an = ath_node_find(sc, sta->addr);
  1188. spin_unlock_irqrestore(&sc->node_lock, flags);
  1189. switch (cmd) {
  1190. case STA_NOTIFY_ADD:
  1191. spin_lock_irqsave(&sc->node_lock, flags);
  1192. if (!an) {
  1193. ath_node_attach(sc, sta->addr, 0);
  1194. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a node: %s\n",
  1195. __func__, print_mac(mac, sta->addr));
  1196. } else {
  1197. ath_node_get(sc, sta->addr);
  1198. }
  1199. spin_unlock_irqrestore(&sc->node_lock, flags);
  1200. break;
  1201. case STA_NOTIFY_REMOVE:
  1202. if (!an)
  1203. DPRINTF(sc, ATH_DBG_FATAL,
  1204. "%s: Removal of a non-existent node\n",
  1205. __func__);
  1206. else {
  1207. ath_node_put(sc, an, ATH9K_BH_STATUS_INTACT);
  1208. DPRINTF(sc, ATH_DBG_CONFIG, "%s: Put a node: %s\n",
  1209. __func__,
  1210. print_mac(mac, sta->addr));
  1211. }
  1212. break;
  1213. default:
  1214. break;
  1215. }
  1216. }
  1217. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1218. u16 queue,
  1219. const struct ieee80211_tx_queue_params *params)
  1220. {
  1221. struct ath_softc *sc = hw->priv;
  1222. struct ath9k_tx_queue_info qi;
  1223. int ret = 0, qnum;
  1224. if (queue >= WME_NUM_AC)
  1225. return 0;
  1226. qi.tqi_aifs = params->aifs;
  1227. qi.tqi_cwmin = params->cw_min;
  1228. qi.tqi_cwmax = params->cw_max;
  1229. qi.tqi_burstTime = params->txop;
  1230. qnum = ath_get_hal_qnum(queue, sc);
  1231. DPRINTF(sc, ATH_DBG_CONFIG,
  1232. "%s: Configure tx [queue/halq] [%d/%d], "
  1233. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1234. __func__,
  1235. queue,
  1236. qnum,
  1237. params->aifs,
  1238. params->cw_min,
  1239. params->cw_max,
  1240. params->txop);
  1241. ret = ath_txq_update(sc, qnum, &qi);
  1242. if (ret)
  1243. DPRINTF(sc, ATH_DBG_FATAL,
  1244. "%s: TXQ Update failed\n", __func__);
  1245. return ret;
  1246. }
  1247. static int ath9k_set_key(struct ieee80211_hw *hw,
  1248. enum set_key_cmd cmd,
  1249. const u8 *local_addr,
  1250. const u8 *addr,
  1251. struct ieee80211_key_conf *key)
  1252. {
  1253. struct ath_softc *sc = hw->priv;
  1254. int ret = 0;
  1255. DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
  1256. switch (cmd) {
  1257. case SET_KEY:
  1258. ret = ath_key_config(sc, addr, key);
  1259. if (!ret) {
  1260. set_bit(key->keyidx, sc->sc_keymap);
  1261. key->hw_key_idx = key->keyidx;
  1262. /* push IV and Michael MIC generation to stack */
  1263. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1264. if (key->alg == ALG_TKIP)
  1265. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1266. }
  1267. break;
  1268. case DISABLE_KEY:
  1269. ath_key_delete(sc, key);
  1270. clear_bit(key->keyidx, sc->sc_keymap);
  1271. break;
  1272. default:
  1273. ret = -EINVAL;
  1274. }
  1275. return ret;
  1276. }
  1277. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1278. struct ieee80211_vif *vif,
  1279. struct ieee80211_bss_conf *bss_conf,
  1280. u32 changed)
  1281. {
  1282. struct ath_softc *sc = hw->priv;
  1283. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1284. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
  1285. __func__,
  1286. bss_conf->use_short_preamble);
  1287. if (bss_conf->use_short_preamble)
  1288. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1289. else
  1290. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1291. }
  1292. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1293. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
  1294. __func__,
  1295. bss_conf->use_cts_prot);
  1296. if (bss_conf->use_cts_prot &&
  1297. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1298. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1299. else
  1300. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1301. }
  1302. if (changed & BSS_CHANGED_HT) {
  1303. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT %d\n",
  1304. __func__,
  1305. bss_conf->assoc_ht);
  1306. ath9k_ht_conf(sc, bss_conf);
  1307. }
  1308. if (changed & BSS_CHANGED_ASSOC) {
  1309. DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
  1310. __func__,
  1311. bss_conf->assoc);
  1312. ath9k_bss_assoc_info(sc, bss_conf);
  1313. }
  1314. }
  1315. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1316. {
  1317. u64 tsf;
  1318. struct ath_softc *sc = hw->priv;
  1319. struct ath_hal *ah = sc->sc_ah;
  1320. tsf = ath9k_hw_gettsf64(ah);
  1321. return tsf;
  1322. }
  1323. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1324. {
  1325. struct ath_softc *sc = hw->priv;
  1326. struct ath_hal *ah = sc->sc_ah;
  1327. ath9k_hw_reset_tsf(ah);
  1328. }
  1329. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1330. enum ieee80211_ampdu_mlme_action action,
  1331. struct ieee80211_sta *sta,
  1332. u16 tid, u16 *ssn)
  1333. {
  1334. struct ath_softc *sc = hw->priv;
  1335. int ret = 0;
  1336. switch (action) {
  1337. case IEEE80211_AMPDU_RX_START:
  1338. ret = ath_rx_aggr_start(sc, sta->addr, tid, ssn);
  1339. if (ret < 0)
  1340. DPRINTF(sc, ATH_DBG_FATAL,
  1341. "%s: Unable to start RX aggregation\n",
  1342. __func__);
  1343. break;
  1344. case IEEE80211_AMPDU_RX_STOP:
  1345. ret = ath_rx_aggr_stop(sc, sta->addr, tid);
  1346. if (ret < 0)
  1347. DPRINTF(sc, ATH_DBG_FATAL,
  1348. "%s: Unable to stop RX aggregation\n",
  1349. __func__);
  1350. break;
  1351. case IEEE80211_AMPDU_TX_START:
  1352. ret = ath_tx_aggr_start(sc, sta->addr, tid, ssn);
  1353. if (ret < 0)
  1354. DPRINTF(sc, ATH_DBG_FATAL,
  1355. "%s: Unable to start TX aggregation\n",
  1356. __func__);
  1357. else
  1358. ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  1359. break;
  1360. case IEEE80211_AMPDU_TX_STOP:
  1361. ret = ath_tx_aggr_stop(sc, sta->addr, tid);
  1362. if (ret < 0)
  1363. DPRINTF(sc, ATH_DBG_FATAL,
  1364. "%s: Unable to stop TX aggregation\n",
  1365. __func__);
  1366. ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
  1367. break;
  1368. default:
  1369. DPRINTF(sc, ATH_DBG_FATAL,
  1370. "%s: Unknown AMPDU action\n", __func__);
  1371. }
  1372. return ret;
  1373. }
  1374. static struct ieee80211_ops ath9k_ops = {
  1375. .tx = ath9k_tx,
  1376. .start = ath9k_start,
  1377. .stop = ath9k_stop,
  1378. .add_interface = ath9k_add_interface,
  1379. .remove_interface = ath9k_remove_interface,
  1380. .config = ath9k_config,
  1381. .config_interface = ath9k_config_interface,
  1382. .configure_filter = ath9k_configure_filter,
  1383. .get_stats = NULL,
  1384. .sta_notify = ath9k_sta_notify,
  1385. .conf_tx = ath9k_conf_tx,
  1386. .get_tx_stats = NULL,
  1387. .bss_info_changed = ath9k_bss_info_changed,
  1388. .set_tim = NULL,
  1389. .set_key = ath9k_set_key,
  1390. .hw_scan = NULL,
  1391. .get_tkip_seq = NULL,
  1392. .set_rts_threshold = NULL,
  1393. .set_frag_threshold = NULL,
  1394. .set_retry_limit = NULL,
  1395. .get_tsf = ath9k_get_tsf,
  1396. .reset_tsf = ath9k_reset_tsf,
  1397. .tx_last_beacon = NULL,
  1398. .ampdu_action = ath9k_ampdu_action
  1399. };
  1400. static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1401. {
  1402. void __iomem *mem;
  1403. struct ath_softc *sc;
  1404. struct ieee80211_hw *hw;
  1405. const char *athname;
  1406. u8 csz;
  1407. u32 val;
  1408. int ret = 0;
  1409. if (pci_enable_device(pdev))
  1410. return -EIO;
  1411. /* XXX 32-bit addressing only */
  1412. if (pci_set_dma_mask(pdev, 0xffffffff)) {
  1413. printk(KERN_ERR "ath_pci: 32-bit DMA not available\n");
  1414. ret = -ENODEV;
  1415. goto bad;
  1416. }
  1417. /*
  1418. * Cache line size is used to size and align various
  1419. * structures used to communicate with the hardware.
  1420. */
  1421. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
  1422. if (csz == 0) {
  1423. /*
  1424. * Linux 2.4.18 (at least) writes the cache line size
  1425. * register as a 16-bit wide register which is wrong.
  1426. * We must have this setup properly for rx buffer
  1427. * DMA to work so force a reasonable value here if it
  1428. * comes up zero.
  1429. */
  1430. csz = L1_CACHE_BYTES / sizeof(u32);
  1431. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
  1432. }
  1433. /*
  1434. * The default setting of latency timer yields poor results,
  1435. * set it to the value used by other systems. It may be worth
  1436. * tweaking this setting more.
  1437. */
  1438. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
  1439. pci_set_master(pdev);
  1440. /*
  1441. * Disable the RETRY_TIMEOUT register (0x41) to keep
  1442. * PCI Tx retries from interfering with C3 CPU state.
  1443. */
  1444. pci_read_config_dword(pdev, 0x40, &val);
  1445. if ((val & 0x0000ff00) != 0)
  1446. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1447. ret = pci_request_region(pdev, 0, "ath9k");
  1448. if (ret) {
  1449. dev_err(&pdev->dev, "PCI memory region reserve error\n");
  1450. ret = -ENODEV;
  1451. goto bad;
  1452. }
  1453. mem = pci_iomap(pdev, 0, 0);
  1454. if (!mem) {
  1455. printk(KERN_ERR "PCI memory map error\n") ;
  1456. ret = -EIO;
  1457. goto bad1;
  1458. }
  1459. hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
  1460. if (hw == NULL) {
  1461. printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
  1462. goto bad2;
  1463. }
  1464. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  1465. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  1466. IEEE80211_HW_SIGNAL_DBM |
  1467. IEEE80211_HW_NOISE_DBM;
  1468. hw->wiphy->interface_modes =
  1469. BIT(NL80211_IFTYPE_AP) |
  1470. BIT(NL80211_IFTYPE_STATION) |
  1471. BIT(NL80211_IFTYPE_ADHOC);
  1472. SET_IEEE80211_DEV(hw, &pdev->dev);
  1473. pci_set_drvdata(pdev, hw);
  1474. sc = hw->priv;
  1475. sc->hw = hw;
  1476. sc->pdev = pdev;
  1477. sc->mem = mem;
  1478. if (ath_attach(id->device, sc) != 0) {
  1479. ret = -ENODEV;
  1480. goto bad3;
  1481. }
  1482. /* setup interrupt service routine */
  1483. if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
  1484. printk(KERN_ERR "%s: request_irq failed\n",
  1485. wiphy_name(hw->wiphy));
  1486. ret = -EIO;
  1487. goto bad4;
  1488. }
  1489. athname = ath9k_hw_probe(id->vendor, id->device);
  1490. printk(KERN_INFO "%s: %s: mem=0x%lx, irq=%d\n",
  1491. wiphy_name(hw->wiphy),
  1492. athname ? athname : "Atheros ???",
  1493. (unsigned long)mem, pdev->irq);
  1494. return 0;
  1495. bad4:
  1496. ath_detach(sc);
  1497. bad3:
  1498. ieee80211_free_hw(hw);
  1499. bad2:
  1500. pci_iounmap(pdev, mem);
  1501. bad1:
  1502. pci_release_region(pdev, 0);
  1503. bad:
  1504. pci_disable_device(pdev);
  1505. return ret;
  1506. }
  1507. static void ath_pci_remove(struct pci_dev *pdev)
  1508. {
  1509. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1510. struct ath_softc *sc = hw->priv;
  1511. enum ath9k_int status;
  1512. if (pdev->irq) {
  1513. ath9k_hw_set_interrupts(sc->sc_ah, 0);
  1514. /* clear the ISR */
  1515. ath9k_hw_getisr(sc->sc_ah, &status);
  1516. sc->sc_flags |= SC_OP_INVALID;
  1517. free_irq(pdev->irq, sc);
  1518. }
  1519. ath_detach(sc);
  1520. pci_iounmap(pdev, sc->mem);
  1521. pci_release_region(pdev, 0);
  1522. pci_disable_device(pdev);
  1523. ieee80211_free_hw(hw);
  1524. }
  1525. #ifdef CONFIG_PM
  1526. static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  1527. {
  1528. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1529. struct ath_softc *sc = hw->priv;
  1530. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  1531. #ifdef CONFIG_RFKILL
  1532. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1533. cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
  1534. #endif
  1535. pci_save_state(pdev);
  1536. pci_disable_device(pdev);
  1537. pci_set_power_state(pdev, 3);
  1538. return 0;
  1539. }
  1540. static int ath_pci_resume(struct pci_dev *pdev)
  1541. {
  1542. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1543. struct ath_softc *sc = hw->priv;
  1544. u32 val;
  1545. int err;
  1546. err = pci_enable_device(pdev);
  1547. if (err)
  1548. return err;
  1549. pci_restore_state(pdev);
  1550. /*
  1551. * Suspend/Resume resets the PCI configuration space, so we have to
  1552. * re-disable the RETRY_TIMEOUT register (0x41) to keep
  1553. * PCI Tx retries from interfering with C3 CPU state
  1554. */
  1555. pci_read_config_dword(pdev, 0x40, &val);
  1556. if ((val & 0x0000ff00) != 0)
  1557. pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
  1558. /* Enable LED */
  1559. ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
  1560. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  1561. ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
  1562. #ifdef CONFIG_RFKILL
  1563. /*
  1564. * check the h/w rfkill state on resume
  1565. * and start the rfkill poll timer
  1566. */
  1567. if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1568. queue_delayed_work(sc->hw->workqueue,
  1569. &sc->rf_kill.rfkill_poll, 0);
  1570. #endif
  1571. return 0;
  1572. }
  1573. #endif /* CONFIG_PM */
  1574. MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
  1575. static struct pci_driver ath_pci_driver = {
  1576. .name = "ath9k",
  1577. .id_table = ath_pci_id_table,
  1578. .probe = ath_pci_probe,
  1579. .remove = ath_pci_remove,
  1580. #ifdef CONFIG_PM
  1581. .suspend = ath_pci_suspend,
  1582. .resume = ath_pci_resume,
  1583. #endif /* CONFIG_PM */
  1584. };
  1585. static int __init init_ath_pci(void)
  1586. {
  1587. printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
  1588. if (pci_register_driver(&ath_pci_driver) < 0) {
  1589. printk(KERN_ERR
  1590. "ath_pci: No devices found, driver not installed.\n");
  1591. pci_unregister_driver(&ath_pci_driver);
  1592. return -ENODEV;
  1593. }
  1594. return 0;
  1595. }
  1596. module_init(init_ath_pci);
  1597. static void __exit exit_ath_pci(void)
  1598. {
  1599. pci_unregister_driver(&ath_pci_driver);
  1600. printk(KERN_INFO "%s: driver unloaded\n", dev_info);
  1601. }
  1602. module_exit(exit_ath_pci);