sdricoh_cs.c 14 KB

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  1. /*
  2. * sdricoh_cs.c - driver for Ricoh Secure Digital Card Readers that can be
  3. * found on some Ricoh RL5c476 II cardbus bridge
  4. *
  5. * Copyright (C) 2006 - 2008 Sascha Sommer <saschasommer@freenet.de>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. *
  21. */
  22. /*
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. */
  26. #include <linux/delay.h>
  27. #include <linux/highmem.h>
  28. #include <linux/pci.h>
  29. #include <linux/ioport.h>
  30. #include <linux/scatterlist.h>
  31. #include <pcmcia/cs_types.h>
  32. #include <pcmcia/cs.h>
  33. #include <pcmcia/cistpl.h>
  34. #include <pcmcia/ds.h>
  35. #include <linux/io.h>
  36. #include <linux/mmc/host.h>
  37. #define DRIVER_NAME "sdricoh_cs"
  38. static unsigned int switchlocked;
  39. /* i/o region */
  40. #define SDRICOH_PCI_REGION 0
  41. #define SDRICOH_PCI_REGION_SIZE 0x1000
  42. /* registers */
  43. #define R104_VERSION 0x104
  44. #define R200_CMD 0x200
  45. #define R204_CMD_ARG 0x204
  46. #define R208_DATAIO 0x208
  47. #define R20C_RESP 0x20c
  48. #define R21C_STATUS 0x21c
  49. #define R2E0_INIT 0x2e0
  50. #define R2E4_STATUS_RESP 0x2e4
  51. #define R2F0_RESET 0x2f0
  52. #define R224_MODE 0x224
  53. #define R226_BLOCKSIZE 0x226
  54. #define R228_POWER 0x228
  55. #define R230_DATA 0x230
  56. /* flags for the R21C_STATUS register */
  57. #define STATUS_CMD_FINISHED 0x00000001
  58. #define STATUS_TRANSFER_FINISHED 0x00000004
  59. #define STATUS_CARD_INSERTED 0x00000020
  60. #define STATUS_CARD_LOCKED 0x00000080
  61. #define STATUS_CMD_TIMEOUT 0x00400000
  62. #define STATUS_READY_TO_READ 0x01000000
  63. #define STATUS_READY_TO_WRITE 0x02000000
  64. #define STATUS_BUSY 0x40000000
  65. /* timeouts */
  66. #define INIT_TIMEOUT 100
  67. #define CMD_TIMEOUT 100000
  68. #define TRANSFER_TIMEOUT 100000
  69. #define BUSY_TIMEOUT 32767
  70. /* list of supported pcmcia devices */
  71. static struct pcmcia_device_id pcmcia_ids[] = {
  72. /* vendor and device strings followed by their crc32 hashes */
  73. PCMCIA_DEVICE_PROD_ID12("RICOH", "Bay1Controller", 0xd9f522ed,
  74. 0xc3901202),
  75. PCMCIA_DEVICE_NULL,
  76. };
  77. MODULE_DEVICE_TABLE(pcmcia, pcmcia_ids);
  78. /* mmc privdata */
  79. struct sdricoh_host {
  80. struct device *dev;
  81. struct mmc_host *mmc; /* MMC structure */
  82. unsigned char __iomem *iobase;
  83. struct pci_dev *pci_dev;
  84. int app_cmd;
  85. };
  86. /***************** register i/o helper functions *****************************/
  87. static inline unsigned int sdricoh_readl(struct sdricoh_host *host,
  88. unsigned int reg)
  89. {
  90. unsigned int value = readl(host->iobase + reg);
  91. dev_vdbg(host->dev, "rl %x 0x%x\n", reg, value);
  92. return value;
  93. }
  94. static inline void sdricoh_writel(struct sdricoh_host *host, unsigned int reg,
  95. unsigned int value)
  96. {
  97. writel(value, host->iobase + reg);
  98. dev_vdbg(host->dev, "wl %x 0x%x\n", reg, value);
  99. }
  100. static inline unsigned int sdricoh_readw(struct sdricoh_host *host,
  101. unsigned int reg)
  102. {
  103. unsigned int value = readw(host->iobase + reg);
  104. dev_vdbg(host->dev, "rb %x 0x%x\n", reg, value);
  105. return value;
  106. }
  107. static inline void sdricoh_writew(struct sdricoh_host *host, unsigned int reg,
  108. unsigned short value)
  109. {
  110. writew(value, host->iobase + reg);
  111. dev_vdbg(host->dev, "ww %x 0x%x\n", reg, value);
  112. }
  113. static inline unsigned int sdricoh_readb(struct sdricoh_host *host,
  114. unsigned int reg)
  115. {
  116. unsigned int value = readb(host->iobase + reg);
  117. dev_vdbg(host->dev, "rb %x 0x%x\n", reg, value);
  118. return value;
  119. }
  120. static int sdricoh_query_status(struct sdricoh_host *host, unsigned int wanted,
  121. unsigned int timeout){
  122. unsigned int loop;
  123. unsigned int status = 0;
  124. struct device *dev = host->dev;
  125. for (loop = 0; loop < timeout; loop++) {
  126. status = sdricoh_readl(host, R21C_STATUS);
  127. sdricoh_writel(host, R2E4_STATUS_RESP, status);
  128. if (status & wanted)
  129. break;
  130. }
  131. if (loop == timeout) {
  132. dev_err(dev, "query_status: timeout waiting for %x\n", wanted);
  133. return -ETIMEDOUT;
  134. }
  135. /* do not do this check in the loop as some commands fail otherwise */
  136. if (status & 0x7F0000) {
  137. dev_err(dev, "waiting for status bit %x failed\n", wanted);
  138. return -EINVAL;
  139. }
  140. return 0;
  141. }
  142. static int sdricoh_mmc_cmd(struct sdricoh_host *host, unsigned char opcode,
  143. unsigned int arg)
  144. {
  145. unsigned int status;
  146. int result = 0;
  147. unsigned int loop = 0;
  148. /* reset status reg? */
  149. sdricoh_writel(host, R21C_STATUS, 0x18);
  150. /* fill parameters */
  151. sdricoh_writel(host, R204_CMD_ARG, arg);
  152. sdricoh_writel(host, R200_CMD, (0x10000 << 8) | opcode);
  153. /* wait for command completion */
  154. if (opcode) {
  155. for (loop = 0; loop < CMD_TIMEOUT; loop++) {
  156. status = sdricoh_readl(host, R21C_STATUS);
  157. sdricoh_writel(host, R2E4_STATUS_RESP, status);
  158. if (status & STATUS_CMD_FINISHED)
  159. break;
  160. }
  161. /* don't check for timeout in the loop it is not always
  162. reset correctly
  163. */
  164. if (loop == CMD_TIMEOUT || status & STATUS_CMD_TIMEOUT)
  165. result = -ETIMEDOUT;
  166. }
  167. return result;
  168. }
  169. static int sdricoh_reset(struct sdricoh_host *host)
  170. {
  171. dev_dbg(host->dev, "reset\n");
  172. sdricoh_writel(host, R2F0_RESET, 0x10001);
  173. sdricoh_writel(host, R2E0_INIT, 0x10000);
  174. if (sdricoh_readl(host, R2E0_INIT) != 0x10000)
  175. return -EIO;
  176. sdricoh_writel(host, R2E0_INIT, 0x10007);
  177. sdricoh_writel(host, R224_MODE, 0x2000000);
  178. sdricoh_writel(host, R228_POWER, 0xe0);
  179. /* status register ? */
  180. sdricoh_writel(host, R21C_STATUS, 0x18);
  181. return 0;
  182. }
  183. static int sdricoh_blockio(struct sdricoh_host *host, int read,
  184. u8 *buf, int len)
  185. {
  186. int size;
  187. u32 data = 0;
  188. /* wait until the data is available */
  189. if (read) {
  190. if (sdricoh_query_status(host, STATUS_READY_TO_READ,
  191. TRANSFER_TIMEOUT))
  192. return -ETIMEDOUT;
  193. sdricoh_writel(host, R21C_STATUS, 0x18);
  194. /* read data */
  195. while (len) {
  196. data = sdricoh_readl(host, R230_DATA);
  197. size = min(len, 4);
  198. len -= size;
  199. while (size) {
  200. *buf = data & 0xFF;
  201. buf++;
  202. data >>= 8;
  203. size--;
  204. }
  205. }
  206. } else {
  207. if (sdricoh_query_status(host, STATUS_READY_TO_WRITE,
  208. TRANSFER_TIMEOUT))
  209. return -ETIMEDOUT;
  210. sdricoh_writel(host, R21C_STATUS, 0x18);
  211. /* write data */
  212. while (len) {
  213. size = min(len, 4);
  214. len -= size;
  215. while (size) {
  216. data >>= 8;
  217. data |= (u32)*buf << 24;
  218. buf++;
  219. size--;
  220. }
  221. sdricoh_writel(host, R230_DATA, data);
  222. }
  223. }
  224. if (len)
  225. return -EIO;
  226. return 0;
  227. }
  228. static void sdricoh_request(struct mmc_host *mmc, struct mmc_request *mrq)
  229. {
  230. struct sdricoh_host *host = mmc_priv(mmc);
  231. struct mmc_command *cmd = mrq->cmd;
  232. struct mmc_data *data = cmd->data;
  233. struct device *dev = host->dev;
  234. unsigned char opcode = cmd->opcode;
  235. int i;
  236. dev_dbg(dev, "=============================\n");
  237. dev_dbg(dev, "sdricoh_request opcode=%i\n", opcode);
  238. sdricoh_writel(host, R21C_STATUS, 0x18);
  239. /* MMC_APP_CMDs need some special handling */
  240. if (host->app_cmd) {
  241. opcode |= 64;
  242. host->app_cmd = 0;
  243. } else if (opcode == 55)
  244. host->app_cmd = 1;
  245. /* read/write commands seem to require this */
  246. if (data) {
  247. sdricoh_writew(host, R226_BLOCKSIZE, data->blksz);
  248. sdricoh_writel(host, R208_DATAIO, 0);
  249. }
  250. cmd->error = sdricoh_mmc_cmd(host, opcode, cmd->arg);
  251. /* read response buffer */
  252. if (cmd->flags & MMC_RSP_PRESENT) {
  253. if (cmd->flags & MMC_RSP_136) {
  254. /* CRC is stripped so we need to do some shifting. */
  255. for (i = 0; i < 4; i++) {
  256. cmd->resp[i] =
  257. sdricoh_readl(host,
  258. R20C_RESP + (3 - i) * 4) << 8;
  259. if (i != 3)
  260. cmd->resp[i] |=
  261. sdricoh_readb(host, R20C_RESP +
  262. (3 - i) * 4 - 1);
  263. }
  264. } else
  265. cmd->resp[0] = sdricoh_readl(host, R20C_RESP);
  266. }
  267. /* transfer data */
  268. if (data && cmd->error == 0) {
  269. dev_dbg(dev, "transfer: blksz %i blocks %i sg_len %i "
  270. "sg length %i\n", data->blksz, data->blocks,
  271. data->sg_len, data->sg->length);
  272. /* enter data reading mode */
  273. sdricoh_writel(host, R21C_STATUS, 0x837f031e);
  274. for (i = 0; i < data->blocks; i++) {
  275. size_t len = data->blksz;
  276. u8 *buf;
  277. struct page *page;
  278. int result;
  279. page = sg_page(data->sg);
  280. buf = kmap(page) + data->sg->offset + (len * i);
  281. result =
  282. sdricoh_blockio(host,
  283. data->flags & MMC_DATA_READ, buf, len);
  284. kunmap(page);
  285. flush_dcache_page(page);
  286. if (result) {
  287. dev_err(dev, "sdricoh_request: cmd %i "
  288. "block transfer failed\n", cmd->opcode);
  289. cmd->error = result;
  290. break;
  291. } else
  292. data->bytes_xfered += len;
  293. }
  294. sdricoh_writel(host, R208_DATAIO, 1);
  295. if (sdricoh_query_status(host, STATUS_TRANSFER_FINISHED,
  296. TRANSFER_TIMEOUT)) {
  297. dev_err(dev, "sdricoh_request: transfer end error\n");
  298. cmd->error = -EINVAL;
  299. }
  300. }
  301. /* FIXME check busy flag */
  302. mmc_request_done(mmc, mrq);
  303. dev_dbg(dev, "=============================\n");
  304. }
  305. static void sdricoh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  306. {
  307. struct sdricoh_host *host = mmc_priv(mmc);
  308. dev_dbg(host->dev, "set_ios\n");
  309. if (ios->power_mode == MMC_POWER_ON) {
  310. sdricoh_writel(host, R228_POWER, 0xc0e0);
  311. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  312. sdricoh_writel(host, R224_MODE, 0x2000300);
  313. sdricoh_writel(host, R228_POWER, 0x40e0);
  314. } else {
  315. sdricoh_writel(host, R224_MODE, 0x2000340);
  316. }
  317. } else if (ios->power_mode == MMC_POWER_UP) {
  318. sdricoh_writel(host, R224_MODE, 0x2000320);
  319. sdricoh_writel(host, R228_POWER, 0xe0);
  320. }
  321. }
  322. static int sdricoh_get_ro(struct mmc_host *mmc)
  323. {
  324. struct sdricoh_host *host = mmc_priv(mmc);
  325. unsigned int status;
  326. status = sdricoh_readl(host, R21C_STATUS);
  327. sdricoh_writel(host, R2E4_STATUS_RESP, status);
  328. /* some notebooks seem to have the locked flag switched */
  329. if (switchlocked)
  330. return !(status & STATUS_CARD_LOCKED);
  331. return (status & STATUS_CARD_LOCKED);
  332. }
  333. static struct mmc_host_ops sdricoh_ops = {
  334. .request = sdricoh_request,
  335. .set_ios = sdricoh_set_ios,
  336. .get_ro = sdricoh_get_ro,
  337. };
  338. /* initialize the control and register it to the mmc framework */
  339. static int sdricoh_init_mmc(struct pci_dev *pci_dev,
  340. struct pcmcia_device *pcmcia_dev)
  341. {
  342. int result = 0;
  343. void __iomem *iobase = NULL;
  344. struct mmc_host *mmc = NULL;
  345. struct sdricoh_host *host = NULL;
  346. struct device *dev = &pcmcia_dev->dev;
  347. /* map iomem */
  348. if (pci_resource_len(pci_dev, SDRICOH_PCI_REGION) !=
  349. SDRICOH_PCI_REGION_SIZE) {
  350. dev_dbg(dev, "unexpected pci resource len\n");
  351. return -ENODEV;
  352. }
  353. iobase =
  354. pci_iomap(pci_dev, SDRICOH_PCI_REGION, SDRICOH_PCI_REGION_SIZE);
  355. if (!iobase) {
  356. dev_err(dev, "unable to map iobase\n");
  357. return -ENODEV;
  358. }
  359. /* check version? */
  360. if (readl(iobase + R104_VERSION) != 0x4000) {
  361. dev_dbg(dev, "no supported mmc controller found\n");
  362. result = -ENODEV;
  363. goto err;
  364. }
  365. /* allocate privdata */
  366. mmc = pcmcia_dev->priv =
  367. mmc_alloc_host(sizeof(struct sdricoh_host), &pcmcia_dev->dev);
  368. if (!mmc) {
  369. dev_err(dev, "mmc_alloc_host failed\n");
  370. result = -ENOMEM;
  371. goto err;
  372. }
  373. host = mmc_priv(mmc);
  374. host->iobase = iobase;
  375. host->dev = dev;
  376. host->pci_dev = pci_dev;
  377. mmc->ops = &sdricoh_ops;
  378. /* FIXME: frequency and voltage handling is done by the controller
  379. */
  380. mmc->f_min = 450000;
  381. mmc->f_max = 24000000;
  382. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  383. mmc->caps |= MMC_CAP_4_BIT_DATA;
  384. mmc->max_seg_size = 1024 * 512;
  385. mmc->max_blk_size = 512;
  386. /* reset the controler */
  387. if (sdricoh_reset(host)) {
  388. dev_dbg(dev, "could not reset\n");
  389. result = -EIO;
  390. goto err;
  391. }
  392. result = mmc_add_host(mmc);
  393. if (!result) {
  394. dev_dbg(dev, "mmc host registered\n");
  395. return 0;
  396. }
  397. err:
  398. if (iobase)
  399. iounmap(iobase);
  400. if (mmc)
  401. mmc_free_host(mmc);
  402. return result;
  403. }
  404. /* search for supported mmc controllers */
  405. static int sdricoh_pcmcia_probe(struct pcmcia_device *pcmcia_dev)
  406. {
  407. struct pci_dev *pci_dev = NULL;
  408. dev_info(&pcmcia_dev->dev, "Searching MMC controller for pcmcia device"
  409. " %s %s ...\n", pcmcia_dev->prod_id[0], pcmcia_dev->prod_id[1]);
  410. /* search pci cardbus bridge that contains the mmc controler */
  411. /* the io region is already claimed by yenta_socket... */
  412. while ((pci_dev =
  413. pci_get_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476,
  414. pci_dev))) {
  415. /* try to init the device */
  416. if (!sdricoh_init_mmc(pci_dev, pcmcia_dev)) {
  417. dev_info(&pcmcia_dev->dev, "MMC controller found\n");
  418. return 0;
  419. }
  420. }
  421. dev_err(&pcmcia_dev->dev, "No MMC controller was found.\n");
  422. return -ENODEV;
  423. }
  424. static void sdricoh_pcmcia_detach(struct pcmcia_device *link)
  425. {
  426. struct mmc_host *mmc = link->priv;
  427. dev_dbg(&link->dev, "detach\n");
  428. /* remove mmc host */
  429. if (mmc) {
  430. struct sdricoh_host *host = mmc_priv(mmc);
  431. mmc_remove_host(mmc);
  432. pci_iounmap(host->pci_dev, host->iobase);
  433. pci_dev_put(host->pci_dev);
  434. mmc_free_host(mmc);
  435. }
  436. pcmcia_disable_device(link);
  437. }
  438. #ifdef CONFIG_PM
  439. static int sdricoh_pcmcia_suspend(struct pcmcia_device *link)
  440. {
  441. struct mmc_host *mmc = link->priv;
  442. dev_dbg(&link->dev, "suspend\n");
  443. mmc_suspend_host(mmc, PMSG_SUSPEND);
  444. return 0;
  445. }
  446. static int sdricoh_pcmcia_resume(struct pcmcia_device *link)
  447. {
  448. struct mmc_host *mmc = link->priv;
  449. dev_dbg(&link->dev, "resume\n");
  450. sdricoh_reset(mmc_priv(mmc));
  451. mmc_resume_host(mmc);
  452. return 0;
  453. }
  454. #else
  455. #define sdricoh_pcmcia_suspend NULL
  456. #define sdricoh_pcmcia_resume NULL
  457. #endif
  458. static struct pcmcia_driver sdricoh_driver = {
  459. .drv = {
  460. .name = DRIVER_NAME,
  461. },
  462. .probe = sdricoh_pcmcia_probe,
  463. .remove = sdricoh_pcmcia_detach,
  464. .id_table = pcmcia_ids,
  465. .suspend = sdricoh_pcmcia_suspend,
  466. .resume = sdricoh_pcmcia_resume,
  467. };
  468. /*****************************************************************************\
  469. * *
  470. * Driver init/exit *
  471. * *
  472. \*****************************************************************************/
  473. static int __init sdricoh_drv_init(void)
  474. {
  475. return pcmcia_register_driver(&sdricoh_driver);
  476. }
  477. static void __exit sdricoh_drv_exit(void)
  478. {
  479. pcmcia_unregister_driver(&sdricoh_driver);
  480. }
  481. module_init(sdricoh_drv_init);
  482. module_exit(sdricoh_drv_exit);
  483. module_param(switchlocked, uint, 0444);
  484. MODULE_AUTHOR("Sascha Sommer <saschasommer@freenet.de>");
  485. MODULE_DESCRIPTION("Ricoh PCMCIA Secure Digital Interface driver");
  486. MODULE_LICENSE("GPL");
  487. MODULE_PARM_DESC(switchlocked, "Switch the cards locked status."
  488. "Use this when unlocked cards are shown readonly (default 0)");