ucb1x00.h 6.7 KB

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  1. /*
  2. * linux/drivers/mfd/ucb1x00.h
  3. *
  4. * Copyright (C) 2001 Russell King, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License.
  9. */
  10. #ifndef UCB1200_H
  11. #define UCB1200_H
  12. #define UCB_IO_DATA 0x00
  13. #define UCB_IO_DIR 0x01
  14. #define UCB_IO_0 (1 << 0)
  15. #define UCB_IO_1 (1 << 1)
  16. #define UCB_IO_2 (1 << 2)
  17. #define UCB_IO_3 (1 << 3)
  18. #define UCB_IO_4 (1 << 4)
  19. #define UCB_IO_5 (1 << 5)
  20. #define UCB_IO_6 (1 << 6)
  21. #define UCB_IO_7 (1 << 7)
  22. #define UCB_IO_8 (1 << 8)
  23. #define UCB_IO_9 (1 << 9)
  24. #define UCB_IE_RIS 0x02
  25. #define UCB_IE_FAL 0x03
  26. #define UCB_IE_STATUS 0x04
  27. #define UCB_IE_CLEAR 0x04
  28. #define UCB_IE_ADC (1 << 11)
  29. #define UCB_IE_TSPX (1 << 12)
  30. #define UCB_IE_TSMX (1 << 13)
  31. #define UCB_IE_TCLIP (1 << 14)
  32. #define UCB_IE_ACLIP (1 << 15)
  33. #define UCB_IRQ_TSPX 12
  34. #define UCB_TC_A 0x05
  35. #define UCB_TC_A_LOOP (1 << 7) /* UCB1200 */
  36. #define UCB_TC_A_AMPL (1 << 7) /* UCB1300 */
  37. #define UCB_TC_B 0x06
  38. #define UCB_TC_B_VOICE_ENA (1 << 3)
  39. #define UCB_TC_B_CLIP (1 << 4)
  40. #define UCB_TC_B_ATT (1 << 6)
  41. #define UCB_TC_B_SIDE_ENA (1 << 11)
  42. #define UCB_TC_B_MUTE (1 << 13)
  43. #define UCB_TC_B_IN_ENA (1 << 14)
  44. #define UCB_TC_B_OUT_ENA (1 << 15)
  45. #define UCB_AC_A 0x07
  46. #define UCB_AC_B 0x08
  47. #define UCB_AC_B_LOOP (1 << 8)
  48. #define UCB_AC_B_MUTE (1 << 13)
  49. #define UCB_AC_B_IN_ENA (1 << 14)
  50. #define UCB_AC_B_OUT_ENA (1 << 15)
  51. #define UCB_TS_CR 0x09
  52. #define UCB_TS_CR_TSMX_POW (1 << 0)
  53. #define UCB_TS_CR_TSPX_POW (1 << 1)
  54. #define UCB_TS_CR_TSMY_POW (1 << 2)
  55. #define UCB_TS_CR_TSPY_POW (1 << 3)
  56. #define UCB_TS_CR_TSMX_GND (1 << 4)
  57. #define UCB_TS_CR_TSPX_GND (1 << 5)
  58. #define UCB_TS_CR_TSMY_GND (1 << 6)
  59. #define UCB_TS_CR_TSPY_GND (1 << 7)
  60. #define UCB_TS_CR_MODE_INT (0 << 8)
  61. #define UCB_TS_CR_MODE_PRES (1 << 8)
  62. #define UCB_TS_CR_MODE_POS (2 << 8)
  63. #define UCB_TS_CR_BIAS_ENA (1 << 11)
  64. #define UCB_TS_CR_TSPX_LOW (1 << 12)
  65. #define UCB_TS_CR_TSMX_LOW (1 << 13)
  66. #define UCB_ADC_CR 0x0a
  67. #define UCB_ADC_SYNC_ENA (1 << 0)
  68. #define UCB_ADC_VREFBYP_CON (1 << 1)
  69. #define UCB_ADC_INP_TSPX (0 << 2)
  70. #define UCB_ADC_INP_TSMX (1 << 2)
  71. #define UCB_ADC_INP_TSPY (2 << 2)
  72. #define UCB_ADC_INP_TSMY (3 << 2)
  73. #define UCB_ADC_INP_AD0 (4 << 2)
  74. #define UCB_ADC_INP_AD1 (5 << 2)
  75. #define UCB_ADC_INP_AD2 (6 << 2)
  76. #define UCB_ADC_INP_AD3 (7 << 2)
  77. #define UCB_ADC_EXT_REF (1 << 5)
  78. #define UCB_ADC_START (1 << 7)
  79. #define UCB_ADC_ENA (1 << 15)
  80. #define UCB_ADC_DATA 0x0b
  81. #define UCB_ADC_DAT_VAL (1 << 15)
  82. #define UCB_ADC_DAT(x) (((x) & 0x7fe0) >> 5)
  83. #define UCB_ID 0x0c
  84. #define UCB_ID_1200 0x1004
  85. #define UCB_ID_1300 0x1005
  86. #define UCB_ID_TC35143 0x9712
  87. #define UCB_MODE 0x0d
  88. #define UCB_MODE_DYN_VFLAG_ENA (1 << 12)
  89. #define UCB_MODE_AUD_OFF_CAN (1 << 13)
  90. #include "mcp.h"
  91. struct ucb1x00_irq {
  92. void *devid;
  93. void (*fn)(int, void *);
  94. };
  95. struct ucb1x00 {
  96. spinlock_t lock;
  97. struct mcp *mcp;
  98. unsigned int irq;
  99. struct semaphore adc_sem;
  100. spinlock_t io_lock;
  101. u16 id;
  102. u16 io_dir;
  103. u16 io_out;
  104. u16 adc_cr;
  105. u16 irq_fal_enbl;
  106. u16 irq_ris_enbl;
  107. struct ucb1x00_irq irq_handler[16];
  108. struct device dev;
  109. struct list_head node;
  110. struct list_head devs;
  111. };
  112. struct ucb1x00_driver;
  113. struct ucb1x00_dev {
  114. struct list_head dev_node;
  115. struct list_head drv_node;
  116. struct ucb1x00 *ucb;
  117. struct ucb1x00_driver *drv;
  118. void *priv;
  119. };
  120. struct ucb1x00_driver {
  121. struct list_head node;
  122. struct list_head devs;
  123. int (*add)(struct ucb1x00_dev *dev);
  124. void (*remove)(struct ucb1x00_dev *dev);
  125. int (*suspend)(struct ucb1x00_dev *dev, pm_message_t state);
  126. int (*resume)(struct ucb1x00_dev *dev);
  127. };
  128. #define classdev_to_ucb1x00(cd) container_of(cd, struct ucb1x00, dev)
  129. int ucb1x00_register_driver(struct ucb1x00_driver *);
  130. void ucb1x00_unregister_driver(struct ucb1x00_driver *);
  131. /**
  132. * ucb1x00_clkrate - return the UCB1x00 SIB clock rate
  133. * @ucb: UCB1x00 structure describing chip
  134. *
  135. * Return the SIB clock rate in Hz.
  136. */
  137. static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
  138. {
  139. return mcp_get_sclk_rate(ucb->mcp);
  140. }
  141. /**
  142. * ucb1x00_enable - enable the UCB1x00 SIB clock
  143. * @ucb: UCB1x00 structure describing chip
  144. *
  145. * Enable the SIB clock. This can be called multiple times.
  146. */
  147. static inline void ucb1x00_enable(struct ucb1x00 *ucb)
  148. {
  149. mcp_enable(ucb->mcp);
  150. }
  151. /**
  152. * ucb1x00_disable - disable the UCB1x00 SIB clock
  153. * @ucb: UCB1x00 structure describing chip
  154. *
  155. * Disable the SIB clock. The SIB clock will only be disabled
  156. * when the number of ucb1x00_enable calls match the number of
  157. * ucb1x00_disable calls.
  158. */
  159. static inline void ucb1x00_disable(struct ucb1x00 *ucb)
  160. {
  161. mcp_disable(ucb->mcp);
  162. }
  163. /**
  164. * ucb1x00_reg_write - write a UCB1x00 register
  165. * @ucb: UCB1x00 structure describing chip
  166. * @reg: UCB1x00 4-bit register index to write
  167. * @val: UCB1x00 16-bit value to write
  168. *
  169. * Write the UCB1x00 register @reg with value @val. The SIB
  170. * clock must be running for this function to return.
  171. */
  172. static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val)
  173. {
  174. mcp_reg_write(ucb->mcp, reg, val);
  175. }
  176. /**
  177. * ucb1x00_reg_read - read a UCB1x00 register
  178. * @ucb: UCB1x00 structure describing chip
  179. * @reg: UCB1x00 4-bit register index to write
  180. *
  181. * Read the UCB1x00 register @reg and return its value. The SIB
  182. * clock must be running for this function to return.
  183. */
  184. static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg)
  185. {
  186. return mcp_reg_read(ucb->mcp, reg);
  187. }
  188. /**
  189. * ucb1x00_set_audio_divisor -
  190. * @ucb: UCB1x00 structure describing chip
  191. * @div: SIB clock divisor
  192. */
  193. static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div)
  194. {
  195. mcp_set_audio_divisor(ucb->mcp, div);
  196. }
  197. /**
  198. * ucb1x00_set_telecom_divisor -
  199. * @ucb: UCB1x00 structure describing chip
  200. * @div: SIB clock divisor
  201. */
  202. static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div)
  203. {
  204. mcp_set_telecom_divisor(ucb->mcp, div);
  205. }
  206. void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int, unsigned int);
  207. void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int, unsigned int);
  208. unsigned int ucb1x00_io_read(struct ucb1x00 *ucb);
  209. #define UCB_NOSYNC (0)
  210. #define UCB_SYNC (1)
  211. unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
  212. void ucb1x00_adc_enable(struct ucb1x00 *ucb);
  213. void ucb1x00_adc_disable(struct ucb1x00 *ucb);
  214. /*
  215. * Which edges of the IRQ do you want to control today?
  216. */
  217. #define UCB_RISING (1 << 0)
  218. #define UCB_FALLING (1 << 1)
  219. int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid);
  220. void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
  221. void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
  222. int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid);
  223. #endif