ucb1x00-core.c 16 KB

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  1. /*
  2. * linux/drivers/mfd/ucb1x00-core.c
  3. *
  4. * Copyright (C) 2001 Russell King, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License.
  9. *
  10. * The UCB1x00 core driver provides basic services for handling IO,
  11. * the ADC, interrupts, and accessing registers. It is designed
  12. * such that everything goes through this layer, thereby providing
  13. * a consistent locking methodology, as well as allowing the drivers
  14. * to be used on other non-MCP-enabled hardware platforms.
  15. *
  16. * Note that all locks are private to this file. Nothing else may
  17. * touch them.
  18. */
  19. #include <linux/module.h>
  20. #include <linux/kernel.h>
  21. #include <linux/slab.h>
  22. #include <linux/init.h>
  23. #include <linux/errno.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/device.h>
  26. #include <linux/mutex.h>
  27. #include <asm/dma.h>
  28. #include <mach/hardware.h>
  29. #include "ucb1x00.h"
  30. static DEFINE_MUTEX(ucb1x00_mutex);
  31. static LIST_HEAD(ucb1x00_drivers);
  32. static LIST_HEAD(ucb1x00_devices);
  33. /**
  34. * ucb1x00_io_set_dir - set IO direction
  35. * @ucb: UCB1x00 structure describing chip
  36. * @in: bitfield of IO pins to be set as inputs
  37. * @out: bitfield of IO pins to be set as outputs
  38. *
  39. * Set the IO direction of the ten general purpose IO pins on
  40. * the UCB1x00 chip. The @in bitfield has priority over the
  41. * @out bitfield, in that if you specify a pin as both input
  42. * and output, it will end up as an input.
  43. *
  44. * ucb1x00_enable must have been called to enable the comms
  45. * before using this function.
  46. *
  47. * This function takes a spinlock, disabling interrupts.
  48. */
  49. void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out)
  50. {
  51. unsigned long flags;
  52. spin_lock_irqsave(&ucb->io_lock, flags);
  53. ucb->io_dir |= out;
  54. ucb->io_dir &= ~in;
  55. ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
  56. spin_unlock_irqrestore(&ucb->io_lock, flags);
  57. }
  58. /**
  59. * ucb1x00_io_write - set or clear IO outputs
  60. * @ucb: UCB1x00 structure describing chip
  61. * @set: bitfield of IO pins to set to logic '1'
  62. * @clear: bitfield of IO pins to set to logic '0'
  63. *
  64. * Set the IO output state of the specified IO pins. The value
  65. * is retained if the pins are subsequently configured as inputs.
  66. * The @clear bitfield has priority over the @set bitfield -
  67. * outputs will be cleared.
  68. *
  69. * ucb1x00_enable must have been called to enable the comms
  70. * before using this function.
  71. *
  72. * This function takes a spinlock, disabling interrupts.
  73. */
  74. void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear)
  75. {
  76. unsigned long flags;
  77. spin_lock_irqsave(&ucb->io_lock, flags);
  78. ucb->io_out |= set;
  79. ucb->io_out &= ~clear;
  80. ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
  81. spin_unlock_irqrestore(&ucb->io_lock, flags);
  82. }
  83. /**
  84. * ucb1x00_io_read - read the current state of the IO pins
  85. * @ucb: UCB1x00 structure describing chip
  86. *
  87. * Return a bitfield describing the logic state of the ten
  88. * general purpose IO pins.
  89. *
  90. * ucb1x00_enable must have been called to enable the comms
  91. * before using this function.
  92. *
  93. * This function does not take any semaphores or spinlocks.
  94. */
  95. unsigned int ucb1x00_io_read(struct ucb1x00 *ucb)
  96. {
  97. return ucb1x00_reg_read(ucb, UCB_IO_DATA);
  98. }
  99. /*
  100. * UCB1300 data sheet says we must:
  101. * 1. enable ADC => 5us (including reference startup time)
  102. * 2. select input => 51*tsibclk => 4.3us
  103. * 3. start conversion => 102*tsibclk => 8.5us
  104. * (tsibclk = 1/11981000)
  105. * Period between SIB 128-bit frames = 10.7us
  106. */
  107. /**
  108. * ucb1x00_adc_enable - enable the ADC converter
  109. * @ucb: UCB1x00 structure describing chip
  110. *
  111. * Enable the ucb1x00 and ADC converter on the UCB1x00 for use.
  112. * Any code wishing to use the ADC converter must call this
  113. * function prior to using it.
  114. *
  115. * This function takes the ADC semaphore to prevent two or more
  116. * concurrent uses, and therefore may sleep. As a result, it
  117. * can only be called from process context, not interrupt
  118. * context.
  119. *
  120. * You should release the ADC as soon as possible using
  121. * ucb1x00_adc_disable.
  122. */
  123. void ucb1x00_adc_enable(struct ucb1x00 *ucb)
  124. {
  125. down(&ucb->adc_sem);
  126. ucb->adc_cr |= UCB_ADC_ENA;
  127. ucb1x00_enable(ucb);
  128. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
  129. }
  130. /**
  131. * ucb1x00_adc_read - read the specified ADC channel
  132. * @ucb: UCB1x00 structure describing chip
  133. * @adc_channel: ADC channel mask
  134. * @sync: wait for syncronisation pulse.
  135. *
  136. * Start an ADC conversion and wait for the result. Note that
  137. * synchronised ADC conversions (via the ADCSYNC pin) must wait
  138. * until the trigger is asserted and the conversion is finished.
  139. *
  140. * This function currently spins waiting for the conversion to
  141. * complete (2 frames max without sync).
  142. *
  143. * If called for a synchronised ADC conversion, it may sleep
  144. * with the ADC semaphore held.
  145. */
  146. unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync)
  147. {
  148. unsigned int val;
  149. if (sync)
  150. adc_channel |= UCB_ADC_SYNC_ENA;
  151. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel);
  152. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START);
  153. for (;;) {
  154. val = ucb1x00_reg_read(ucb, UCB_ADC_DATA);
  155. if (val & UCB_ADC_DAT_VAL)
  156. break;
  157. /* yield to other processes */
  158. set_current_state(TASK_INTERRUPTIBLE);
  159. schedule_timeout(1);
  160. }
  161. return UCB_ADC_DAT(val);
  162. }
  163. /**
  164. * ucb1x00_adc_disable - disable the ADC converter
  165. * @ucb: UCB1x00 structure describing chip
  166. *
  167. * Disable the ADC converter and release the ADC semaphore.
  168. */
  169. void ucb1x00_adc_disable(struct ucb1x00 *ucb)
  170. {
  171. ucb->adc_cr &= ~UCB_ADC_ENA;
  172. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
  173. ucb1x00_disable(ucb);
  174. up(&ucb->adc_sem);
  175. }
  176. /*
  177. * UCB1x00 Interrupt handling.
  178. *
  179. * The UCB1x00 can generate interrupts when the SIBCLK is stopped.
  180. * Since we need to read an internal register, we must re-enable
  181. * SIBCLK to talk to the chip. We leave the clock running until
  182. * we have finished processing all interrupts from the chip.
  183. */
  184. static irqreturn_t ucb1x00_irq(int irqnr, void *devid)
  185. {
  186. struct ucb1x00 *ucb = devid;
  187. struct ucb1x00_irq *irq;
  188. unsigned int isr, i;
  189. ucb1x00_enable(ucb);
  190. isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS);
  191. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr);
  192. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
  193. for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++)
  194. if (isr & 1 && irq->fn)
  195. irq->fn(i, irq->devid);
  196. ucb1x00_disable(ucb);
  197. return IRQ_HANDLED;
  198. }
  199. /**
  200. * ucb1x00_hook_irq - hook a UCB1x00 interrupt
  201. * @ucb: UCB1x00 structure describing chip
  202. * @idx: interrupt index
  203. * @fn: function to call when interrupt is triggered
  204. * @devid: device id to pass to interrupt handler
  205. *
  206. * Hook the specified interrupt. You can only register one handler
  207. * for each interrupt source. The interrupt source is not enabled
  208. * by this function; use ucb1x00_enable_irq instead.
  209. *
  210. * Interrupt handlers will be called with other interrupts enabled.
  211. *
  212. * Returns zero on success, or one of the following errors:
  213. * -EINVAL if the interrupt index is invalid
  214. * -EBUSY if the interrupt has already been hooked
  215. */
  216. int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid)
  217. {
  218. struct ucb1x00_irq *irq;
  219. int ret = -EINVAL;
  220. if (idx < 16) {
  221. irq = ucb->irq_handler + idx;
  222. ret = -EBUSY;
  223. spin_lock_irq(&ucb->lock);
  224. if (irq->fn == NULL) {
  225. irq->devid = devid;
  226. irq->fn = fn;
  227. ret = 0;
  228. }
  229. spin_unlock_irq(&ucb->lock);
  230. }
  231. return ret;
  232. }
  233. /**
  234. * ucb1x00_enable_irq - enable an UCB1x00 interrupt source
  235. * @ucb: UCB1x00 structure describing chip
  236. * @idx: interrupt index
  237. * @edges: interrupt edges to enable
  238. *
  239. * Enable the specified interrupt to trigger on %UCB_RISING,
  240. * %UCB_FALLING or both edges. The interrupt should have been
  241. * hooked by ucb1x00_hook_irq.
  242. */
  243. void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
  244. {
  245. unsigned long flags;
  246. if (idx < 16) {
  247. spin_lock_irqsave(&ucb->lock, flags);
  248. ucb1x00_enable(ucb);
  249. if (edges & UCB_RISING) {
  250. ucb->irq_ris_enbl |= 1 << idx;
  251. ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
  252. }
  253. if (edges & UCB_FALLING) {
  254. ucb->irq_fal_enbl |= 1 << idx;
  255. ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
  256. }
  257. ucb1x00_disable(ucb);
  258. spin_unlock_irqrestore(&ucb->lock, flags);
  259. }
  260. }
  261. /**
  262. * ucb1x00_disable_irq - disable an UCB1x00 interrupt source
  263. * @ucb: UCB1x00 structure describing chip
  264. * @edges: interrupt edges to disable
  265. *
  266. * Disable the specified interrupt triggering on the specified
  267. * (%UCB_RISING, %UCB_FALLING or both) edges.
  268. */
  269. void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
  270. {
  271. unsigned long flags;
  272. if (idx < 16) {
  273. spin_lock_irqsave(&ucb->lock, flags);
  274. ucb1x00_enable(ucb);
  275. if (edges & UCB_RISING) {
  276. ucb->irq_ris_enbl &= ~(1 << idx);
  277. ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
  278. }
  279. if (edges & UCB_FALLING) {
  280. ucb->irq_fal_enbl &= ~(1 << idx);
  281. ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
  282. }
  283. ucb1x00_disable(ucb);
  284. spin_unlock_irqrestore(&ucb->lock, flags);
  285. }
  286. }
  287. /**
  288. * ucb1x00_free_irq - disable and free the specified UCB1x00 interrupt
  289. * @ucb: UCB1x00 structure describing chip
  290. * @idx: interrupt index
  291. * @devid: device id.
  292. *
  293. * Disable the interrupt source and remove the handler. devid must
  294. * match the devid passed when hooking the interrupt.
  295. *
  296. * Returns zero on success, or one of the following errors:
  297. * -EINVAL if the interrupt index is invalid
  298. * -ENOENT if devid does not match
  299. */
  300. int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid)
  301. {
  302. struct ucb1x00_irq *irq;
  303. int ret;
  304. if (idx >= 16)
  305. goto bad;
  306. irq = ucb->irq_handler + idx;
  307. ret = -ENOENT;
  308. spin_lock_irq(&ucb->lock);
  309. if (irq->devid == devid) {
  310. ucb->irq_ris_enbl &= ~(1 << idx);
  311. ucb->irq_fal_enbl &= ~(1 << idx);
  312. ucb1x00_enable(ucb);
  313. ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
  314. ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
  315. ucb1x00_disable(ucb);
  316. irq->fn = NULL;
  317. irq->devid = NULL;
  318. ret = 0;
  319. }
  320. spin_unlock_irq(&ucb->lock);
  321. return ret;
  322. bad:
  323. printk(KERN_ERR "Freeing bad UCB1x00 irq %d\n", idx);
  324. return -EINVAL;
  325. }
  326. static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv)
  327. {
  328. struct ucb1x00_dev *dev;
  329. int ret = -ENOMEM;
  330. dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL);
  331. if (dev) {
  332. dev->ucb = ucb;
  333. dev->drv = drv;
  334. ret = drv->add(dev);
  335. if (ret == 0) {
  336. list_add(&dev->dev_node, &ucb->devs);
  337. list_add(&dev->drv_node, &drv->devs);
  338. } else {
  339. kfree(dev);
  340. }
  341. }
  342. return ret;
  343. }
  344. static void ucb1x00_remove_dev(struct ucb1x00_dev *dev)
  345. {
  346. dev->drv->remove(dev);
  347. list_del(&dev->dev_node);
  348. list_del(&dev->drv_node);
  349. kfree(dev);
  350. }
  351. /*
  352. * Try to probe our interrupt, rather than relying on lots of
  353. * hard-coded machine dependencies. For reference, the expected
  354. * IRQ mappings are:
  355. *
  356. * Machine Default IRQ
  357. * adsbitsy IRQ_GPCIN4
  358. * cerf IRQ_GPIO_UCB1200_IRQ
  359. * flexanet IRQ_GPIO_GUI
  360. * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ
  361. * graphicsclient ADS_EXT_IRQ(8)
  362. * graphicsmaster ADS_EXT_IRQ(8)
  363. * lart LART_IRQ_UCB1200
  364. * omnimeter IRQ_GPIO23
  365. * pfs168 IRQ_GPIO_UCB1300_IRQ
  366. * simpad IRQ_GPIO_UCB1300_IRQ
  367. * shannon SHANNON_IRQ_GPIO_IRQ_CODEC
  368. * yopy IRQ_GPIO_UCB1200_IRQ
  369. */
  370. static int ucb1x00_detect_irq(struct ucb1x00 *ucb)
  371. {
  372. unsigned long mask;
  373. mask = probe_irq_on();
  374. if (!mask) {
  375. probe_irq_off(mask);
  376. return NO_IRQ;
  377. }
  378. /*
  379. * Enable the ADC interrupt.
  380. */
  381. ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
  382. ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
  383. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  384. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
  385. /*
  386. * Cause an ADC interrupt.
  387. */
  388. ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
  389. ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
  390. /*
  391. * Wait for the conversion to complete.
  392. */
  393. while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0);
  394. ucb1x00_reg_write(ucb, UCB_ADC_CR, 0);
  395. /*
  396. * Disable and clear interrupt.
  397. */
  398. ucb1x00_reg_write(ucb, UCB_IE_RIS, 0);
  399. ucb1x00_reg_write(ucb, UCB_IE_FAL, 0);
  400. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  401. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
  402. /*
  403. * Read triggered interrupt.
  404. */
  405. return probe_irq_off(mask);
  406. }
  407. static void ucb1x00_release(struct device *dev)
  408. {
  409. struct ucb1x00 *ucb = classdev_to_ucb1x00(dev);
  410. kfree(ucb);
  411. }
  412. static struct class ucb1x00_class = {
  413. .name = "ucb1x00",
  414. .dev_release = ucb1x00_release,
  415. };
  416. static int ucb1x00_probe(struct mcp *mcp)
  417. {
  418. struct ucb1x00 *ucb;
  419. struct ucb1x00_driver *drv;
  420. unsigned int id;
  421. int ret = -ENODEV;
  422. mcp_enable(mcp);
  423. id = mcp_reg_read(mcp, UCB_ID);
  424. if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) {
  425. printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id);
  426. goto err_disable;
  427. }
  428. ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL);
  429. ret = -ENOMEM;
  430. if (!ucb)
  431. goto err_disable;
  432. ucb->dev.class = &ucb1x00_class;
  433. ucb->dev.parent = &mcp->attached_device;
  434. strlcpy(ucb->dev.bus_id, "ucb1x00", sizeof(ucb->dev.bus_id));
  435. spin_lock_init(&ucb->lock);
  436. spin_lock_init(&ucb->io_lock);
  437. sema_init(&ucb->adc_sem, 1);
  438. ucb->id = id;
  439. ucb->mcp = mcp;
  440. ucb->irq = ucb1x00_detect_irq(ucb);
  441. if (ucb->irq == NO_IRQ) {
  442. printk(KERN_ERR "UCB1x00: IRQ probe failed\n");
  443. ret = -ENODEV;
  444. goto err_free;
  445. }
  446. ret = request_irq(ucb->irq, ucb1x00_irq, IRQF_TRIGGER_RISING,
  447. "UCB1x00", ucb);
  448. if (ret) {
  449. printk(KERN_ERR "ucb1x00: unable to grab irq%d: %d\n",
  450. ucb->irq, ret);
  451. goto err_free;
  452. }
  453. mcp_set_drvdata(mcp, ucb);
  454. ret = device_register(&ucb->dev);
  455. if (ret)
  456. goto err_irq;
  457. INIT_LIST_HEAD(&ucb->devs);
  458. mutex_lock(&ucb1x00_mutex);
  459. list_add(&ucb->node, &ucb1x00_devices);
  460. list_for_each_entry(drv, &ucb1x00_drivers, node) {
  461. ucb1x00_add_dev(ucb, drv);
  462. }
  463. mutex_unlock(&ucb1x00_mutex);
  464. goto out;
  465. err_irq:
  466. free_irq(ucb->irq, ucb);
  467. err_free:
  468. kfree(ucb);
  469. err_disable:
  470. mcp_disable(mcp);
  471. out:
  472. return ret;
  473. }
  474. static void ucb1x00_remove(struct mcp *mcp)
  475. {
  476. struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
  477. struct list_head *l, *n;
  478. mutex_lock(&ucb1x00_mutex);
  479. list_del(&ucb->node);
  480. list_for_each_safe(l, n, &ucb->devs) {
  481. struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node);
  482. ucb1x00_remove_dev(dev);
  483. }
  484. mutex_unlock(&ucb1x00_mutex);
  485. free_irq(ucb->irq, ucb);
  486. device_unregister(&ucb->dev);
  487. }
  488. int ucb1x00_register_driver(struct ucb1x00_driver *drv)
  489. {
  490. struct ucb1x00 *ucb;
  491. INIT_LIST_HEAD(&drv->devs);
  492. mutex_lock(&ucb1x00_mutex);
  493. list_add(&drv->node, &ucb1x00_drivers);
  494. list_for_each_entry(ucb, &ucb1x00_devices, node) {
  495. ucb1x00_add_dev(ucb, drv);
  496. }
  497. mutex_unlock(&ucb1x00_mutex);
  498. return 0;
  499. }
  500. void ucb1x00_unregister_driver(struct ucb1x00_driver *drv)
  501. {
  502. struct list_head *n, *l;
  503. mutex_lock(&ucb1x00_mutex);
  504. list_del(&drv->node);
  505. list_for_each_safe(l, n, &drv->devs) {
  506. struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node);
  507. ucb1x00_remove_dev(dev);
  508. }
  509. mutex_unlock(&ucb1x00_mutex);
  510. }
  511. static int ucb1x00_suspend(struct mcp *mcp, pm_message_t state)
  512. {
  513. struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
  514. struct ucb1x00_dev *dev;
  515. mutex_lock(&ucb1x00_mutex);
  516. list_for_each_entry(dev, &ucb->devs, dev_node) {
  517. if (dev->drv->suspend)
  518. dev->drv->suspend(dev, state);
  519. }
  520. mutex_unlock(&ucb1x00_mutex);
  521. return 0;
  522. }
  523. static int ucb1x00_resume(struct mcp *mcp)
  524. {
  525. struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
  526. struct ucb1x00_dev *dev;
  527. mutex_lock(&ucb1x00_mutex);
  528. list_for_each_entry(dev, &ucb->devs, dev_node) {
  529. if (dev->drv->resume)
  530. dev->drv->resume(dev);
  531. }
  532. mutex_unlock(&ucb1x00_mutex);
  533. return 0;
  534. }
  535. static struct mcp_driver ucb1x00_driver = {
  536. .drv = {
  537. .name = "ucb1x00",
  538. },
  539. .probe = ucb1x00_probe,
  540. .remove = ucb1x00_remove,
  541. .suspend = ucb1x00_suspend,
  542. .resume = ucb1x00_resume,
  543. };
  544. static int __init ucb1x00_init(void)
  545. {
  546. int ret = class_register(&ucb1x00_class);
  547. if (ret == 0) {
  548. ret = mcp_driver_register(&ucb1x00_driver);
  549. if (ret)
  550. class_unregister(&ucb1x00_class);
  551. }
  552. return ret;
  553. }
  554. static void __exit ucb1x00_exit(void)
  555. {
  556. mcp_driver_unregister(&ucb1x00_driver);
  557. class_unregister(&ucb1x00_class);
  558. }
  559. module_init(ucb1x00_init);
  560. module_exit(ucb1x00_exit);
  561. EXPORT_SYMBOL(ucb1x00_io_set_dir);
  562. EXPORT_SYMBOL(ucb1x00_io_write);
  563. EXPORT_SYMBOL(ucb1x00_io_read);
  564. EXPORT_SYMBOL(ucb1x00_adc_enable);
  565. EXPORT_SYMBOL(ucb1x00_adc_read);
  566. EXPORT_SYMBOL(ucb1x00_adc_disable);
  567. EXPORT_SYMBOL(ucb1x00_hook_irq);
  568. EXPORT_SYMBOL(ucb1x00_free_irq);
  569. EXPORT_SYMBOL(ucb1x00_enable_irq);
  570. EXPORT_SYMBOL(ucb1x00_disable_irq);
  571. EXPORT_SYMBOL(ucb1x00_register_driver);
  572. EXPORT_SYMBOL(ucb1x00_unregister_driver);
  573. MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
  574. MODULE_DESCRIPTION("UCB1x00 core driver");
  575. MODULE_LICENSE("GPL");