netjet.c 26 KB

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  1. /* $Id: netjet.c,v 1.29.2.4 2004/02/11 13:21:34 keil Exp $
  2. *
  3. * low level stuff for Traverse Technologie NETJet ISDN cards
  4. *
  5. * Author Karsten Keil
  6. * Copyright by Karsten Keil <keil@isdn4linux.de>
  7. *
  8. * This software may be used and distributed according to the terms
  9. * of the GNU General Public License, incorporated herein by reference.
  10. *
  11. * Thanks to Traverse Technologies Australia for documents and information
  12. *
  13. * 16-Apr-2002 - led code added - Guy Ellis (guy@traverse.com.au)
  14. *
  15. */
  16. #include <linux/init.h>
  17. #include "hisax.h"
  18. #include "isac.h"
  19. #include "hscx.h"
  20. #include "isdnl1.h"
  21. #include <linux/interrupt.h>
  22. #include <linux/ppp_defs.h>
  23. #include <asm/io.h>
  24. #include "netjet.h"
  25. /* Interface functions */
  26. u_char
  27. NETjet_ReadIC(struct IsdnCardState *cs, u_char offset)
  28. {
  29. u_char ret;
  30. cs->hw.njet.auxd &= 0xfc;
  31. cs->hw.njet.auxd |= (offset>>4) & 3;
  32. byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
  33. ret = bytein(cs->hw.njet.isac + ((offset & 0xf)<<2));
  34. return(ret);
  35. }
  36. void
  37. NETjet_WriteIC(struct IsdnCardState *cs, u_char offset, u_char value)
  38. {
  39. cs->hw.njet.auxd &= 0xfc;
  40. cs->hw.njet.auxd |= (offset>>4) & 3;
  41. byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
  42. byteout(cs->hw.njet.isac + ((offset & 0xf)<<2), value);
  43. }
  44. void
  45. NETjet_ReadICfifo(struct IsdnCardState *cs, u_char *data, int size)
  46. {
  47. cs->hw.njet.auxd &= 0xfc;
  48. byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
  49. insb(cs->hw.njet.isac, data, size);
  50. }
  51. void
  52. NETjet_WriteICfifo(struct IsdnCardState *cs, u_char *data, int size)
  53. {
  54. cs->hw.njet.auxd &= 0xfc;
  55. byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
  56. outsb(cs->hw.njet.isac, data, size);
  57. }
  58. static void fill_mem(struct BCState *bcs, u_int *pos, u_int cnt, int chan, u_char fill)
  59. {
  60. u_int mask=0x000000ff, val = 0, *p=pos;
  61. u_int i;
  62. val |= fill;
  63. if (chan) {
  64. val <<= 8;
  65. mask <<= 8;
  66. }
  67. mask ^= 0xffffffff;
  68. for (i=0; i<cnt; i++) {
  69. *p &= mask;
  70. *p++ |= val;
  71. if (p > bcs->hw.tiger.s_end)
  72. p = bcs->hw.tiger.send;
  73. }
  74. }
  75. static void
  76. mode_tiger(struct BCState *bcs, int mode, int bc)
  77. {
  78. struct IsdnCardState *cs = bcs->cs;
  79. u_char led;
  80. if (cs->debug & L1_DEB_HSCX)
  81. debugl1(cs, "Tiger mode %d bchan %d/%d",
  82. mode, bc, bcs->channel);
  83. bcs->mode = mode;
  84. bcs->channel = bc;
  85. switch (mode) {
  86. case (L1_MODE_NULL):
  87. fill_mem(bcs, bcs->hw.tiger.send,
  88. NETJET_DMA_TXSIZE, bc, 0xff);
  89. if (cs->debug & L1_DEB_HSCX)
  90. debugl1(cs, "Tiger stat rec %d/%d send %d",
  91. bcs->hw.tiger.r_tot, bcs->hw.tiger.r_err,
  92. bcs->hw.tiger.s_tot);
  93. if ((cs->bcs[0].mode == L1_MODE_NULL) &&
  94. (cs->bcs[1].mode == L1_MODE_NULL)) {
  95. cs->hw.njet.dmactrl = 0;
  96. byteout(cs->hw.njet.base + NETJET_DMACTRL,
  97. cs->hw.njet.dmactrl);
  98. byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0);
  99. }
  100. if (cs->typ == ISDN_CTYPE_NETJET_S)
  101. {
  102. // led off
  103. led = bc & 0x01;
  104. led = 0x01 << (6 + led); // convert to mask
  105. led = ~led;
  106. cs->hw.njet.auxd &= led;
  107. byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
  108. }
  109. break;
  110. case (L1_MODE_TRANS):
  111. break;
  112. case (L1_MODE_HDLC_56K):
  113. case (L1_MODE_HDLC):
  114. fill_mem(bcs, bcs->hw.tiger.send,
  115. NETJET_DMA_TXSIZE, bc, 0xff);
  116. bcs->hw.tiger.r_state = HDLC_ZERO_SEARCH;
  117. bcs->hw.tiger.r_tot = 0;
  118. bcs->hw.tiger.r_bitcnt = 0;
  119. bcs->hw.tiger.r_one = 0;
  120. bcs->hw.tiger.r_err = 0;
  121. bcs->hw.tiger.s_tot = 0;
  122. if (! cs->hw.njet.dmactrl) {
  123. fill_mem(bcs, bcs->hw.tiger.send,
  124. NETJET_DMA_TXSIZE, !bc, 0xff);
  125. cs->hw.njet.dmactrl = 1;
  126. byteout(cs->hw.njet.base + NETJET_DMACTRL,
  127. cs->hw.njet.dmactrl);
  128. byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0x0f);
  129. /* was 0x3f now 0x0f for TJ300 and TJ320 GE 13/07/00 */
  130. }
  131. bcs->hw.tiger.sendp = bcs->hw.tiger.send;
  132. bcs->hw.tiger.free = NETJET_DMA_TXSIZE;
  133. test_and_set_bit(BC_FLG_EMPTY, &bcs->Flag);
  134. if (cs->typ == ISDN_CTYPE_NETJET_S)
  135. {
  136. // led on
  137. led = bc & 0x01;
  138. led = 0x01 << (6 + led); // convert to mask
  139. cs->hw.njet.auxd |= led;
  140. byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
  141. }
  142. break;
  143. }
  144. if (cs->debug & L1_DEB_HSCX)
  145. debugl1(cs, "tiger: set %x %x %x %x/%x pulse=%d",
  146. bytein(cs->hw.njet.base + NETJET_DMACTRL),
  147. bytein(cs->hw.njet.base + NETJET_IRQMASK0),
  148. bytein(cs->hw.njet.base + NETJET_IRQSTAT0),
  149. inl(cs->hw.njet.base + NETJET_DMA_READ_ADR),
  150. inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR),
  151. bytein(cs->hw.njet.base + NETJET_PULSE_CNT));
  152. }
  153. static void printframe(struct IsdnCardState *cs, u_char *buf, int count, char *s) {
  154. char tmp[128];
  155. char *t = tmp;
  156. int i=count,j;
  157. u_char *p = buf;
  158. t += sprintf(t, "tiger %s(%4d)", s, count);
  159. while (i>0) {
  160. if (i>16)
  161. j=16;
  162. else
  163. j=i;
  164. QuickHex(t, p, j);
  165. debugl1(cs, tmp);
  166. p += j;
  167. i -= j;
  168. t = tmp;
  169. t += sprintf(t, "tiger %s ", s);
  170. }
  171. }
  172. // macro for 64k
  173. #define MAKE_RAW_BYTE for (j=0; j<8; j++) { \
  174. bitcnt++;\
  175. s_val >>= 1;\
  176. if (val & 1) {\
  177. s_one++;\
  178. s_val |= 0x80;\
  179. } else {\
  180. s_one = 0;\
  181. s_val &= 0x7f;\
  182. }\
  183. if (bitcnt==8) {\
  184. bcs->hw.tiger.sendbuf[s_cnt++] = s_val;\
  185. bitcnt = 0;\
  186. }\
  187. if (s_one == 5) {\
  188. s_val >>= 1;\
  189. s_val &= 0x7f;\
  190. bitcnt++;\
  191. s_one = 0;\
  192. }\
  193. if (bitcnt==8) {\
  194. bcs->hw.tiger.sendbuf[s_cnt++] = s_val;\
  195. bitcnt = 0;\
  196. }\
  197. val >>= 1;\
  198. }
  199. static int make_raw_data(struct BCState *bcs) {
  200. // this make_raw is for 64k
  201. register u_int i,s_cnt=0;
  202. register u_char j;
  203. register u_char val;
  204. register u_char s_one = 0;
  205. register u_char s_val = 0;
  206. register u_char bitcnt = 0;
  207. u_int fcs;
  208. if (!bcs->tx_skb) {
  209. debugl1(bcs->cs, "tiger make_raw: NULL skb");
  210. return(1);
  211. }
  212. bcs->hw.tiger.sendbuf[s_cnt++] = HDLC_FLAG_VALUE;
  213. fcs = PPP_INITFCS;
  214. for (i=0; i<bcs->tx_skb->len; i++) {
  215. val = bcs->tx_skb->data[i];
  216. fcs = PPP_FCS (fcs, val);
  217. MAKE_RAW_BYTE;
  218. }
  219. fcs ^= 0xffff;
  220. val = fcs & 0xff;
  221. MAKE_RAW_BYTE;
  222. val = (fcs>>8) & 0xff;
  223. MAKE_RAW_BYTE;
  224. val = HDLC_FLAG_VALUE;
  225. for (j=0; j<8; j++) {
  226. bitcnt++;
  227. s_val >>= 1;
  228. if (val & 1)
  229. s_val |= 0x80;
  230. else
  231. s_val &= 0x7f;
  232. if (bitcnt==8) {
  233. bcs->hw.tiger.sendbuf[s_cnt++] = s_val;
  234. bitcnt = 0;
  235. }
  236. val >>= 1;
  237. }
  238. if (bcs->cs->debug & L1_DEB_HSCX)
  239. debugl1(bcs->cs,"tiger make_raw: in %ld out %d.%d",
  240. bcs->tx_skb->len, s_cnt, bitcnt);
  241. if (bitcnt) {
  242. while (8>bitcnt++) {
  243. s_val >>= 1;
  244. s_val |= 0x80;
  245. }
  246. bcs->hw.tiger.sendbuf[s_cnt++] = s_val;
  247. bcs->hw.tiger.sendbuf[s_cnt++] = 0xff; // NJ<->NJ thoughput bug fix
  248. }
  249. bcs->hw.tiger.sendcnt = s_cnt;
  250. bcs->tx_cnt -= bcs->tx_skb->len;
  251. bcs->hw.tiger.sp = bcs->hw.tiger.sendbuf;
  252. return(0);
  253. }
  254. // macro for 56k
  255. #define MAKE_RAW_BYTE_56K for (j=0; j<8; j++) { \
  256. bitcnt++;\
  257. s_val >>= 1;\
  258. if (val & 1) {\
  259. s_one++;\
  260. s_val |= 0x80;\
  261. } else {\
  262. s_one = 0;\
  263. s_val &= 0x7f;\
  264. }\
  265. if (bitcnt==7) {\
  266. s_val >>= 1;\
  267. s_val |= 0x80;\
  268. bcs->hw.tiger.sendbuf[s_cnt++] = s_val;\
  269. bitcnt = 0;\
  270. }\
  271. if (s_one == 5) {\
  272. s_val >>= 1;\
  273. s_val &= 0x7f;\
  274. bitcnt++;\
  275. s_one = 0;\
  276. }\
  277. if (bitcnt==7) {\
  278. s_val >>= 1;\
  279. s_val |= 0x80;\
  280. bcs->hw.tiger.sendbuf[s_cnt++] = s_val;\
  281. bitcnt = 0;\
  282. }\
  283. val >>= 1;\
  284. }
  285. static int make_raw_data_56k(struct BCState *bcs) {
  286. // this make_raw is for 56k
  287. register u_int i,s_cnt=0;
  288. register u_char j;
  289. register u_char val;
  290. register u_char s_one = 0;
  291. register u_char s_val = 0;
  292. register u_char bitcnt = 0;
  293. u_int fcs;
  294. if (!bcs->tx_skb) {
  295. debugl1(bcs->cs, "tiger make_raw_56k: NULL skb");
  296. return(1);
  297. }
  298. val = HDLC_FLAG_VALUE;
  299. for (j=0; j<8; j++) {
  300. bitcnt++;
  301. s_val >>= 1;
  302. if (val & 1)
  303. s_val |= 0x80;
  304. else
  305. s_val &= 0x7f;
  306. if (bitcnt==7) {
  307. s_val >>= 1;
  308. s_val |= 0x80;
  309. bcs->hw.tiger.sendbuf[s_cnt++] = s_val;
  310. bitcnt = 0;
  311. }
  312. val >>= 1;
  313. };
  314. fcs = PPP_INITFCS;
  315. for (i=0; i<bcs->tx_skb->len; i++) {
  316. val = bcs->tx_skb->data[i];
  317. fcs = PPP_FCS (fcs, val);
  318. MAKE_RAW_BYTE_56K;
  319. }
  320. fcs ^= 0xffff;
  321. val = fcs & 0xff;
  322. MAKE_RAW_BYTE_56K;
  323. val = (fcs>>8) & 0xff;
  324. MAKE_RAW_BYTE_56K;
  325. val = HDLC_FLAG_VALUE;
  326. for (j=0; j<8; j++) {
  327. bitcnt++;
  328. s_val >>= 1;
  329. if (val & 1)
  330. s_val |= 0x80;
  331. else
  332. s_val &= 0x7f;
  333. if (bitcnt==7) {
  334. s_val >>= 1;
  335. s_val |= 0x80;
  336. bcs->hw.tiger.sendbuf[s_cnt++] = s_val;
  337. bitcnt = 0;
  338. }
  339. val >>= 1;
  340. }
  341. if (bcs->cs->debug & L1_DEB_HSCX)
  342. debugl1(bcs->cs,"tiger make_raw_56k: in %ld out %d.%d",
  343. bcs->tx_skb->len, s_cnt, bitcnt);
  344. if (bitcnt) {
  345. while (8>bitcnt++) {
  346. s_val >>= 1;
  347. s_val |= 0x80;
  348. }
  349. bcs->hw.tiger.sendbuf[s_cnt++] = s_val;
  350. bcs->hw.tiger.sendbuf[s_cnt++] = 0xff; // NJ<->NJ thoughput bug fix
  351. }
  352. bcs->hw.tiger.sendcnt = s_cnt;
  353. bcs->tx_cnt -= bcs->tx_skb->len;
  354. bcs->hw.tiger.sp = bcs->hw.tiger.sendbuf;
  355. return(0);
  356. }
  357. static void got_frame(struct BCState *bcs, int count) {
  358. struct sk_buff *skb;
  359. if (!(skb = dev_alloc_skb(count)))
  360. printk(KERN_WARNING "TIGER: receive out of memory\n");
  361. else {
  362. memcpy(skb_put(skb, count), bcs->hw.tiger.rcvbuf, count);
  363. skb_queue_tail(&bcs->rqueue, skb);
  364. }
  365. test_and_set_bit(B_RCVBUFREADY, &bcs->event);
  366. schedule_work(&bcs->tqueue);
  367. if (bcs->cs->debug & L1_DEB_RECEIVE_FRAME)
  368. printframe(bcs->cs, bcs->hw.tiger.rcvbuf, count, "rec");
  369. }
  370. static void read_raw(struct BCState *bcs, u_int *buf, int cnt){
  371. int i;
  372. register u_char j;
  373. register u_char val;
  374. u_int *pend = bcs->hw.tiger.rec +NETJET_DMA_RXSIZE -1;
  375. register u_char state = bcs->hw.tiger.r_state;
  376. register u_char r_one = bcs->hw.tiger.r_one;
  377. register u_char r_val = bcs->hw.tiger.r_val;
  378. register u_int bitcnt = bcs->hw.tiger.r_bitcnt;
  379. u_int *p = buf;
  380. int bits;
  381. u_char mask;
  382. if (bcs->mode == L1_MODE_HDLC) { // it's 64k
  383. mask = 0xff;
  384. bits = 8;
  385. }
  386. else { // it's 56K
  387. mask = 0x7f;
  388. bits = 7;
  389. };
  390. for (i=0;i<cnt;i++) {
  391. val = bcs->channel ? ((*p>>8) & 0xff) : (*p & 0xff);
  392. p++;
  393. if (p > pend)
  394. p = bcs->hw.tiger.rec;
  395. if ((val & mask) == mask) {
  396. state = HDLC_ZERO_SEARCH;
  397. bcs->hw.tiger.r_tot++;
  398. bitcnt = 0;
  399. r_one = 0;
  400. continue;
  401. }
  402. for (j=0;j<bits;j++) {
  403. if (state == HDLC_ZERO_SEARCH) {
  404. if (val & 1) {
  405. r_one++;
  406. } else {
  407. r_one=0;
  408. state= HDLC_FLAG_SEARCH;
  409. if (bcs->cs->debug & L1_DEB_HSCX)
  410. debugl1(bcs->cs,"tiger read_raw: zBit(%d,%d,%d) %x",
  411. bcs->hw.tiger.r_tot,i,j,val);
  412. }
  413. } else if (state == HDLC_FLAG_SEARCH) {
  414. if (val & 1) {
  415. r_one++;
  416. if (r_one>6) {
  417. state=HDLC_ZERO_SEARCH;
  418. }
  419. } else {
  420. if (r_one==6) {
  421. bitcnt=0;
  422. r_val=0;
  423. state=HDLC_FLAG_FOUND;
  424. if (bcs->cs->debug & L1_DEB_HSCX)
  425. debugl1(bcs->cs,"tiger read_raw: flag(%d,%d,%d) %x",
  426. bcs->hw.tiger.r_tot,i,j,val);
  427. }
  428. r_one=0;
  429. }
  430. } else if (state == HDLC_FLAG_FOUND) {
  431. if (val & 1) {
  432. r_one++;
  433. if (r_one>6) {
  434. state=HDLC_ZERO_SEARCH;
  435. } else {
  436. r_val >>= 1;
  437. r_val |= 0x80;
  438. bitcnt++;
  439. }
  440. } else {
  441. if (r_one==6) {
  442. bitcnt=0;
  443. r_val=0;
  444. r_one=0;
  445. val >>= 1;
  446. continue;
  447. } else if (r_one!=5) {
  448. r_val >>= 1;
  449. r_val &= 0x7f;
  450. bitcnt++;
  451. }
  452. r_one=0;
  453. }
  454. if ((state != HDLC_ZERO_SEARCH) &&
  455. !(bitcnt & 7)) {
  456. state=HDLC_FRAME_FOUND;
  457. bcs->hw.tiger.r_fcs = PPP_INITFCS;
  458. bcs->hw.tiger.rcvbuf[0] = r_val;
  459. bcs->hw.tiger.r_fcs = PPP_FCS (bcs->hw.tiger.r_fcs, r_val);
  460. if (bcs->cs->debug & L1_DEB_HSCX)
  461. debugl1(bcs->cs,"tiger read_raw: byte1(%d,%d,%d) rval %x val %x i %x",
  462. bcs->hw.tiger.r_tot,i,j,r_val,val,
  463. bcs->cs->hw.njet.irqstat0);
  464. }
  465. } else if (state == HDLC_FRAME_FOUND) {
  466. if (val & 1) {
  467. r_one++;
  468. if (r_one>6) {
  469. state=HDLC_ZERO_SEARCH;
  470. bitcnt=0;
  471. } else {
  472. r_val >>= 1;
  473. r_val |= 0x80;
  474. bitcnt++;
  475. }
  476. } else {
  477. if (r_one==6) {
  478. r_val=0;
  479. r_one=0;
  480. bitcnt++;
  481. if (bitcnt & 7) {
  482. debugl1(bcs->cs, "tiger: frame not byte aligned");
  483. state=HDLC_FLAG_SEARCH;
  484. bcs->hw.tiger.r_err++;
  485. #ifdef ERROR_STATISTIC
  486. bcs->err_inv++;
  487. #endif
  488. } else {
  489. if (bcs->cs->debug & L1_DEB_HSCX)
  490. debugl1(bcs->cs,"tiger frame end(%d,%d): fcs(%x) i %x",
  491. i,j,bcs->hw.tiger.r_fcs, bcs->cs->hw.njet.irqstat0);
  492. if (bcs->hw.tiger.r_fcs == PPP_GOODFCS) {
  493. got_frame(bcs, (bitcnt>>3)-3);
  494. } else {
  495. if (bcs->cs->debug) {
  496. debugl1(bcs->cs, "tiger FCS error");
  497. printframe(bcs->cs, bcs->hw.tiger.rcvbuf,
  498. (bitcnt>>3)-1, "rec");
  499. bcs->hw.tiger.r_err++;
  500. }
  501. #ifdef ERROR_STATISTIC
  502. bcs->err_crc++;
  503. #endif
  504. }
  505. state=HDLC_FLAG_FOUND;
  506. }
  507. bitcnt=0;
  508. } else if (r_one==5) {
  509. val >>= 1;
  510. r_one=0;
  511. continue;
  512. } else {
  513. r_val >>= 1;
  514. r_val &= 0x7f;
  515. bitcnt++;
  516. }
  517. r_one=0;
  518. }
  519. if ((state == HDLC_FRAME_FOUND) &&
  520. !(bitcnt & 7)) {
  521. if ((bitcnt>>3)>=HSCX_BUFMAX) {
  522. debugl1(bcs->cs, "tiger: frame too big");
  523. r_val=0;
  524. state=HDLC_FLAG_SEARCH;
  525. bcs->hw.tiger.r_err++;
  526. #ifdef ERROR_STATISTIC
  527. bcs->err_inv++;
  528. #endif
  529. } else {
  530. bcs->hw.tiger.rcvbuf[(bitcnt>>3)-1] = r_val;
  531. bcs->hw.tiger.r_fcs =
  532. PPP_FCS (bcs->hw.tiger.r_fcs, r_val);
  533. }
  534. }
  535. }
  536. val >>= 1;
  537. }
  538. bcs->hw.tiger.r_tot++;
  539. }
  540. bcs->hw.tiger.r_state = state;
  541. bcs->hw.tiger.r_one = r_one;
  542. bcs->hw.tiger.r_val = r_val;
  543. bcs->hw.tiger.r_bitcnt = bitcnt;
  544. }
  545. void read_tiger(struct IsdnCardState *cs) {
  546. u_int *p;
  547. int cnt = NETJET_DMA_RXSIZE/2;
  548. if ((cs->hw.njet.irqstat0 & cs->hw.njet.last_is0) & NETJET_IRQM0_READ) {
  549. debugl1(cs,"tiger warn read double dma %x/%x",
  550. cs->hw.njet.irqstat0, cs->hw.njet.last_is0);
  551. #ifdef ERROR_STATISTIC
  552. if (cs->bcs[0].mode)
  553. cs->bcs[0].err_rdo++;
  554. if (cs->bcs[1].mode)
  555. cs->bcs[1].err_rdo++;
  556. #endif
  557. return;
  558. } else {
  559. cs->hw.njet.last_is0 &= ~NETJET_IRQM0_READ;
  560. cs->hw.njet.last_is0 |= (cs->hw.njet.irqstat0 & NETJET_IRQM0_READ);
  561. }
  562. if (cs->hw.njet.irqstat0 & NETJET_IRQM0_READ_1)
  563. p = cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE - 1;
  564. else
  565. p = cs->bcs[0].hw.tiger.rec + cnt - 1;
  566. if ((cs->bcs[0].mode == L1_MODE_HDLC) || (cs->bcs[0].mode == L1_MODE_HDLC_56K))
  567. read_raw(cs->bcs, p, cnt);
  568. if ((cs->bcs[1].mode == L1_MODE_HDLC) || (cs->bcs[1].mode == L1_MODE_HDLC_56K))
  569. read_raw(cs->bcs + 1, p, cnt);
  570. cs->hw.njet.irqstat0 &= ~NETJET_IRQM0_READ;
  571. }
  572. static void write_raw(struct BCState *bcs, u_int *buf, int cnt);
  573. void netjet_fill_dma(struct BCState *bcs)
  574. {
  575. register u_int *p, *sp;
  576. register int cnt;
  577. if (!bcs->tx_skb)
  578. return;
  579. if (bcs->cs->debug & L1_DEB_HSCX)
  580. debugl1(bcs->cs,"tiger fill_dma1: c%d %4x", bcs->channel,
  581. bcs->Flag);
  582. if (test_and_set_bit(BC_FLG_BUSY, &bcs->Flag))
  583. return;
  584. if (bcs->mode == L1_MODE_HDLC) { // it's 64k
  585. if (make_raw_data(bcs))
  586. return;
  587. }
  588. else { // it's 56k
  589. if (make_raw_data_56k(bcs))
  590. return;
  591. };
  592. if (bcs->cs->debug & L1_DEB_HSCX)
  593. debugl1(bcs->cs,"tiger fill_dma2: c%d %4x", bcs->channel,
  594. bcs->Flag);
  595. if (test_and_clear_bit(BC_FLG_NOFRAME, &bcs->Flag)) {
  596. write_raw(bcs, bcs->hw.tiger.sendp, bcs->hw.tiger.free);
  597. } else if (test_and_clear_bit(BC_FLG_HALF, &bcs->Flag)) {
  598. p = bus_to_virt(inl(bcs->cs->hw.njet.base + NETJET_DMA_READ_ADR));
  599. sp = bcs->hw.tiger.sendp;
  600. if (p == bcs->hw.tiger.s_end)
  601. p = bcs->hw.tiger.send -1;
  602. if (sp == bcs->hw.tiger.s_end)
  603. sp = bcs->hw.tiger.send -1;
  604. cnt = p - sp;
  605. if (cnt <0) {
  606. write_raw(bcs, bcs->hw.tiger.sendp, bcs->hw.tiger.free);
  607. } else {
  608. p++;
  609. cnt++;
  610. if (p > bcs->hw.tiger.s_end)
  611. p = bcs->hw.tiger.send;
  612. p++;
  613. cnt++;
  614. if (p > bcs->hw.tiger.s_end)
  615. p = bcs->hw.tiger.send;
  616. write_raw(bcs, p, bcs->hw.tiger.free - cnt);
  617. }
  618. } else if (test_and_clear_bit(BC_FLG_EMPTY, &bcs->Flag)) {
  619. p = bus_to_virt(inl(bcs->cs->hw.njet.base + NETJET_DMA_READ_ADR));
  620. cnt = bcs->hw.tiger.s_end - p;
  621. if (cnt < 2) {
  622. p = bcs->hw.tiger.send + 1;
  623. cnt = NETJET_DMA_TXSIZE/2 - 2;
  624. } else {
  625. p++;
  626. p++;
  627. if (cnt <= (NETJET_DMA_TXSIZE/2))
  628. cnt += NETJET_DMA_TXSIZE/2;
  629. cnt--;
  630. cnt--;
  631. }
  632. write_raw(bcs, p, cnt);
  633. }
  634. if (bcs->cs->debug & L1_DEB_HSCX)
  635. debugl1(bcs->cs,"tiger fill_dma3: c%d %4x", bcs->channel,
  636. bcs->Flag);
  637. }
  638. static void write_raw(struct BCState *bcs, u_int *buf, int cnt) {
  639. u_int mask, val, *p=buf;
  640. u_int i, s_cnt;
  641. if (cnt <= 0)
  642. return;
  643. if (test_bit(BC_FLG_BUSY, &bcs->Flag)) {
  644. if (bcs->hw.tiger.sendcnt> cnt) {
  645. s_cnt = cnt;
  646. bcs->hw.tiger.sendcnt -= cnt;
  647. } else {
  648. s_cnt = bcs->hw.tiger.sendcnt;
  649. bcs->hw.tiger.sendcnt = 0;
  650. }
  651. if (bcs->channel)
  652. mask = 0xffff00ff;
  653. else
  654. mask = 0xffffff00;
  655. for (i=0; i<s_cnt; i++) {
  656. val = bcs->channel ? ((bcs->hw.tiger.sp[i] <<8) & 0xff00) :
  657. (bcs->hw.tiger.sp[i]);
  658. *p &= mask;
  659. *p++ |= val;
  660. if (p>bcs->hw.tiger.s_end)
  661. p = bcs->hw.tiger.send;
  662. }
  663. bcs->hw.tiger.s_tot += s_cnt;
  664. if (bcs->cs->debug & L1_DEB_HSCX)
  665. debugl1(bcs->cs,"tiger write_raw: c%d %p-%p %d/%d %d %x", bcs->channel,
  666. buf, p, s_cnt, cnt,
  667. bcs->hw.tiger.sendcnt, bcs->cs->hw.njet.irqstat0);
  668. if (bcs->cs->debug & L1_DEB_HSCX_FIFO)
  669. printframe(bcs->cs, bcs->hw.tiger.sp, s_cnt, "snd");
  670. bcs->hw.tiger.sp += s_cnt;
  671. bcs->hw.tiger.sendp = p;
  672. if (!bcs->hw.tiger.sendcnt) {
  673. if (!bcs->tx_skb) {
  674. debugl1(bcs->cs,"tiger write_raw: NULL skb s_cnt %d", s_cnt);
  675. } else {
  676. if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
  677. (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
  678. u_long flags;
  679. spin_lock_irqsave(&bcs->aclock, flags);
  680. bcs->ackcnt += bcs->tx_skb->len;
  681. spin_unlock_irqrestore(&bcs->aclock, flags);
  682. schedule_event(bcs, B_ACKPENDING);
  683. }
  684. dev_kfree_skb_any(bcs->tx_skb);
  685. bcs->tx_skb = NULL;
  686. }
  687. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  688. bcs->hw.tiger.free = cnt - s_cnt;
  689. if (bcs->hw.tiger.free > (NETJET_DMA_TXSIZE/2))
  690. test_and_set_bit(BC_FLG_HALF, &bcs->Flag);
  691. else {
  692. test_and_clear_bit(BC_FLG_HALF, &bcs->Flag);
  693. test_and_set_bit(BC_FLG_NOFRAME, &bcs->Flag);
  694. }
  695. if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
  696. netjet_fill_dma(bcs);
  697. } else {
  698. mask ^= 0xffffffff;
  699. if (s_cnt < cnt) {
  700. for (i=s_cnt; i<cnt;i++) {
  701. *p++ |= mask;
  702. if (p>bcs->hw.tiger.s_end)
  703. p = bcs->hw.tiger.send;
  704. }
  705. if (bcs->cs->debug & L1_DEB_HSCX)
  706. debugl1(bcs->cs, "tiger write_raw: fill rest %d",
  707. cnt - s_cnt);
  708. }
  709. test_and_set_bit(B_XMTBUFREADY, &bcs->event);
  710. schedule_work(&bcs->tqueue);
  711. }
  712. }
  713. } else if (test_and_clear_bit(BC_FLG_NOFRAME, &bcs->Flag)) {
  714. test_and_set_bit(BC_FLG_HALF, &bcs->Flag);
  715. fill_mem(bcs, buf, cnt, bcs->channel, 0xff);
  716. bcs->hw.tiger.free += cnt;
  717. if (bcs->cs->debug & L1_DEB_HSCX)
  718. debugl1(bcs->cs,"tiger write_raw: fill half");
  719. } else if (test_and_clear_bit(BC_FLG_HALF, &bcs->Flag)) {
  720. test_and_set_bit(BC_FLG_EMPTY, &bcs->Flag);
  721. fill_mem(bcs, buf, cnt, bcs->channel, 0xff);
  722. if (bcs->cs->debug & L1_DEB_HSCX)
  723. debugl1(bcs->cs,"tiger write_raw: fill full");
  724. }
  725. }
  726. void write_tiger(struct IsdnCardState *cs) {
  727. u_int *p, cnt = NETJET_DMA_TXSIZE/2;
  728. if ((cs->hw.njet.irqstat0 & cs->hw.njet.last_is0) & NETJET_IRQM0_WRITE) {
  729. debugl1(cs,"tiger warn write double dma %x/%x",
  730. cs->hw.njet.irqstat0, cs->hw.njet.last_is0);
  731. #ifdef ERROR_STATISTIC
  732. if (cs->bcs[0].mode)
  733. cs->bcs[0].err_tx++;
  734. if (cs->bcs[1].mode)
  735. cs->bcs[1].err_tx++;
  736. #endif
  737. return;
  738. } else {
  739. cs->hw.njet.last_is0 &= ~NETJET_IRQM0_WRITE;
  740. cs->hw.njet.last_is0 |= (cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE);
  741. }
  742. if (cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE_1)
  743. p = cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE - 1;
  744. else
  745. p = cs->bcs[0].hw.tiger.send + cnt - 1;
  746. if ((cs->bcs[0].mode == L1_MODE_HDLC) || (cs->bcs[0].mode == L1_MODE_HDLC_56K))
  747. write_raw(cs->bcs, p, cnt);
  748. if ((cs->bcs[1].mode == L1_MODE_HDLC) || (cs->bcs[1].mode == L1_MODE_HDLC_56K))
  749. write_raw(cs->bcs + 1, p, cnt);
  750. cs->hw.njet.irqstat0 &= ~NETJET_IRQM0_WRITE;
  751. }
  752. static void
  753. tiger_l2l1(struct PStack *st, int pr, void *arg)
  754. {
  755. struct BCState *bcs = st->l1.bcs;
  756. struct sk_buff *skb = arg;
  757. u_long flags;
  758. switch (pr) {
  759. case (PH_DATA | REQUEST):
  760. spin_lock_irqsave(&bcs->cs->lock, flags);
  761. if (bcs->tx_skb) {
  762. skb_queue_tail(&bcs->squeue, skb);
  763. } else {
  764. bcs->tx_skb = skb;
  765. bcs->cs->BC_Send_Data(bcs);
  766. }
  767. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  768. break;
  769. case (PH_PULL | INDICATION):
  770. spin_lock_irqsave(&bcs->cs->lock, flags);
  771. if (bcs->tx_skb) {
  772. printk(KERN_WARNING "tiger_l2l1: this shouldn't happen\n");
  773. } else {
  774. bcs->tx_skb = skb;
  775. bcs->cs->BC_Send_Data(bcs);
  776. }
  777. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  778. break;
  779. case (PH_PULL | REQUEST):
  780. if (!bcs->tx_skb) {
  781. test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
  782. st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
  783. } else
  784. test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
  785. break;
  786. case (PH_ACTIVATE | REQUEST):
  787. spin_lock_irqsave(&bcs->cs->lock, flags);
  788. test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
  789. mode_tiger(bcs, st->l1.mode, st->l1.bc);
  790. /* 2001/10/04 Christoph Ersfeld, Formula-n Europe AG */
  791. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  792. bcs->cs->cardmsg(bcs->cs, MDL_BC_ASSIGN, (void *)(&st->l1.bc));
  793. l1_msg_b(st, pr, arg);
  794. break;
  795. case (PH_DEACTIVATE | REQUEST):
  796. /* 2001/10/04 Christoph Ersfeld, Formula-n Europe AG */
  797. bcs->cs->cardmsg(bcs->cs, MDL_BC_RELEASE, (void *)(&st->l1.bc));
  798. l1_msg_b(st, pr, arg);
  799. break;
  800. case (PH_DEACTIVATE | CONFIRM):
  801. spin_lock_irqsave(&bcs->cs->lock, flags);
  802. test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
  803. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  804. mode_tiger(bcs, 0, st->l1.bc);
  805. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  806. st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
  807. break;
  808. }
  809. }
  810. static void
  811. close_tigerstate(struct BCState *bcs)
  812. {
  813. mode_tiger(bcs, 0, bcs->channel);
  814. if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
  815. kfree(bcs->hw.tiger.rcvbuf);
  816. bcs->hw.tiger.rcvbuf = NULL;
  817. kfree(bcs->hw.tiger.sendbuf);
  818. bcs->hw.tiger.sendbuf = NULL;
  819. skb_queue_purge(&bcs->rqueue);
  820. skb_queue_purge(&bcs->squeue);
  821. if (bcs->tx_skb) {
  822. dev_kfree_skb_any(bcs->tx_skb);
  823. bcs->tx_skb = NULL;
  824. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  825. }
  826. }
  827. }
  828. static int
  829. open_tigerstate(struct IsdnCardState *cs, struct BCState *bcs)
  830. {
  831. if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
  832. if (!(bcs->hw.tiger.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
  833. printk(KERN_WARNING
  834. "HiSax: No memory for tiger.rcvbuf\n");
  835. return (1);
  836. }
  837. if (!(bcs->hw.tiger.sendbuf = kmalloc(RAW_BUFMAX, GFP_ATOMIC))) {
  838. printk(KERN_WARNING
  839. "HiSax: No memory for tiger.sendbuf\n");
  840. return (1);
  841. }
  842. skb_queue_head_init(&bcs->rqueue);
  843. skb_queue_head_init(&bcs->squeue);
  844. }
  845. bcs->tx_skb = NULL;
  846. bcs->hw.tiger.sendcnt = 0;
  847. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  848. bcs->event = 0;
  849. bcs->tx_cnt = 0;
  850. return (0);
  851. }
  852. static int
  853. setstack_tiger(struct PStack *st, struct BCState *bcs)
  854. {
  855. bcs->channel = st->l1.bc;
  856. if (open_tigerstate(st->l1.hardware, bcs))
  857. return (-1);
  858. st->l1.bcs = bcs;
  859. st->l2.l2l1 = tiger_l2l1;
  860. setstack_manager(st);
  861. bcs->st = st;
  862. setstack_l1_B(st);
  863. return (0);
  864. }
  865. void
  866. inittiger(struct IsdnCardState *cs)
  867. {
  868. if (!(cs->bcs[0].hw.tiger.send = kmalloc(NETJET_DMA_TXSIZE * sizeof(unsigned int),
  869. GFP_KERNEL | GFP_DMA))) {
  870. printk(KERN_WARNING
  871. "HiSax: No memory for tiger.send\n");
  872. return;
  873. }
  874. cs->bcs[0].hw.tiger.s_irq = cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE/2 - 1;
  875. cs->bcs[0].hw.tiger.s_end = cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE - 1;
  876. cs->bcs[1].hw.tiger.send = cs->bcs[0].hw.tiger.send;
  877. cs->bcs[1].hw.tiger.s_irq = cs->bcs[0].hw.tiger.s_irq;
  878. cs->bcs[1].hw.tiger.s_end = cs->bcs[0].hw.tiger.s_end;
  879. memset(cs->bcs[0].hw.tiger.send, 0xff, NETJET_DMA_TXSIZE * sizeof(unsigned int));
  880. debugl1(cs, "tiger: send buf %p - %p", cs->bcs[0].hw.tiger.send,
  881. cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE - 1);
  882. outl(virt_to_bus(cs->bcs[0].hw.tiger.send),
  883. cs->hw.njet.base + NETJET_DMA_READ_START);
  884. outl(virt_to_bus(cs->bcs[0].hw.tiger.s_irq),
  885. cs->hw.njet.base + NETJET_DMA_READ_IRQ);
  886. outl(virt_to_bus(cs->bcs[0].hw.tiger.s_end),
  887. cs->hw.njet.base + NETJET_DMA_READ_END);
  888. if (!(cs->bcs[0].hw.tiger.rec = kmalloc(NETJET_DMA_RXSIZE * sizeof(unsigned int),
  889. GFP_KERNEL | GFP_DMA))) {
  890. printk(KERN_WARNING
  891. "HiSax: No memory for tiger.rec\n");
  892. return;
  893. }
  894. debugl1(cs, "tiger: rec buf %p - %p", cs->bcs[0].hw.tiger.rec,
  895. cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE - 1);
  896. cs->bcs[1].hw.tiger.rec = cs->bcs[0].hw.tiger.rec;
  897. memset(cs->bcs[0].hw.tiger.rec, 0xff, NETJET_DMA_RXSIZE * sizeof(unsigned int));
  898. outl(virt_to_bus(cs->bcs[0].hw.tiger.rec),
  899. cs->hw.njet.base + NETJET_DMA_WRITE_START);
  900. outl(virt_to_bus(cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE/2 - 1),
  901. cs->hw.njet.base + NETJET_DMA_WRITE_IRQ);
  902. outl(virt_to_bus(cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE - 1),
  903. cs->hw.njet.base + NETJET_DMA_WRITE_END);
  904. debugl1(cs, "tiger: dmacfg %x/%x pulse=%d",
  905. inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR),
  906. inl(cs->hw.njet.base + NETJET_DMA_READ_ADR),
  907. bytein(cs->hw.njet.base + NETJET_PULSE_CNT));
  908. cs->hw.njet.last_is0 = 0;
  909. cs->bcs[0].BC_SetStack = setstack_tiger;
  910. cs->bcs[1].BC_SetStack = setstack_tiger;
  911. cs->bcs[0].BC_Close = close_tigerstate;
  912. cs->bcs[1].BC_Close = close_tigerstate;
  913. }
  914. static void
  915. releasetiger(struct IsdnCardState *cs)
  916. {
  917. kfree(cs->bcs[0].hw.tiger.send);
  918. cs->bcs[0].hw.tiger.send = NULL;
  919. cs->bcs[1].hw.tiger.send = NULL;
  920. kfree(cs->bcs[0].hw.tiger.rec);
  921. cs->bcs[0].hw.tiger.rec = NULL;
  922. cs->bcs[1].hw.tiger.rec = NULL;
  923. }
  924. void
  925. release_io_netjet(struct IsdnCardState *cs)
  926. {
  927. byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0);
  928. byteout(cs->hw.njet.base + NETJET_IRQMASK1, 0);
  929. releasetiger(cs);
  930. release_region(cs->hw.njet.base, 256);
  931. }