isar.c 51 KB

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  1. /* $Id: isar.c,v 1.22.2.6 2004/02/11 13:21:34 keil Exp $
  2. *
  3. * isar.c ISAR (Siemens PSB 7110) specific routines
  4. *
  5. * Author Karsten Keil (keil@isdn4linux.de)
  6. *
  7. * This file is (c) under GNU General Public License
  8. *
  9. */
  10. #include <linux/init.h>
  11. #include "hisax.h"
  12. #include "isar.h"
  13. #include "isdnl1.h"
  14. #include <linux/interrupt.h>
  15. #define DBG_LOADFIRM 0
  16. #define DUMP_MBOXFRAME 2
  17. #define DLE 0x10
  18. #define ETX 0x03
  19. #define FAXMODCNT 13
  20. static const u_char faxmodulation[] = {3,24,48,72,73,74,96,97,98,121,122,145,146};
  21. static u_int modmask = 0x1fff;
  22. static int frm_extra_delay = 2;
  23. static int para_TOA = 6;
  24. static const u_char *FC1_CMD[] = {"FAE", "FTS", "FRS", "FTM", "FRM", "FTH", "FRH", "CTRL" };
  25. static void isar_setup(struct IsdnCardState *cs);
  26. static void isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para);
  27. static void ll_deliver_faxstat(struct BCState *bcs, u_char status);
  28. static inline int
  29. waitforHIA(struct IsdnCardState *cs, int timeout)
  30. {
  31. while ((cs->BC_Read_Reg(cs, 0, ISAR_HIA) & 1) && timeout) {
  32. udelay(1);
  33. timeout--;
  34. }
  35. if (!timeout)
  36. printk(KERN_WARNING "HiSax: ISAR waitforHIA timeout\n");
  37. return(timeout);
  38. }
  39. static int
  40. sendmsg(struct IsdnCardState *cs, u_char his, u_char creg, u_char len,
  41. u_char *msg)
  42. {
  43. int i;
  44. if (!waitforHIA(cs, 4000))
  45. return(0);
  46. #if DUMP_MBOXFRAME
  47. if (cs->debug & L1_DEB_HSCX)
  48. debugl1(cs, "sendmsg(%02x,%02x,%d)", his, creg, len);
  49. #endif
  50. cs->BC_Write_Reg(cs, 0, ISAR_CTRL_H, creg);
  51. cs->BC_Write_Reg(cs, 0, ISAR_CTRL_L, len);
  52. cs->BC_Write_Reg(cs, 0, ISAR_WADR, 0);
  53. if (msg && len) {
  54. cs->BC_Write_Reg(cs, 1, ISAR_MBOX, msg[0]);
  55. for (i=1; i<len; i++)
  56. cs->BC_Write_Reg(cs, 2, ISAR_MBOX, msg[i]);
  57. #if DUMP_MBOXFRAME>1
  58. if (cs->debug & L1_DEB_HSCX_FIFO) {
  59. char tmp[256], *t;
  60. i = len;
  61. while (i>0) {
  62. t = tmp;
  63. t += sprintf(t, "sendmbox cnt %d", len);
  64. QuickHex(t, &msg[len-i], (i>64) ? 64:i);
  65. debugl1(cs, tmp);
  66. i -= 64;
  67. }
  68. }
  69. #endif
  70. }
  71. cs->BC_Write_Reg(cs, 1, ISAR_HIS, his);
  72. waitforHIA(cs, 10000);
  73. return(1);
  74. }
  75. /* Call only with IRQ disabled !!! */
  76. static inline void
  77. rcv_mbox(struct IsdnCardState *cs, struct isar_reg *ireg, u_char *msg)
  78. {
  79. int i;
  80. cs->BC_Write_Reg(cs, 1, ISAR_RADR, 0);
  81. if (msg && ireg->clsb) {
  82. msg[0] = cs->BC_Read_Reg(cs, 1, ISAR_MBOX);
  83. for (i=1; i < ireg->clsb; i++)
  84. msg[i] = cs->BC_Read_Reg(cs, 2, ISAR_MBOX);
  85. #if DUMP_MBOXFRAME>1
  86. if (cs->debug & L1_DEB_HSCX_FIFO) {
  87. char tmp[256], *t;
  88. i = ireg->clsb;
  89. while (i>0) {
  90. t = tmp;
  91. t += sprintf(t, "rcv_mbox cnt %d", ireg->clsb);
  92. QuickHex(t, &msg[ireg->clsb-i], (i>64) ? 64:i);
  93. debugl1(cs, tmp);
  94. i -= 64;
  95. }
  96. }
  97. #endif
  98. }
  99. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  100. }
  101. /* Call only with IRQ disabled !!! */
  102. static inline void
  103. get_irq_infos(struct IsdnCardState *cs, struct isar_reg *ireg)
  104. {
  105. ireg->iis = cs->BC_Read_Reg(cs, 1, ISAR_IIS);
  106. ireg->cmsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_H);
  107. ireg->clsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_L);
  108. #if DUMP_MBOXFRAME
  109. if (cs->debug & L1_DEB_HSCX)
  110. debugl1(cs, "irq_stat(%02x,%02x,%d)", ireg->iis, ireg->cmsb,
  111. ireg->clsb);
  112. #endif
  113. }
  114. static int
  115. waitrecmsg(struct IsdnCardState *cs, u_char *len,
  116. u_char *msg, int maxdelay)
  117. {
  118. int timeout = 0;
  119. struct isar_reg *ir = cs->bcs[0].hw.isar.reg;
  120. while((!(cs->BC_Read_Reg(cs, 0, ISAR_IRQBIT) & ISAR_IRQSTA)) &&
  121. (timeout++ < maxdelay))
  122. udelay(1);
  123. if (timeout >= maxdelay) {
  124. printk(KERN_WARNING"isar recmsg IRQSTA timeout\n");
  125. return(0);
  126. }
  127. get_irq_infos(cs, ir);
  128. rcv_mbox(cs, ir, msg);
  129. *len = ir->clsb;
  130. return(1);
  131. }
  132. int
  133. ISARVersion(struct IsdnCardState *cs, char *s)
  134. {
  135. int ver;
  136. u_char msg[] = ISAR_MSG_HWVER;
  137. u_char tmp[64];
  138. u_char len;
  139. u_long flags;
  140. int debug;
  141. cs->cardmsg(cs, CARD_RESET, NULL);
  142. spin_lock_irqsave(&cs->lock, flags);
  143. /* disable ISAR IRQ */
  144. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
  145. debug = cs->debug;
  146. cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
  147. if (!sendmsg(cs, ISAR_HIS_VNR, 0, 3, msg)) {
  148. spin_unlock_irqrestore(&cs->lock, flags);
  149. return(-1);
  150. }
  151. if (!waitrecmsg(cs, &len, tmp, 100000)) {
  152. spin_unlock_irqrestore(&cs->lock, flags);
  153. return(-2);
  154. }
  155. cs->debug = debug;
  156. if (cs->bcs[0].hw.isar.reg->iis == ISAR_IIS_VNR) {
  157. if (len == 1) {
  158. ver = tmp[0] & 0xf;
  159. printk(KERN_INFO "%s ISAR version %d\n", s, ver);
  160. } else
  161. ver = -3;
  162. } else
  163. ver = -4;
  164. spin_unlock_irqrestore(&cs->lock, flags);
  165. return(ver);
  166. }
  167. static int
  168. isar_load_firmware(struct IsdnCardState *cs, u_char __user *buf)
  169. {
  170. int ret, size, cnt, debug;
  171. u_char len, nom, noc;
  172. u_short sadr, left, *sp;
  173. u_char __user *p = buf;
  174. u_char *msg, *tmpmsg, *mp, tmp[64];
  175. u_long flags;
  176. struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
  177. struct {u_short sadr;
  178. u_short len;
  179. u_short d_key;
  180. } blk_head;
  181. #define BLK_HEAD_SIZE 6
  182. if (1 != (ret = ISARVersion(cs, "Testing"))) {
  183. printk(KERN_ERR"isar_load_firmware wrong isar version %d\n", ret);
  184. return(1);
  185. }
  186. debug = cs->debug;
  187. #if DBG_LOADFIRM<2
  188. cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
  189. #endif
  190. if ((ret = copy_from_user(&size, p, sizeof(int)))) {
  191. printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
  192. return ret;
  193. }
  194. p += sizeof(int);
  195. printk(KERN_DEBUG"isar_load_firmware size: %d\n", size);
  196. cnt = 0;
  197. /* disable ISAR IRQ */
  198. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
  199. if (!(msg = kmalloc(256, GFP_KERNEL))) {
  200. printk(KERN_ERR"isar_load_firmware no buffer\n");
  201. return (1);
  202. }
  203. if (!(tmpmsg = kmalloc(256, GFP_KERNEL))) {
  204. printk(KERN_ERR"isar_load_firmware no tmp buffer\n");
  205. kfree(msg);
  206. return (1);
  207. }
  208. spin_lock_irqsave(&cs->lock, flags);
  209. /* disable ISAR IRQ */
  210. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
  211. spin_unlock_irqrestore(&cs->lock, flags);
  212. while (cnt < size) {
  213. if ((ret = copy_from_user(&blk_head, p, BLK_HEAD_SIZE))) {
  214. printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
  215. goto reterror;
  216. }
  217. #ifdef __BIG_ENDIAN
  218. sadr = (blk_head.sadr & 0xff)*256 + blk_head.sadr/256;
  219. blk_head.sadr = sadr;
  220. sadr = (blk_head.len & 0xff)*256 + blk_head.len/256;
  221. blk_head.len = sadr;
  222. sadr = (blk_head.d_key & 0xff)*256 + blk_head.d_key/256;
  223. blk_head.d_key = sadr;
  224. #endif /* __BIG_ENDIAN */
  225. cnt += BLK_HEAD_SIZE;
  226. p += BLK_HEAD_SIZE;
  227. printk(KERN_DEBUG"isar firmware block (%#x,%5d,%#x)\n",
  228. blk_head.sadr, blk_head.len, blk_head.d_key & 0xff);
  229. sadr = blk_head.sadr;
  230. left = blk_head.len;
  231. spin_lock_irqsave(&cs->lock, flags);
  232. if (!sendmsg(cs, ISAR_HIS_DKEY, blk_head.d_key & 0xff, 0, NULL)) {
  233. printk(KERN_ERR"isar sendmsg dkey failed\n");
  234. ret = 1;goto reterr_unlock;
  235. }
  236. if (!waitrecmsg(cs, &len, tmp, 100000)) {
  237. printk(KERN_ERR"isar waitrecmsg dkey failed\n");
  238. ret = 1;goto reterr_unlock;
  239. }
  240. if ((ireg->iis != ISAR_IIS_DKEY) || ireg->cmsb || len) {
  241. printk(KERN_ERR"isar wrong dkey response (%x,%x,%x)\n",
  242. ireg->iis, ireg->cmsb, len);
  243. ret = 1;goto reterr_unlock;
  244. }
  245. spin_unlock_irqrestore(&cs->lock, flags);
  246. while (left>0) {
  247. if (left > 126)
  248. noc = 126;
  249. else
  250. noc = left;
  251. nom = 2*noc;
  252. mp = msg;
  253. *mp++ = sadr / 256;
  254. *mp++ = sadr % 256;
  255. left -= noc;
  256. *mp++ = noc;
  257. if ((ret = copy_from_user(tmpmsg, p, nom))) {
  258. printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
  259. goto reterror;
  260. }
  261. p += nom;
  262. cnt += nom;
  263. nom += 3;
  264. sp = (u_short *)tmpmsg;
  265. #if DBG_LOADFIRM
  266. printk(KERN_DEBUG"isar: load %3d words at %04x left %d\n",
  267. noc, sadr, left);
  268. #endif
  269. sadr += noc;
  270. while(noc) {
  271. #ifdef __BIG_ENDIAN
  272. *mp++ = *sp % 256;
  273. *mp++ = *sp / 256;
  274. #else
  275. *mp++ = *sp / 256;
  276. *mp++ = *sp % 256;
  277. #endif /* __BIG_ENDIAN */
  278. sp++;
  279. noc--;
  280. }
  281. spin_lock_irqsave(&cs->lock, flags);
  282. if (!sendmsg(cs, ISAR_HIS_FIRM, 0, nom, msg)) {
  283. printk(KERN_ERR"isar sendmsg prog failed\n");
  284. ret = 1;goto reterr_unlock;
  285. }
  286. if (!waitrecmsg(cs, &len, tmp, 100000)) {
  287. printk(KERN_ERR"isar waitrecmsg prog failed\n");
  288. ret = 1;goto reterr_unlock;
  289. }
  290. if ((ireg->iis != ISAR_IIS_FIRM) || ireg->cmsb || len) {
  291. printk(KERN_ERR"isar wrong prog response (%x,%x,%x)\n",
  292. ireg->iis, ireg->cmsb, len);
  293. ret = 1;goto reterr_unlock;
  294. }
  295. spin_unlock_irqrestore(&cs->lock, flags);
  296. }
  297. printk(KERN_DEBUG"isar firmware block %5d words loaded\n",
  298. blk_head.len);
  299. }
  300. /* 10ms delay */
  301. cnt = 10;
  302. while (cnt--)
  303. udelay(1000);
  304. msg[0] = 0xff;
  305. msg[1] = 0xfe;
  306. ireg->bstat = 0;
  307. spin_lock_irqsave(&cs->lock, flags);
  308. if (!sendmsg(cs, ISAR_HIS_STDSP, 0, 2, msg)) {
  309. printk(KERN_ERR"isar sendmsg start dsp failed\n");
  310. ret = 1;goto reterr_unlock;
  311. }
  312. if (!waitrecmsg(cs, &len, tmp, 100000)) {
  313. printk(KERN_ERR"isar waitrecmsg start dsp failed\n");
  314. ret = 1;goto reterr_unlock;
  315. }
  316. if ((ireg->iis != ISAR_IIS_STDSP) || ireg->cmsb || len) {
  317. printk(KERN_ERR"isar wrong start dsp response (%x,%x,%x)\n",
  318. ireg->iis, ireg->cmsb, len);
  319. ret = 1;goto reterr_unlock;
  320. } else
  321. printk(KERN_DEBUG"isar start dsp success\n");
  322. /* NORMAL mode entered */
  323. /* Enable IRQs of ISAR */
  324. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, ISAR_IRQSTA);
  325. spin_unlock_irqrestore(&cs->lock, flags);
  326. cnt = 1000; /* max 1s */
  327. while ((!ireg->bstat) && cnt) {
  328. udelay(1000);
  329. cnt--;
  330. }
  331. if (!cnt) {
  332. printk(KERN_ERR"isar no general status event received\n");
  333. ret = 1;goto reterror;
  334. } else {
  335. printk(KERN_DEBUG"isar general status event %x\n",
  336. ireg->bstat);
  337. }
  338. /* 10ms delay */
  339. cnt = 10;
  340. while (cnt--)
  341. udelay(1000);
  342. spin_lock_irqsave(&cs->lock, flags);
  343. ireg->iis = 0;
  344. if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) {
  345. printk(KERN_ERR"isar sendmsg self tst failed\n");
  346. ret = 1;goto reterr_unlock;
  347. }
  348. cnt = 10000; /* max 100 ms */
  349. spin_unlock_irqrestore(&cs->lock, flags);
  350. while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
  351. udelay(10);
  352. cnt--;
  353. }
  354. udelay(1000);
  355. if (!cnt) {
  356. printk(KERN_ERR"isar no self tst response\n");
  357. ret = 1;goto reterror;
  358. }
  359. if ((ireg->cmsb == ISAR_CTRL_STST) && (ireg->clsb == 1)
  360. && (ireg->par[0] == 0)) {
  361. printk(KERN_DEBUG"isar selftest OK\n");
  362. } else {
  363. printk(KERN_DEBUG"isar selftest not OK %x/%x/%x\n",
  364. ireg->cmsb, ireg->clsb, ireg->par[0]);
  365. ret = 1;goto reterror;
  366. }
  367. spin_lock_irqsave(&cs->lock, flags);
  368. ireg->iis = 0;
  369. if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) {
  370. printk(KERN_ERR"isar RQST SVN failed\n");
  371. ret = 1;goto reterr_unlock;
  372. }
  373. spin_unlock_irqrestore(&cs->lock, flags);
  374. cnt = 30000; /* max 300 ms */
  375. while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
  376. udelay(10);
  377. cnt--;
  378. }
  379. udelay(1000);
  380. if (!cnt) {
  381. printk(KERN_ERR"isar no SVN response\n");
  382. ret = 1;goto reterror;
  383. } else {
  384. if ((ireg->cmsb == ISAR_CTRL_SWVER) && (ireg->clsb == 1))
  385. printk(KERN_DEBUG"isar software version %#x\n",
  386. ireg->par[0]);
  387. else {
  388. printk(KERN_ERR"isar wrong swver response (%x,%x) cnt(%d)\n",
  389. ireg->cmsb, ireg->clsb, cnt);
  390. ret = 1;goto reterror;
  391. }
  392. }
  393. spin_lock_irqsave(&cs->lock, flags);
  394. cs->debug = debug;
  395. isar_setup(cs);
  396. ret = 0;
  397. reterr_unlock:
  398. spin_unlock_irqrestore(&cs->lock, flags);
  399. reterror:
  400. cs->debug = debug;
  401. if (ret)
  402. /* disable ISAR IRQ */
  403. cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
  404. kfree(msg);
  405. kfree(tmpmsg);
  406. return(ret);
  407. }
  408. #define B_LL_NOCARRIER 8
  409. #define B_LL_CONNECT 9
  410. #define B_LL_OK 10
  411. static void
  412. isar_bh(struct work_struct *work)
  413. {
  414. struct BCState *bcs = container_of(work, struct BCState, tqueue);
  415. BChannel_bh(work);
  416. if (test_and_clear_bit(B_LL_NOCARRIER, &bcs->event))
  417. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_NOCARR);
  418. if (test_and_clear_bit(B_LL_CONNECT, &bcs->event))
  419. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  420. if (test_and_clear_bit(B_LL_OK, &bcs->event))
  421. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_OK);
  422. }
  423. static void
  424. send_DLE_ETX(struct BCState *bcs)
  425. {
  426. u_char dleetx[2] = {DLE,ETX};
  427. struct sk_buff *skb;
  428. if ((skb = dev_alloc_skb(2))) {
  429. memcpy(skb_put(skb, 2), dleetx, 2);
  430. skb_queue_tail(&bcs->rqueue, skb);
  431. schedule_event(bcs, B_RCVBUFREADY);
  432. } else {
  433. printk(KERN_WARNING "HiSax: skb out of memory\n");
  434. }
  435. }
  436. static inline int
  437. dle_count(unsigned char *buf, int len)
  438. {
  439. int count = 0;
  440. while (len--)
  441. if (*buf++ == DLE)
  442. count++;
  443. return count;
  444. }
  445. static inline void
  446. insert_dle(unsigned char *dest, unsigned char *src, int count) {
  447. /* <DLE> in input stream have to be flagged as <DLE><DLE> */
  448. while (count--) {
  449. *dest++ = *src;
  450. if (*src++ == DLE)
  451. *dest++ = DLE;
  452. }
  453. }
  454. static void
  455. isar_rcv_frame(struct IsdnCardState *cs, struct BCState *bcs)
  456. {
  457. u_char *ptr;
  458. struct sk_buff *skb;
  459. struct isar_reg *ireg = bcs->hw.isar.reg;
  460. if (!ireg->clsb) {
  461. debugl1(cs, "isar zero len frame");
  462. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  463. return;
  464. }
  465. switch (bcs->mode) {
  466. case L1_MODE_NULL:
  467. debugl1(cs, "isar mode 0 spurious IIS_RDATA %x/%x/%x",
  468. ireg->iis, ireg->cmsb, ireg->clsb);
  469. printk(KERN_WARNING"isar mode 0 spurious IIS_RDATA %x/%x/%x\n",
  470. ireg->iis, ireg->cmsb, ireg->clsb);
  471. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  472. break;
  473. case L1_MODE_TRANS:
  474. case L1_MODE_V32:
  475. if ((skb = dev_alloc_skb(ireg->clsb))) {
  476. rcv_mbox(cs, ireg, (u_char *)skb_put(skb, ireg->clsb));
  477. skb_queue_tail(&bcs->rqueue, skb);
  478. schedule_event(bcs, B_RCVBUFREADY);
  479. } else {
  480. printk(KERN_WARNING "HiSax: skb out of memory\n");
  481. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  482. }
  483. break;
  484. case L1_MODE_HDLC:
  485. if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
  486. if (cs->debug & L1_DEB_WARN)
  487. debugl1(cs, "isar_rcv_frame: incoming packet too large");
  488. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  489. bcs->hw.isar.rcvidx = 0;
  490. } else if (ireg->cmsb & HDLC_ERROR) {
  491. if (cs->debug & L1_DEB_WARN)
  492. debugl1(cs, "isar frame error %x len %d",
  493. ireg->cmsb, ireg->clsb);
  494. #ifdef ERROR_STATISTIC
  495. if (ireg->cmsb & HDLC_ERR_RER)
  496. bcs->err_inv++;
  497. if (ireg->cmsb & HDLC_ERR_CER)
  498. bcs->err_crc++;
  499. #endif
  500. bcs->hw.isar.rcvidx = 0;
  501. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  502. } else {
  503. if (ireg->cmsb & HDLC_FSD)
  504. bcs->hw.isar.rcvidx = 0;
  505. ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
  506. bcs->hw.isar.rcvidx += ireg->clsb;
  507. rcv_mbox(cs, ireg, ptr);
  508. if (ireg->cmsb & HDLC_FED) {
  509. if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
  510. if (cs->debug & L1_DEB_WARN)
  511. debugl1(cs, "isar frame to short %d",
  512. bcs->hw.isar.rcvidx);
  513. } else if (!(skb = dev_alloc_skb(bcs->hw.isar.rcvidx-2))) {
  514. printk(KERN_WARNING "ISAR: receive out of memory\n");
  515. } else {
  516. memcpy(skb_put(skb, bcs->hw.isar.rcvidx-2),
  517. bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx-2);
  518. skb_queue_tail(&bcs->rqueue, skb);
  519. schedule_event(bcs, B_RCVBUFREADY);
  520. }
  521. bcs->hw.isar.rcvidx = 0;
  522. }
  523. }
  524. break;
  525. case L1_MODE_FAX:
  526. if (bcs->hw.isar.state != STFAX_ACTIV) {
  527. if (cs->debug & L1_DEB_WARN)
  528. debugl1(cs, "isar_rcv_frame: not ACTIV");
  529. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  530. bcs->hw.isar.rcvidx = 0;
  531. break;
  532. }
  533. if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
  534. rcv_mbox(cs, ireg, bcs->hw.isar.rcvbuf);
  535. bcs->hw.isar.rcvidx = ireg->clsb +
  536. dle_count(bcs->hw.isar.rcvbuf, ireg->clsb);
  537. if (cs->debug & L1_DEB_HSCX)
  538. debugl1(cs, "isar_rcv_frame: raw(%d) dle(%d)",
  539. ireg->clsb, bcs->hw.isar.rcvidx);
  540. if ((skb = dev_alloc_skb(bcs->hw.isar.rcvidx))) {
  541. insert_dle((u_char *)skb_put(skb, bcs->hw.isar.rcvidx),
  542. bcs->hw.isar.rcvbuf, ireg->clsb);
  543. skb_queue_tail(&bcs->rqueue, skb);
  544. schedule_event(bcs, B_RCVBUFREADY);
  545. if (ireg->cmsb & SART_NMD) { /* ABORT */
  546. if (cs->debug & L1_DEB_WARN)
  547. debugl1(cs, "isar_rcv_frame: no more data");
  548. bcs->hw.isar.rcvidx = 0;
  549. send_DLE_ETX(bcs);
  550. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
  551. ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC,
  552. 0, NULL);
  553. bcs->hw.isar.state = STFAX_ESCAPE;
  554. schedule_event(bcs, B_LL_NOCARRIER);
  555. }
  556. } else {
  557. printk(KERN_WARNING "HiSax: skb out of memory\n");
  558. }
  559. break;
  560. }
  561. if (bcs->hw.isar.cmd != PCTRL_CMD_FRH) {
  562. if (cs->debug & L1_DEB_WARN)
  563. debugl1(cs, "isar_rcv_frame: unknown fax mode %x",
  564. bcs->hw.isar.cmd);
  565. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  566. bcs->hw.isar.rcvidx = 0;
  567. break;
  568. }
  569. /* PCTRL_CMD_FRH */
  570. if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
  571. if (cs->debug & L1_DEB_WARN)
  572. debugl1(cs, "isar_rcv_frame: incoming packet too large");
  573. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  574. bcs->hw.isar.rcvidx = 0;
  575. } else if (ireg->cmsb & HDLC_ERROR) {
  576. if (cs->debug & L1_DEB_WARN)
  577. debugl1(cs, "isar frame error %x len %d",
  578. ireg->cmsb, ireg->clsb);
  579. bcs->hw.isar.rcvidx = 0;
  580. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  581. } else {
  582. if (ireg->cmsb & HDLC_FSD) {
  583. bcs->hw.isar.rcvidx = 0;
  584. }
  585. ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
  586. bcs->hw.isar.rcvidx += ireg->clsb;
  587. rcv_mbox(cs, ireg, ptr);
  588. if (ireg->cmsb & HDLC_FED) {
  589. int len = bcs->hw.isar.rcvidx +
  590. dle_count(bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx);
  591. if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
  592. if (cs->debug & L1_DEB_WARN)
  593. debugl1(cs, "isar frame to short %d",
  594. bcs->hw.isar.rcvidx);
  595. printk(KERN_WARNING "ISAR: frame to short %d\n",
  596. bcs->hw.isar.rcvidx);
  597. } else if (!(skb = dev_alloc_skb(len))) {
  598. printk(KERN_WARNING "ISAR: receive out of memory\n");
  599. } else {
  600. insert_dle((u_char *)skb_put(skb, len),
  601. bcs->hw.isar.rcvbuf,
  602. bcs->hw.isar.rcvidx);
  603. skb_queue_tail(&bcs->rqueue, skb);
  604. schedule_event(bcs, B_RCVBUFREADY);
  605. send_DLE_ETX(bcs);
  606. schedule_event(bcs, B_LL_OK);
  607. test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  608. }
  609. bcs->hw.isar.rcvidx = 0;
  610. }
  611. }
  612. if (ireg->cmsb & SART_NMD) { /* ABORT */
  613. if (cs->debug & L1_DEB_WARN)
  614. debugl1(cs, "isar_rcv_frame: no more data");
  615. bcs->hw.isar.rcvidx = 0;
  616. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
  617. ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
  618. bcs->hw.isar.state = STFAX_ESCAPE;
  619. if (test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag)) {
  620. send_DLE_ETX(bcs);
  621. schedule_event(bcs, B_LL_NOCARRIER);
  622. }
  623. }
  624. break;
  625. default:
  626. printk(KERN_ERR"isar_rcv_frame mode (%x)error\n", bcs->mode);
  627. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  628. break;
  629. }
  630. }
  631. void
  632. isar_fill_fifo(struct BCState *bcs)
  633. {
  634. struct IsdnCardState *cs = bcs->cs;
  635. int count;
  636. u_char msb;
  637. u_char *ptr;
  638. if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
  639. debugl1(cs, "isar_fill_fifo");
  640. if (!bcs->tx_skb)
  641. return;
  642. if (bcs->tx_skb->len <= 0)
  643. return;
  644. if (!(bcs->hw.isar.reg->bstat &
  645. (bcs->hw.isar.dpath == 1 ? BSTAT_RDM1 : BSTAT_RDM2)))
  646. return;
  647. if (bcs->tx_skb->len > bcs->hw.isar.mml) {
  648. msb = 0;
  649. count = bcs->hw.isar.mml;
  650. } else {
  651. count = bcs->tx_skb->len;
  652. msb = HDLC_FED;
  653. }
  654. ptr = bcs->tx_skb->data;
  655. if (!bcs->hw.isar.txcnt) {
  656. msb |= HDLC_FST;
  657. if ((bcs->mode == L1_MODE_FAX) &&
  658. (bcs->hw.isar.cmd == PCTRL_CMD_FTH)) {
  659. if (bcs->tx_skb->len > 1) {
  660. if ((ptr[0]== 0xff) && (ptr[1] == 0x13))
  661. /* last frame */
  662. test_and_set_bit(BC_FLG_LASTDATA,
  663. &bcs->Flag);
  664. }
  665. }
  666. }
  667. skb_pull(bcs->tx_skb, count);
  668. bcs->tx_cnt -= count;
  669. bcs->hw.isar.txcnt += count;
  670. switch (bcs->mode) {
  671. case L1_MODE_NULL:
  672. printk(KERN_ERR"isar_fill_fifo wrong mode 0\n");
  673. break;
  674. case L1_MODE_TRANS:
  675. case L1_MODE_V32:
  676. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
  677. 0, count, ptr);
  678. break;
  679. case L1_MODE_HDLC:
  680. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
  681. msb, count, ptr);
  682. break;
  683. case L1_MODE_FAX:
  684. if (bcs->hw.isar.state != STFAX_ACTIV) {
  685. if (cs->debug & L1_DEB_WARN)
  686. debugl1(cs, "isar_fill_fifo: not ACTIV");
  687. } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
  688. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
  689. msb, count, ptr);
  690. } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
  691. sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
  692. 0, count, ptr);
  693. } else {
  694. if (cs->debug & L1_DEB_WARN)
  695. debugl1(cs, "isar_fill_fifo: not FTH/FTM");
  696. }
  697. break;
  698. default:
  699. if (cs->debug)
  700. debugl1(cs, "isar_fill_fifo mode(%x) error", bcs->mode);
  701. printk(KERN_ERR"isar_fill_fifo mode(%x) error\n", bcs->mode);
  702. break;
  703. }
  704. }
  705. static inline
  706. struct BCState *sel_bcs_isar(struct IsdnCardState *cs, u_char dpath)
  707. {
  708. if ((!dpath) || (dpath == 3))
  709. return(NULL);
  710. if (cs->bcs[0].hw.isar.dpath == dpath)
  711. return(&cs->bcs[0]);
  712. if (cs->bcs[1].hw.isar.dpath == dpath)
  713. return(&cs->bcs[1]);
  714. return(NULL);
  715. }
  716. static void
  717. send_frames(struct BCState *bcs)
  718. {
  719. if (bcs->tx_skb) {
  720. if (bcs->tx_skb->len) {
  721. isar_fill_fifo(bcs);
  722. return;
  723. } else {
  724. if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
  725. (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
  726. u_long flags;
  727. spin_lock_irqsave(&bcs->aclock, flags);
  728. bcs->ackcnt += bcs->hw.isar.txcnt;
  729. spin_unlock_irqrestore(&bcs->aclock, flags);
  730. schedule_event(bcs, B_ACKPENDING);
  731. }
  732. if (bcs->mode == L1_MODE_FAX) {
  733. if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
  734. if (test_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
  735. test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
  736. }
  737. } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
  738. if (test_bit(BC_FLG_DLEETX, &bcs->Flag)) {
  739. test_and_set_bit(BC_FLG_LASTDATA, &bcs->Flag);
  740. test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
  741. }
  742. }
  743. }
  744. dev_kfree_skb_any(bcs->tx_skb);
  745. bcs->hw.isar.txcnt = 0;
  746. bcs->tx_skb = NULL;
  747. }
  748. }
  749. if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
  750. bcs->hw.isar.txcnt = 0;
  751. test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
  752. isar_fill_fifo(bcs);
  753. } else {
  754. if (test_and_clear_bit(BC_FLG_DLEETX, &bcs->Flag)) {
  755. if (test_and_clear_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
  756. if (test_and_clear_bit(BC_FLG_NMD_DATA, &bcs->Flag)) {
  757. u_char dummy = 0;
  758. sendmsg(bcs->cs, SET_DPS(bcs->hw.isar.dpath) |
  759. ISAR_HIS_SDATA, 0x01, 1, &dummy);
  760. }
  761. test_and_set_bit(BC_FLG_LL_OK, &bcs->Flag);
  762. } else {
  763. schedule_event(bcs, B_LL_CONNECT);
  764. }
  765. }
  766. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  767. schedule_event(bcs, B_XMTBUFREADY);
  768. }
  769. }
  770. static inline void
  771. check_send(struct IsdnCardState *cs, u_char rdm)
  772. {
  773. struct BCState *bcs;
  774. if (rdm & BSTAT_RDM1) {
  775. if ((bcs = sel_bcs_isar(cs, 1))) {
  776. if (bcs->mode) {
  777. send_frames(bcs);
  778. }
  779. }
  780. }
  781. if (rdm & BSTAT_RDM2) {
  782. if ((bcs = sel_bcs_isar(cs, 2))) {
  783. if (bcs->mode) {
  784. send_frames(bcs);
  785. }
  786. }
  787. }
  788. }
  789. static const char *dmril[] = {"NO SPEED", "1200/75", "NODEF2", "75/1200",
  790. "NODEF4", "300", "600", "1200", "2400",
  791. "4800", "7200", "9600nt", "9600t", "12000",
  792. "14400", "WRONG"};
  793. static const char *dmrim[] = {"NO MOD", "NO DEF", "V32/V32b", "V22", "V21",
  794. "Bell103", "V23", "Bell202", "V17", "V29",
  795. "V27ter"};
  796. static void
  797. isar_pump_status_rsp(struct BCState *bcs, struct isar_reg *ireg) {
  798. struct IsdnCardState *cs = bcs->cs;
  799. u_char ril = ireg->par[0];
  800. u_char rim;
  801. if (!test_and_clear_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags))
  802. return;
  803. if (ril > 14) {
  804. if (cs->debug & L1_DEB_WARN)
  805. debugl1(cs, "wrong pstrsp ril=%d",ril);
  806. ril = 15;
  807. }
  808. switch(ireg->par[1]) {
  809. case 0:
  810. rim = 0;
  811. break;
  812. case 0x20:
  813. rim = 2;
  814. break;
  815. case 0x40:
  816. rim = 3;
  817. break;
  818. case 0x41:
  819. rim = 4;
  820. break;
  821. case 0x51:
  822. rim = 5;
  823. break;
  824. case 0x61:
  825. rim = 6;
  826. break;
  827. case 0x71:
  828. rim = 7;
  829. break;
  830. case 0x82:
  831. rim = 8;
  832. break;
  833. case 0x92:
  834. rim = 9;
  835. break;
  836. case 0xa2:
  837. rim = 10;
  838. break;
  839. default:
  840. rim = 1;
  841. break;
  842. }
  843. sprintf(bcs->hw.isar.conmsg,"%s %s", dmril[ril], dmrim[rim]);
  844. bcs->conmsg = bcs->hw.isar.conmsg;
  845. if (cs->debug & L1_DEB_HSCX)
  846. debugl1(cs, "pump strsp %s", bcs->conmsg);
  847. }
  848. static void
  849. isar_pump_statev_modem(struct BCState *bcs, u_char devt) {
  850. struct IsdnCardState *cs = bcs->cs;
  851. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  852. switch(devt) {
  853. case PSEV_10MS_TIMER:
  854. if (cs->debug & L1_DEB_HSCX)
  855. debugl1(cs, "pump stev TIMER");
  856. break;
  857. case PSEV_CON_ON:
  858. if (cs->debug & L1_DEB_HSCX)
  859. debugl1(cs, "pump stev CONNECT");
  860. l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
  861. break;
  862. case PSEV_CON_OFF:
  863. if (cs->debug & L1_DEB_HSCX)
  864. debugl1(cs, "pump stev NO CONNECT");
  865. sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  866. l1_msg_b(bcs->st, PH_DEACTIVATE | REQUEST, NULL);
  867. break;
  868. case PSEV_V24_OFF:
  869. if (cs->debug & L1_DEB_HSCX)
  870. debugl1(cs, "pump stev V24 OFF");
  871. break;
  872. case PSEV_CTS_ON:
  873. if (cs->debug & L1_DEB_HSCX)
  874. debugl1(cs, "pump stev CTS ON");
  875. break;
  876. case PSEV_CTS_OFF:
  877. if (cs->debug & L1_DEB_HSCX)
  878. debugl1(cs, "pump stev CTS OFF");
  879. break;
  880. case PSEV_DCD_ON:
  881. if (cs->debug & L1_DEB_HSCX)
  882. debugl1(cs, "pump stev CARRIER ON");
  883. test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
  884. sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  885. break;
  886. case PSEV_DCD_OFF:
  887. if (cs->debug & L1_DEB_HSCX)
  888. debugl1(cs, "pump stev CARRIER OFF");
  889. break;
  890. case PSEV_DSR_ON:
  891. if (cs->debug & L1_DEB_HSCX)
  892. debugl1(cs, "pump stev DSR ON");
  893. break;
  894. case PSEV_DSR_OFF:
  895. if (cs->debug & L1_DEB_HSCX)
  896. debugl1(cs, "pump stev DSR_OFF");
  897. break;
  898. case PSEV_REM_RET:
  899. if (cs->debug & L1_DEB_HSCX)
  900. debugl1(cs, "pump stev REMOTE RETRAIN");
  901. break;
  902. case PSEV_REM_REN:
  903. if (cs->debug & L1_DEB_HSCX)
  904. debugl1(cs, "pump stev REMOTE RENEGOTIATE");
  905. break;
  906. case PSEV_GSTN_CLR:
  907. if (cs->debug & L1_DEB_HSCX)
  908. debugl1(cs, "pump stev GSTN CLEAR", devt);
  909. break;
  910. default:
  911. if (cs->debug & L1_DEB_HSCX)
  912. debugl1(cs, "unknown pump stev %x", devt);
  913. break;
  914. }
  915. }
  916. static void
  917. ll_deliver_faxstat(struct BCState *bcs, u_char status)
  918. {
  919. isdn_ctrl ic;
  920. struct Channel *chanp = (struct Channel *) bcs->st->lli.userdata;
  921. if (bcs->cs->debug & L1_DEB_HSCX)
  922. debugl1(bcs->cs, "HL->LL FAXIND %x", status);
  923. ic.driver = bcs->cs->myid;
  924. ic.command = ISDN_STAT_FAXIND;
  925. ic.arg = chanp->chan;
  926. ic.parm.aux.cmd = status;
  927. bcs->cs->iif.statcallb(&ic);
  928. }
  929. static void
  930. isar_pump_statev_fax(struct BCState *bcs, u_char devt) {
  931. struct IsdnCardState *cs = bcs->cs;
  932. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  933. u_char p1;
  934. switch(devt) {
  935. case PSEV_10MS_TIMER:
  936. if (cs->debug & L1_DEB_HSCX)
  937. debugl1(cs, "pump stev TIMER");
  938. break;
  939. case PSEV_RSP_READY:
  940. if (cs->debug & L1_DEB_HSCX)
  941. debugl1(cs, "pump stev RSP_READY");
  942. bcs->hw.isar.state = STFAX_READY;
  943. l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
  944. if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
  945. isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FRH, 3);
  946. } else {
  947. isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FTH, 3);
  948. }
  949. break;
  950. case PSEV_LINE_TX_H:
  951. if (bcs->hw.isar.state == STFAX_LINE) {
  952. if (cs->debug & L1_DEB_HSCX)
  953. debugl1(cs, "pump stev LINE_TX_H");
  954. bcs->hw.isar.state = STFAX_CONT;
  955. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
  956. } else {
  957. if (cs->debug & L1_DEB_WARN)
  958. debugl1(cs, "pump stev LINE_TX_H wrong st %x",
  959. bcs->hw.isar.state);
  960. }
  961. break;
  962. case PSEV_LINE_RX_H:
  963. if (bcs->hw.isar.state == STFAX_LINE) {
  964. if (cs->debug & L1_DEB_HSCX)
  965. debugl1(cs, "pump stev LINE_RX_H");
  966. bcs->hw.isar.state = STFAX_CONT;
  967. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
  968. } else {
  969. if (cs->debug & L1_DEB_WARN)
  970. debugl1(cs, "pump stev LINE_RX_H wrong st %x",
  971. bcs->hw.isar.state);
  972. }
  973. break;
  974. case PSEV_LINE_TX_B:
  975. if (bcs->hw.isar.state == STFAX_LINE) {
  976. if (cs->debug & L1_DEB_HSCX)
  977. debugl1(cs, "pump stev LINE_TX_B");
  978. bcs->hw.isar.state = STFAX_CONT;
  979. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
  980. } else {
  981. if (cs->debug & L1_DEB_WARN)
  982. debugl1(cs, "pump stev LINE_TX_B wrong st %x",
  983. bcs->hw.isar.state);
  984. }
  985. break;
  986. case PSEV_LINE_RX_B:
  987. if (bcs->hw.isar.state == STFAX_LINE) {
  988. if (cs->debug & L1_DEB_HSCX)
  989. debugl1(cs, "pump stev LINE_RX_B");
  990. bcs->hw.isar.state = STFAX_CONT;
  991. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
  992. } else {
  993. if (cs->debug & L1_DEB_WARN)
  994. debugl1(cs, "pump stev LINE_RX_B wrong st %x",
  995. bcs->hw.isar.state);
  996. }
  997. break;
  998. case PSEV_RSP_CONN:
  999. if (bcs->hw.isar.state == STFAX_CONT) {
  1000. if (cs->debug & L1_DEB_HSCX)
  1001. debugl1(cs, "pump stev RSP_CONN");
  1002. bcs->hw.isar.state = STFAX_ACTIV;
  1003. test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
  1004. sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  1005. if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
  1006. /* 1s Flags before data */
  1007. if (test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag))
  1008. del_timer(&bcs->hw.isar.ftimer);
  1009. /* 1000 ms */
  1010. bcs->hw.isar.ftimer.expires =
  1011. jiffies + ((1000 * HZ)/1000);
  1012. test_and_set_bit(BC_FLG_LL_CONN,
  1013. &bcs->Flag);
  1014. add_timer(&bcs->hw.isar.ftimer);
  1015. } else {
  1016. schedule_event(bcs, B_LL_CONNECT);
  1017. }
  1018. } else {
  1019. if (cs->debug & L1_DEB_WARN)
  1020. debugl1(cs, "pump stev RSP_CONN wrong st %x",
  1021. bcs->hw.isar.state);
  1022. }
  1023. break;
  1024. case PSEV_FLAGS_DET:
  1025. if (cs->debug & L1_DEB_HSCX)
  1026. debugl1(cs, "pump stev FLAGS_DET");
  1027. break;
  1028. case PSEV_RSP_DISC:
  1029. if (cs->debug & L1_DEB_HSCX)
  1030. debugl1(cs, "pump stev RSP_DISC");
  1031. if (bcs->hw.isar.state == STFAX_ESCAPE) {
  1032. p1 = 5;
  1033. switch(bcs->hw.isar.newcmd) {
  1034. case 0:
  1035. bcs->hw.isar.state = STFAX_READY;
  1036. break;
  1037. case PCTRL_CMD_FTM:
  1038. p1 = 2;
  1039. case PCTRL_CMD_FTH:
  1040. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
  1041. PCTRL_CMD_SILON, 1, &p1);
  1042. bcs->hw.isar.state = STFAX_SILDET;
  1043. break;
  1044. case PCTRL_CMD_FRM:
  1045. if (frm_extra_delay)
  1046. mdelay(frm_extra_delay);
  1047. case PCTRL_CMD_FRH:
  1048. p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
  1049. bcs->hw.isar.newmod = 0;
  1050. bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
  1051. bcs->hw.isar.newcmd = 0;
  1052. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
  1053. bcs->hw.isar.cmd, 1, &p1);
  1054. bcs->hw.isar.state = STFAX_LINE;
  1055. bcs->hw.isar.try_mod = 3;
  1056. break;
  1057. default:
  1058. if (cs->debug & L1_DEB_HSCX)
  1059. debugl1(cs, "RSP_DISC unknown newcmd %x", bcs->hw.isar.newcmd);
  1060. break;
  1061. }
  1062. } else if (bcs->hw.isar.state == STFAX_ACTIV) {
  1063. if (test_and_clear_bit(BC_FLG_LL_OK, &bcs->Flag)) {
  1064. schedule_event(bcs, B_LL_OK);
  1065. } else if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
  1066. send_DLE_ETX(bcs);
  1067. schedule_event(bcs, B_LL_NOCARRIER);
  1068. } else {
  1069. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
  1070. }
  1071. bcs->hw.isar.state = STFAX_READY;
  1072. } else {
  1073. bcs->hw.isar.state = STFAX_READY;
  1074. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
  1075. }
  1076. break;
  1077. case PSEV_RSP_SILDET:
  1078. if (cs->debug & L1_DEB_HSCX)
  1079. debugl1(cs, "pump stev RSP_SILDET");
  1080. if (bcs->hw.isar.state == STFAX_SILDET) {
  1081. p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
  1082. bcs->hw.isar.newmod = 0;
  1083. bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
  1084. bcs->hw.isar.newcmd = 0;
  1085. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
  1086. bcs->hw.isar.cmd, 1, &p1);
  1087. bcs->hw.isar.state = STFAX_LINE;
  1088. bcs->hw.isar.try_mod = 3;
  1089. }
  1090. break;
  1091. case PSEV_RSP_SILOFF:
  1092. if (cs->debug & L1_DEB_HSCX)
  1093. debugl1(cs, "pump stev RSP_SILOFF");
  1094. break;
  1095. case PSEV_RSP_FCERR:
  1096. if (bcs->hw.isar.state == STFAX_LINE) {
  1097. if (cs->debug & L1_DEB_HSCX)
  1098. debugl1(cs, "pump stev RSP_FCERR try %d",
  1099. bcs->hw.isar.try_mod);
  1100. if (bcs->hw.isar.try_mod--) {
  1101. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
  1102. bcs->hw.isar.cmd, 1,
  1103. &bcs->hw.isar.mod);
  1104. break;
  1105. }
  1106. }
  1107. if (cs->debug & L1_DEB_HSCX)
  1108. debugl1(cs, "pump stev RSP_FCERR");
  1109. bcs->hw.isar.state = STFAX_ESCAPE;
  1110. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
  1111. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
  1112. break;
  1113. default:
  1114. break;
  1115. }
  1116. }
  1117. static char debbuf[128];
  1118. void
  1119. isar_int_main(struct IsdnCardState *cs)
  1120. {
  1121. struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
  1122. struct BCState *bcs;
  1123. get_irq_infos(cs, ireg);
  1124. switch (ireg->iis & ISAR_IIS_MSCMSD) {
  1125. case ISAR_IIS_RDATA:
  1126. if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
  1127. isar_rcv_frame(cs, bcs);
  1128. } else {
  1129. debugl1(cs, "isar spurious IIS_RDATA %x/%x/%x",
  1130. ireg->iis, ireg->cmsb, ireg->clsb);
  1131. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1132. }
  1133. break;
  1134. case ISAR_IIS_GSTEV:
  1135. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1136. ireg->bstat |= ireg->cmsb;
  1137. check_send(cs, ireg->cmsb);
  1138. break;
  1139. case ISAR_IIS_BSTEV:
  1140. #ifdef ERROR_STATISTIC
  1141. if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
  1142. if (ireg->cmsb == BSTEV_TBO)
  1143. bcs->err_tx++;
  1144. if (ireg->cmsb == BSTEV_RBO)
  1145. bcs->err_rdo++;
  1146. }
  1147. #endif
  1148. if (cs->debug & L1_DEB_WARN)
  1149. debugl1(cs, "Buffer STEV dpath%d msb(%x)",
  1150. ireg->iis>>6, ireg->cmsb);
  1151. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1152. break;
  1153. case ISAR_IIS_PSTEV:
  1154. if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
  1155. rcv_mbox(cs, ireg, (u_char *)ireg->par);
  1156. if (bcs->mode == L1_MODE_V32) {
  1157. isar_pump_statev_modem(bcs, ireg->cmsb);
  1158. } else if (bcs->mode == L1_MODE_FAX) {
  1159. isar_pump_statev_fax(bcs, ireg->cmsb);
  1160. } else if (ireg->cmsb == PSEV_10MS_TIMER) {
  1161. if (cs->debug & L1_DEB_HSCX)
  1162. debugl1(cs, "pump stev TIMER");
  1163. } else {
  1164. if (cs->debug & L1_DEB_WARN)
  1165. debugl1(cs, "isar IIS_PSTEV pmode %d stat %x",
  1166. bcs->mode, ireg->cmsb);
  1167. }
  1168. } else {
  1169. debugl1(cs, "isar spurious IIS_PSTEV %x/%x/%x",
  1170. ireg->iis, ireg->cmsb, ireg->clsb);
  1171. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1172. }
  1173. break;
  1174. case ISAR_IIS_PSTRSP:
  1175. if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
  1176. rcv_mbox(cs, ireg, (u_char *)ireg->par);
  1177. isar_pump_status_rsp(bcs, ireg);
  1178. } else {
  1179. debugl1(cs, "isar spurious IIS_PSTRSP %x/%x/%x",
  1180. ireg->iis, ireg->cmsb, ireg->clsb);
  1181. cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
  1182. }
  1183. break;
  1184. case ISAR_IIS_DIAG:
  1185. case ISAR_IIS_BSTRSP:
  1186. case ISAR_IIS_IOM2RSP:
  1187. rcv_mbox(cs, ireg, (u_char *)ireg->par);
  1188. if ((cs->debug & (L1_DEB_HSCX | L1_DEB_HSCX_FIFO))
  1189. == L1_DEB_HSCX) {
  1190. u_char *tp=debbuf;
  1191. tp += sprintf(debbuf, "msg iis(%x) msb(%x)",
  1192. ireg->iis, ireg->cmsb);
  1193. QuickHex(tp, (u_char *)ireg->par, ireg->clsb);
  1194. debugl1(cs, debbuf);
  1195. }
  1196. break;
  1197. case ISAR_IIS_INVMSG:
  1198. rcv_mbox(cs, ireg, debbuf);
  1199. if (cs->debug & L1_DEB_WARN)
  1200. debugl1(cs, "invalid msg his:%x",
  1201. ireg->cmsb);
  1202. break;
  1203. default:
  1204. rcv_mbox(cs, ireg, debbuf);
  1205. if (cs->debug & L1_DEB_WARN)
  1206. debugl1(cs, "unhandled msg iis(%x) ctrl(%x/%x)",
  1207. ireg->iis, ireg->cmsb, ireg->clsb);
  1208. break;
  1209. }
  1210. }
  1211. static void
  1212. ftimer_handler(struct BCState *bcs) {
  1213. if (bcs->cs->debug)
  1214. debugl1(bcs->cs, "ftimer flags %04x",
  1215. bcs->Flag);
  1216. test_and_clear_bit(BC_FLG_FTI_RUN, &bcs->Flag);
  1217. if (test_and_clear_bit(BC_FLG_LL_CONN, &bcs->Flag)) {
  1218. schedule_event(bcs, B_LL_CONNECT);
  1219. }
  1220. if (test_and_clear_bit(BC_FLG_FTI_FTS, &bcs->Flag)) {
  1221. schedule_event(bcs, B_LL_OK);
  1222. }
  1223. }
  1224. static void
  1225. setup_pump(struct BCState *bcs) {
  1226. struct IsdnCardState *cs = bcs->cs;
  1227. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  1228. u_char ctrl, param[6];
  1229. switch (bcs->mode) {
  1230. case L1_MODE_NULL:
  1231. case L1_MODE_TRANS:
  1232. case L1_MODE_HDLC:
  1233. sendmsg(cs, dps | ISAR_HIS_PUMPCFG, PMOD_BYPASS, 0, NULL);
  1234. break;
  1235. case L1_MODE_V32:
  1236. ctrl = PMOD_DATAMODEM;
  1237. if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
  1238. ctrl |= PCTRL_ORIG;
  1239. param[5] = PV32P6_CTN;
  1240. } else {
  1241. param[5] = PV32P6_ATN;
  1242. }
  1243. param[0] = para_TOA; /* 6 db */
  1244. param[1] = PV32P2_V23R | PV32P2_V22A | PV32P2_V22B |
  1245. PV32P2_V22C | PV32P2_V21 | PV32P2_BEL;
  1246. param[2] = PV32P3_AMOD | PV32P3_V32B | PV32P3_V23B;
  1247. param[3] = PV32P4_UT144;
  1248. param[4] = PV32P5_UT144;
  1249. sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 6, param);
  1250. break;
  1251. case L1_MODE_FAX:
  1252. ctrl = PMOD_FAX;
  1253. if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
  1254. ctrl |= PCTRL_ORIG;
  1255. param[1] = PFAXP2_CTN;
  1256. } else {
  1257. param[1] = PFAXP2_ATN;
  1258. }
  1259. param[0] = para_TOA; /* 6 db */
  1260. sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 2, param);
  1261. bcs->hw.isar.state = STFAX_NULL;
  1262. bcs->hw.isar.newcmd = 0;
  1263. bcs->hw.isar.newmod = 0;
  1264. test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag);
  1265. break;
  1266. }
  1267. udelay(1000);
  1268. sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
  1269. udelay(1000);
  1270. }
  1271. static void
  1272. setup_sart(struct BCState *bcs) {
  1273. struct IsdnCardState *cs = bcs->cs;
  1274. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  1275. u_char ctrl, param[2];
  1276. switch (bcs->mode) {
  1277. case L1_MODE_NULL:
  1278. sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_DISABLE, 0,
  1279. NULL);
  1280. break;
  1281. case L1_MODE_TRANS:
  1282. sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_BINARY, 2,
  1283. "\0\0");
  1284. break;
  1285. case L1_MODE_HDLC:
  1286. param[0] = 0;
  1287. sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_HDLC, 1,
  1288. param);
  1289. break;
  1290. case L1_MODE_V32:
  1291. ctrl = SMODE_V14 | SCTRL_HDMC_BOTH;
  1292. param[0] = S_P1_CHS_8;
  1293. param[1] = S_P2_BFT_DEF;
  1294. sendmsg(cs, dps | ISAR_HIS_SARTCFG, ctrl, 2,
  1295. param);
  1296. break;
  1297. case L1_MODE_FAX:
  1298. /* SART must not configured with FAX */
  1299. break;
  1300. }
  1301. udelay(1000);
  1302. sendmsg(cs, dps | ISAR_HIS_BSTREQ, 0, 0, NULL);
  1303. udelay(1000);
  1304. }
  1305. static void
  1306. setup_iom2(struct BCState *bcs) {
  1307. struct IsdnCardState *cs = bcs->cs;
  1308. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  1309. u_char cmsb = IOM_CTRL_ENA, msg[5] = {IOM_P1_TXD,0,0,0,0};
  1310. if (bcs->channel)
  1311. msg[1] = msg[3] = 1;
  1312. switch (bcs->mode) {
  1313. case L1_MODE_NULL:
  1314. cmsb = 0;
  1315. /* dummy slot */
  1316. msg[1] = msg[3] = bcs->hw.isar.dpath + 2;
  1317. break;
  1318. case L1_MODE_TRANS:
  1319. case L1_MODE_HDLC:
  1320. break;
  1321. case L1_MODE_V32:
  1322. case L1_MODE_FAX:
  1323. cmsb |= IOM_CTRL_ALAW | IOM_CTRL_RCV;
  1324. break;
  1325. }
  1326. sendmsg(cs, dps | ISAR_HIS_IOM2CFG, cmsb, 5, msg);
  1327. udelay(1000);
  1328. sendmsg(cs, dps | ISAR_HIS_IOM2REQ, 0, 0, NULL);
  1329. udelay(1000);
  1330. }
  1331. static int
  1332. modeisar(struct BCState *bcs, int mode, int bc)
  1333. {
  1334. struct IsdnCardState *cs = bcs->cs;
  1335. /* Here we are selecting the best datapath for requested mode */
  1336. if(bcs->mode == L1_MODE_NULL) { /* New Setup */
  1337. bcs->channel = bc;
  1338. switch (mode) {
  1339. case L1_MODE_NULL: /* init */
  1340. if (!bcs->hw.isar.dpath)
  1341. /* no init for dpath 0 */
  1342. return(0);
  1343. break;
  1344. case L1_MODE_TRANS:
  1345. case L1_MODE_HDLC:
  1346. /* best is datapath 2 */
  1347. if (!test_and_set_bit(ISAR_DP2_USE,
  1348. &bcs->hw.isar.reg->Flags))
  1349. bcs->hw.isar.dpath = 2;
  1350. else if (!test_and_set_bit(ISAR_DP1_USE,
  1351. &bcs->hw.isar.reg->Flags))
  1352. bcs->hw.isar.dpath = 1;
  1353. else {
  1354. printk(KERN_WARNING"isar modeisar both pathes in use\n");
  1355. return(1);
  1356. }
  1357. break;
  1358. case L1_MODE_V32:
  1359. case L1_MODE_FAX:
  1360. /* only datapath 1 */
  1361. if (!test_and_set_bit(ISAR_DP1_USE,
  1362. &bcs->hw.isar.reg->Flags))
  1363. bcs->hw.isar.dpath = 1;
  1364. else {
  1365. printk(KERN_WARNING"isar modeisar analog funktions only with DP1\n");
  1366. debugl1(cs, "isar modeisar analog funktions only with DP1");
  1367. return(1);
  1368. }
  1369. break;
  1370. }
  1371. }
  1372. if (cs->debug & L1_DEB_HSCX)
  1373. debugl1(cs, "isar dp%d mode %d->%d ichan %d",
  1374. bcs->hw.isar.dpath, bcs->mode, mode, bc);
  1375. bcs->mode = mode;
  1376. setup_pump(bcs);
  1377. setup_iom2(bcs);
  1378. setup_sart(bcs);
  1379. if (bcs->mode == L1_MODE_NULL) {
  1380. /* Clear resources */
  1381. if (bcs->hw.isar.dpath == 1)
  1382. test_and_clear_bit(ISAR_DP1_USE, &bcs->hw.isar.reg->Flags);
  1383. else if (bcs->hw.isar.dpath == 2)
  1384. test_and_clear_bit(ISAR_DP2_USE, &bcs->hw.isar.reg->Flags);
  1385. bcs->hw.isar.dpath = 0;
  1386. }
  1387. return(0);
  1388. }
  1389. static void
  1390. isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para)
  1391. {
  1392. struct IsdnCardState *cs = bcs->cs;
  1393. u_char dps = SET_DPS(bcs->hw.isar.dpath);
  1394. u_char ctrl = 0, nom = 0, p1 = 0;
  1395. switch(cmd) {
  1396. case ISDN_FAX_CLASS1_FTM:
  1397. test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  1398. if (bcs->hw.isar.state == STFAX_READY) {
  1399. p1 = para;
  1400. ctrl = PCTRL_CMD_FTM;
  1401. nom = 1;
  1402. bcs->hw.isar.state = STFAX_LINE;
  1403. bcs->hw.isar.cmd = ctrl;
  1404. bcs->hw.isar.mod = para;
  1405. bcs->hw.isar.newmod = 0;
  1406. bcs->hw.isar.newcmd = 0;
  1407. bcs->hw.isar.try_mod = 3;
  1408. } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
  1409. (bcs->hw.isar.cmd == PCTRL_CMD_FTM) &&
  1410. (bcs->hw.isar.mod == para)) {
  1411. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  1412. } else {
  1413. bcs->hw.isar.newmod = para;
  1414. bcs->hw.isar.newcmd = PCTRL_CMD_FTM;
  1415. nom = 0;
  1416. ctrl = PCTRL_CMD_ESC;
  1417. bcs->hw.isar.state = STFAX_ESCAPE;
  1418. }
  1419. break;
  1420. case ISDN_FAX_CLASS1_FTH:
  1421. test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  1422. if (bcs->hw.isar.state == STFAX_READY) {
  1423. p1 = para;
  1424. ctrl = PCTRL_CMD_FTH;
  1425. nom = 1;
  1426. bcs->hw.isar.state = STFAX_LINE;
  1427. bcs->hw.isar.cmd = ctrl;
  1428. bcs->hw.isar.mod = para;
  1429. bcs->hw.isar.newmod = 0;
  1430. bcs->hw.isar.newcmd = 0;
  1431. bcs->hw.isar.try_mod = 3;
  1432. } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
  1433. (bcs->hw.isar.cmd == PCTRL_CMD_FTH) &&
  1434. (bcs->hw.isar.mod == para)) {
  1435. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  1436. } else {
  1437. bcs->hw.isar.newmod = para;
  1438. bcs->hw.isar.newcmd = PCTRL_CMD_FTH;
  1439. nom = 0;
  1440. ctrl = PCTRL_CMD_ESC;
  1441. bcs->hw.isar.state = STFAX_ESCAPE;
  1442. }
  1443. break;
  1444. case ISDN_FAX_CLASS1_FRM:
  1445. test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  1446. if (bcs->hw.isar.state == STFAX_READY) {
  1447. p1 = para;
  1448. ctrl = PCTRL_CMD_FRM;
  1449. nom = 1;
  1450. bcs->hw.isar.state = STFAX_LINE;
  1451. bcs->hw.isar.cmd = ctrl;
  1452. bcs->hw.isar.mod = para;
  1453. bcs->hw.isar.newmod = 0;
  1454. bcs->hw.isar.newcmd = 0;
  1455. bcs->hw.isar.try_mod = 3;
  1456. } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
  1457. (bcs->hw.isar.cmd == PCTRL_CMD_FRM) &&
  1458. (bcs->hw.isar.mod == para)) {
  1459. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  1460. } else {
  1461. bcs->hw.isar.newmod = para;
  1462. bcs->hw.isar.newcmd = PCTRL_CMD_FRM;
  1463. nom = 0;
  1464. ctrl = PCTRL_CMD_ESC;
  1465. bcs->hw.isar.state = STFAX_ESCAPE;
  1466. }
  1467. break;
  1468. case ISDN_FAX_CLASS1_FRH:
  1469. test_and_set_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
  1470. if (bcs->hw.isar.state == STFAX_READY) {
  1471. p1 = para;
  1472. ctrl = PCTRL_CMD_FRH;
  1473. nom = 1;
  1474. bcs->hw.isar.state = STFAX_LINE;
  1475. bcs->hw.isar.cmd = ctrl;
  1476. bcs->hw.isar.mod = para;
  1477. bcs->hw.isar.newmod = 0;
  1478. bcs->hw.isar.newcmd = 0;
  1479. bcs->hw.isar.try_mod = 3;
  1480. } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
  1481. (bcs->hw.isar.cmd == PCTRL_CMD_FRH) &&
  1482. (bcs->hw.isar.mod == para)) {
  1483. ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
  1484. } else {
  1485. bcs->hw.isar.newmod = para;
  1486. bcs->hw.isar.newcmd = PCTRL_CMD_FRH;
  1487. nom = 0;
  1488. ctrl = PCTRL_CMD_ESC;
  1489. bcs->hw.isar.state = STFAX_ESCAPE;
  1490. }
  1491. break;
  1492. case ISDN_FAXPUMP_HALT:
  1493. bcs->hw.isar.state = STFAX_NULL;
  1494. nom = 0;
  1495. ctrl = PCTRL_CMD_HALT;
  1496. break;
  1497. }
  1498. if (ctrl)
  1499. sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, ctrl, nom, &p1);
  1500. }
  1501. static void
  1502. isar_setup(struct IsdnCardState *cs)
  1503. {
  1504. u_char msg;
  1505. int i;
  1506. /* Dpath 1, 2 */
  1507. msg = 61;
  1508. for (i=0; i<2; i++) {
  1509. /* Buffer Config */
  1510. sendmsg(cs, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) |
  1511. ISAR_HIS_P12CFG, 4, 1, &msg);
  1512. cs->bcs[i].hw.isar.mml = msg;
  1513. cs->bcs[i].mode = 0;
  1514. cs->bcs[i].hw.isar.dpath = i + 1;
  1515. modeisar(&cs->bcs[i], 0, 0);
  1516. INIT_WORK(&cs->bcs[i].tqueue, isar_bh);
  1517. }
  1518. }
  1519. static void
  1520. isar_l2l1(struct PStack *st, int pr, void *arg)
  1521. {
  1522. struct BCState *bcs = st->l1.bcs;
  1523. struct sk_buff *skb = arg;
  1524. int ret;
  1525. u_long flags;
  1526. switch (pr) {
  1527. case (PH_DATA | REQUEST):
  1528. spin_lock_irqsave(&bcs->cs->lock, flags);
  1529. if (bcs->tx_skb) {
  1530. skb_queue_tail(&bcs->squeue, skb);
  1531. } else {
  1532. bcs->tx_skb = skb;
  1533. test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
  1534. if (bcs->cs->debug & L1_DEB_HSCX)
  1535. debugl1(bcs->cs, "DRQ set BC_FLG_BUSY");
  1536. bcs->hw.isar.txcnt = 0;
  1537. bcs->cs->BC_Send_Data(bcs);
  1538. }
  1539. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1540. break;
  1541. case (PH_PULL | INDICATION):
  1542. spin_lock_irqsave(&bcs->cs->lock, flags);
  1543. if (bcs->tx_skb) {
  1544. printk(KERN_WARNING "isar_l2l1: this shouldn't happen\n");
  1545. } else {
  1546. test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
  1547. if (bcs->cs->debug & L1_DEB_HSCX)
  1548. debugl1(bcs->cs, "PUI set BC_FLG_BUSY");
  1549. bcs->tx_skb = skb;
  1550. bcs->hw.isar.txcnt = 0;
  1551. bcs->cs->BC_Send_Data(bcs);
  1552. }
  1553. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1554. break;
  1555. case (PH_PULL | REQUEST):
  1556. if (!bcs->tx_skb) {
  1557. test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
  1558. st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
  1559. } else
  1560. test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
  1561. break;
  1562. case (PH_ACTIVATE | REQUEST):
  1563. spin_lock_irqsave(&bcs->cs->lock, flags);
  1564. test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
  1565. bcs->hw.isar.conmsg[0] = 0;
  1566. if (test_bit(FLG_ORIG, &st->l2.flag))
  1567. test_and_set_bit(BC_FLG_ORIG, &bcs->Flag);
  1568. else
  1569. test_and_clear_bit(BC_FLG_ORIG, &bcs->Flag);
  1570. switch(st->l1.mode) {
  1571. case L1_MODE_TRANS:
  1572. case L1_MODE_HDLC:
  1573. ret = modeisar(bcs, st->l1.mode, st->l1.bc);
  1574. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1575. if (ret)
  1576. l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
  1577. else
  1578. l1_msg_b(st, PH_ACTIVATE | REQUEST, arg);
  1579. break;
  1580. case L1_MODE_V32:
  1581. case L1_MODE_FAX:
  1582. ret = modeisar(bcs, st->l1.mode, st->l1.bc);
  1583. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1584. if (ret)
  1585. l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
  1586. break;
  1587. default:
  1588. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1589. break;
  1590. }
  1591. break;
  1592. case (PH_DEACTIVATE | REQUEST):
  1593. l1_msg_b(st, pr, arg);
  1594. break;
  1595. case (PH_DEACTIVATE | CONFIRM):
  1596. spin_lock_irqsave(&bcs->cs->lock, flags);
  1597. switch(st->l1.mode) {
  1598. case L1_MODE_TRANS:
  1599. case L1_MODE_HDLC:
  1600. case L1_MODE_V32:
  1601. break;
  1602. case L1_MODE_FAX:
  1603. isar_pump_cmd(bcs, ISDN_FAXPUMP_HALT, 0);
  1604. break;
  1605. }
  1606. test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
  1607. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  1608. if (bcs->cs->debug & L1_DEB_HSCX)
  1609. debugl1(bcs->cs, "PDAC clear BC_FLG_BUSY");
  1610. modeisar(bcs, 0, st->l1.bc);
  1611. spin_unlock_irqrestore(&bcs->cs->lock, flags);
  1612. st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
  1613. break;
  1614. }
  1615. }
  1616. static void
  1617. close_isarstate(struct BCState *bcs)
  1618. {
  1619. modeisar(bcs, 0, bcs->channel);
  1620. if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
  1621. kfree(bcs->hw.isar.rcvbuf);
  1622. bcs->hw.isar.rcvbuf = NULL;
  1623. skb_queue_purge(&bcs->rqueue);
  1624. skb_queue_purge(&bcs->squeue);
  1625. if (bcs->tx_skb) {
  1626. dev_kfree_skb_any(bcs->tx_skb);
  1627. bcs->tx_skb = NULL;
  1628. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  1629. if (bcs->cs->debug & L1_DEB_HSCX)
  1630. debugl1(bcs->cs, "closeisar clear BC_FLG_BUSY");
  1631. }
  1632. }
  1633. del_timer(&bcs->hw.isar.ftimer);
  1634. }
  1635. static int
  1636. open_isarstate(struct IsdnCardState *cs, struct BCState *bcs)
  1637. {
  1638. if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
  1639. if (!(bcs->hw.isar.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
  1640. printk(KERN_WARNING
  1641. "HiSax: No memory for isar.rcvbuf\n");
  1642. return (1);
  1643. }
  1644. skb_queue_head_init(&bcs->rqueue);
  1645. skb_queue_head_init(&bcs->squeue);
  1646. }
  1647. bcs->tx_skb = NULL;
  1648. test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
  1649. if (cs->debug & L1_DEB_HSCX)
  1650. debugl1(cs, "openisar clear BC_FLG_BUSY");
  1651. bcs->event = 0;
  1652. bcs->hw.isar.rcvidx = 0;
  1653. bcs->tx_cnt = 0;
  1654. return (0);
  1655. }
  1656. static int
  1657. setstack_isar(struct PStack *st, struct BCState *bcs)
  1658. {
  1659. bcs->channel = st->l1.bc;
  1660. if (open_isarstate(st->l1.hardware, bcs))
  1661. return (-1);
  1662. st->l1.bcs = bcs;
  1663. st->l2.l2l1 = isar_l2l1;
  1664. setstack_manager(st);
  1665. bcs->st = st;
  1666. setstack_l1_B(st);
  1667. return (0);
  1668. }
  1669. int
  1670. isar_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) {
  1671. u_long adr;
  1672. int features, i;
  1673. struct BCState *bcs;
  1674. if (cs->debug & L1_DEB_HSCX)
  1675. debugl1(cs, "isar_auxcmd cmd/ch %x/%d", ic->command, ic->arg);
  1676. switch (ic->command) {
  1677. case (ISDN_CMD_FAXCMD):
  1678. bcs = cs->channel[ic->arg].bcs;
  1679. if (cs->debug & L1_DEB_HSCX)
  1680. debugl1(cs, "isar_auxcmd cmd/subcmd %d/%d",
  1681. ic->parm.aux.cmd, ic->parm.aux.subcmd);
  1682. switch(ic->parm.aux.cmd) {
  1683. case ISDN_FAX_CLASS1_CTRL:
  1684. if (ic->parm.aux.subcmd == ETX)
  1685. test_and_set_bit(BC_FLG_DLEETX,
  1686. &bcs->Flag);
  1687. break;
  1688. case ISDN_FAX_CLASS1_FTS:
  1689. if (ic->parm.aux.subcmd == AT_QUERY) {
  1690. ic->command = ISDN_STAT_FAXIND;
  1691. ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK;
  1692. cs->iif.statcallb(ic);
  1693. return(0);
  1694. } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) {
  1695. strcpy(ic->parm.aux.para, "0-255");
  1696. ic->command = ISDN_STAT_FAXIND;
  1697. ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
  1698. cs->iif.statcallb(ic);
  1699. return(0);
  1700. } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) {
  1701. if (cs->debug & L1_DEB_HSCX)
  1702. debugl1(cs, "isar_auxcmd %s=%d",
  1703. FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]);
  1704. if (bcs->hw.isar.state == STFAX_READY) {
  1705. if (! ic->parm.aux.para[0]) {
  1706. ic->command = ISDN_STAT_FAXIND;
  1707. ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK;
  1708. cs->iif.statcallb(ic);
  1709. return(0);
  1710. }
  1711. if (! test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag)) {
  1712. /* n*10 ms */
  1713. bcs->hw.isar.ftimer.expires =
  1714. jiffies + ((ic->parm.aux.para[0] * 10 * HZ)/1000);
  1715. test_and_set_bit(BC_FLG_FTI_FTS, &bcs->Flag);
  1716. add_timer(&bcs->hw.isar.ftimer);
  1717. return(0);
  1718. } else {
  1719. if (cs->debug)
  1720. debugl1(cs, "isar FTS=%d and FTI busy",
  1721. ic->parm.aux.para[0]);
  1722. }
  1723. } else {
  1724. if (cs->debug)
  1725. debugl1(cs, "isar FTS=%d and isar.state not ready(%x)",
  1726. ic->parm.aux.para[0],bcs->hw.isar.state);
  1727. }
  1728. ic->command = ISDN_STAT_FAXIND;
  1729. ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR;
  1730. cs->iif.statcallb(ic);
  1731. }
  1732. break;
  1733. case ISDN_FAX_CLASS1_FRM:
  1734. case ISDN_FAX_CLASS1_FRH:
  1735. case ISDN_FAX_CLASS1_FTM:
  1736. case ISDN_FAX_CLASS1_FTH:
  1737. if (ic->parm.aux.subcmd == AT_QUERY) {
  1738. sprintf(ic->parm.aux.para,
  1739. "%d", bcs->hw.isar.mod);
  1740. ic->command = ISDN_STAT_FAXIND;
  1741. ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
  1742. cs->iif.statcallb(ic);
  1743. return(0);
  1744. } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) {
  1745. char *p = ic->parm.aux.para;
  1746. for(i=0;i<FAXMODCNT;i++)
  1747. if ((1<<i) & modmask)
  1748. p += sprintf(p, "%d,", faxmodulation[i]);
  1749. p--;
  1750. *p=0;
  1751. ic->command = ISDN_STAT_FAXIND;
  1752. ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
  1753. cs->iif.statcallb(ic);
  1754. return(0);
  1755. } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) {
  1756. if (cs->debug & L1_DEB_HSCX)
  1757. debugl1(cs, "isar_auxcmd %s=%d",
  1758. FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]);
  1759. for(i=0;i<FAXMODCNT;i++)
  1760. if (faxmodulation[i]==ic->parm.aux.para[0])
  1761. break;
  1762. if ((i < FAXMODCNT) && ((1<<i) & modmask) &&
  1763. test_bit(BC_FLG_INIT, &bcs->Flag)) {
  1764. isar_pump_cmd(bcs,
  1765. ic->parm.aux.cmd,
  1766. ic->parm.aux.para[0]);
  1767. return(0);
  1768. }
  1769. }
  1770. /* wrong modulation or not activ */
  1771. /* fall through */
  1772. default:
  1773. ic->command = ISDN_STAT_FAXIND;
  1774. ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR;
  1775. cs->iif.statcallb(ic);
  1776. }
  1777. break;
  1778. case (ISDN_CMD_IOCTL):
  1779. switch (ic->arg) {
  1780. case 9: /* load firmware */
  1781. features = ISDN_FEATURE_L2_MODEM |
  1782. ISDN_FEATURE_L2_FAX |
  1783. ISDN_FEATURE_L3_FCLASS1;
  1784. memcpy(&adr, ic->parm.num, sizeof(ulong));
  1785. if (isar_load_firmware(cs, (u_char __user *)adr))
  1786. return(1);
  1787. else
  1788. ll_run(cs, features);
  1789. break;
  1790. case 20:
  1791. features = *(unsigned int *) ic->parm.num;
  1792. printk(KERN_DEBUG "HiSax: max modulation old(%04x) new(%04x)\n",
  1793. modmask, features);
  1794. modmask = features;
  1795. break;
  1796. case 21:
  1797. features = *(unsigned int *) ic->parm.num;
  1798. printk(KERN_DEBUG "HiSax: FRM extra delay old(%d) new(%d) ms\n",
  1799. frm_extra_delay, features);
  1800. if (features >= 0)
  1801. frm_extra_delay = features;
  1802. break;
  1803. case 22:
  1804. features = *(unsigned int *) ic->parm.num;
  1805. printk(KERN_DEBUG "HiSax: TOA old(%d) new(%d) db\n",
  1806. para_TOA, features);
  1807. if (features >= 0 && features < 32)
  1808. para_TOA = features;
  1809. break;
  1810. default:
  1811. printk(KERN_DEBUG "HiSax: invalid ioctl %d\n",
  1812. (int) ic->arg);
  1813. return(-EINVAL);
  1814. }
  1815. break;
  1816. default:
  1817. return(-EINVAL);
  1818. }
  1819. return(0);
  1820. }
  1821. void initisar(struct IsdnCardState *cs)
  1822. {
  1823. cs->bcs[0].BC_SetStack = setstack_isar;
  1824. cs->bcs[1].BC_SetStack = setstack_isar;
  1825. cs->bcs[0].BC_Close = close_isarstate;
  1826. cs->bcs[1].BC_Close = close_isarstate;
  1827. cs->bcs[0].hw.isar.ftimer.function = (void *) ftimer_handler;
  1828. cs->bcs[0].hw.isar.ftimer.data = (long) &cs->bcs[0];
  1829. init_timer(&cs->bcs[0].hw.isar.ftimer);
  1830. cs->bcs[1].hw.isar.ftimer.function = (void *) ftimer_handler;
  1831. cs->bcs[1].hw.isar.ftimer.data = (long) &cs->bcs[1];
  1832. init_timer(&cs->bcs[1].hw.isar.ftimer);
  1833. }