cq.c 20 KB

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  1. /*
  2. * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/mlx4/cq.h>
  34. #include <linux/mlx4/qp.h>
  35. #include "mlx4_ib.h"
  36. #include "user.h"
  37. static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
  38. {
  39. struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
  40. ibcq->comp_handler(ibcq, ibcq->cq_context);
  41. }
  42. static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
  43. {
  44. struct ib_event event;
  45. struct ib_cq *ibcq;
  46. if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
  47. printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
  48. "on CQ %06x\n", type, cq->cqn);
  49. return;
  50. }
  51. ibcq = &to_mibcq(cq)->ibcq;
  52. if (ibcq->event_handler) {
  53. event.device = ibcq->device;
  54. event.event = IB_EVENT_CQ_ERR;
  55. event.element.cq = ibcq;
  56. ibcq->event_handler(&event, ibcq->cq_context);
  57. }
  58. }
  59. static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
  60. {
  61. return mlx4_buf_offset(&buf->buf, n * sizeof (struct mlx4_cqe));
  62. }
  63. static void *get_cqe(struct mlx4_ib_cq *cq, int n)
  64. {
  65. return get_cqe_from_buf(&cq->buf, n);
  66. }
  67. static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
  68. {
  69. struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
  70. return (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
  71. !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
  72. }
  73. static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
  74. {
  75. return get_sw_cqe(cq, cq->mcq.cons_index);
  76. }
  77. int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
  78. {
  79. struct mlx4_ib_cq *mcq = to_mcq(cq);
  80. struct mlx4_ib_dev *dev = to_mdev(cq->device);
  81. return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
  82. }
  83. static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
  84. {
  85. int err;
  86. err = mlx4_buf_alloc(dev->dev, nent * sizeof(struct mlx4_cqe),
  87. PAGE_SIZE * 2, &buf->buf);
  88. if (err)
  89. goto out;
  90. err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
  91. &buf->mtt);
  92. if (err)
  93. goto err_buf;
  94. err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf);
  95. if (err)
  96. goto err_mtt;
  97. return 0;
  98. err_mtt:
  99. mlx4_mtt_cleanup(dev->dev, &buf->mtt);
  100. err_buf:
  101. mlx4_buf_free(dev->dev, nent * sizeof(struct mlx4_cqe),
  102. &buf->buf);
  103. out:
  104. return err;
  105. }
  106. static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
  107. {
  108. mlx4_buf_free(dev->dev, (cqe + 1) * sizeof(struct mlx4_cqe), &buf->buf);
  109. }
  110. static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context,
  111. struct mlx4_ib_cq_buf *buf, struct ib_umem **umem,
  112. u64 buf_addr, int cqe)
  113. {
  114. int err;
  115. *umem = ib_umem_get(context, buf_addr, cqe * sizeof (struct mlx4_cqe),
  116. IB_ACCESS_LOCAL_WRITE, 1);
  117. if (IS_ERR(*umem))
  118. return PTR_ERR(*umem);
  119. err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem),
  120. ilog2((*umem)->page_size), &buf->mtt);
  121. if (err)
  122. goto err_buf;
  123. err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
  124. if (err)
  125. goto err_mtt;
  126. return 0;
  127. err_mtt:
  128. mlx4_mtt_cleanup(dev->dev, &buf->mtt);
  129. err_buf:
  130. ib_umem_release(*umem);
  131. return err;
  132. }
  133. struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector,
  134. struct ib_ucontext *context,
  135. struct ib_udata *udata)
  136. {
  137. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  138. struct mlx4_ib_cq *cq;
  139. struct mlx4_uar *uar;
  140. int err;
  141. if (entries < 1 || entries > dev->dev->caps.max_cqes)
  142. return ERR_PTR(-EINVAL);
  143. cq = kmalloc(sizeof *cq, GFP_KERNEL);
  144. if (!cq)
  145. return ERR_PTR(-ENOMEM);
  146. entries = roundup_pow_of_two(entries + 1);
  147. cq->ibcq.cqe = entries - 1;
  148. mutex_init(&cq->resize_mutex);
  149. spin_lock_init(&cq->lock);
  150. cq->resize_buf = NULL;
  151. cq->resize_umem = NULL;
  152. if (context) {
  153. struct mlx4_ib_create_cq ucmd;
  154. if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
  155. err = -EFAULT;
  156. goto err_cq;
  157. }
  158. err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem,
  159. ucmd.buf_addr, entries);
  160. if (err)
  161. goto err_cq;
  162. err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
  163. &cq->db);
  164. if (err)
  165. goto err_mtt;
  166. uar = &to_mucontext(context)->uar;
  167. } else {
  168. err = mlx4_db_alloc(dev->dev, &cq->db, 1);
  169. if (err)
  170. goto err_cq;
  171. cq->mcq.set_ci_db = cq->db.db;
  172. cq->mcq.arm_db = cq->db.db + 1;
  173. *cq->mcq.set_ci_db = 0;
  174. *cq->mcq.arm_db = 0;
  175. err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
  176. if (err)
  177. goto err_db;
  178. uar = &dev->priv_uar;
  179. }
  180. err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar,
  181. cq->db.dma, &cq->mcq, 0);
  182. if (err)
  183. goto err_dbmap;
  184. cq->mcq.comp = mlx4_ib_cq_comp;
  185. cq->mcq.event = mlx4_ib_cq_event;
  186. if (context)
  187. if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
  188. err = -EFAULT;
  189. goto err_dbmap;
  190. }
  191. return &cq->ibcq;
  192. err_dbmap:
  193. if (context)
  194. mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);
  195. err_mtt:
  196. mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
  197. if (context)
  198. ib_umem_release(cq->umem);
  199. else
  200. mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
  201. err_db:
  202. if (!context)
  203. mlx4_db_free(dev->dev, &cq->db);
  204. err_cq:
  205. kfree(cq);
  206. return ERR_PTR(err);
  207. }
  208. static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
  209. int entries)
  210. {
  211. int err;
  212. if (cq->resize_buf)
  213. return -EBUSY;
  214. cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
  215. if (!cq->resize_buf)
  216. return -ENOMEM;
  217. err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
  218. if (err) {
  219. kfree(cq->resize_buf);
  220. cq->resize_buf = NULL;
  221. return err;
  222. }
  223. cq->resize_buf->cqe = entries - 1;
  224. return 0;
  225. }
  226. static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
  227. int entries, struct ib_udata *udata)
  228. {
  229. struct mlx4_ib_resize_cq ucmd;
  230. int err;
  231. if (cq->resize_umem)
  232. return -EBUSY;
  233. if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
  234. return -EFAULT;
  235. cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
  236. if (!cq->resize_buf)
  237. return -ENOMEM;
  238. err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf,
  239. &cq->resize_umem, ucmd.buf_addr, entries);
  240. if (err) {
  241. kfree(cq->resize_buf);
  242. cq->resize_buf = NULL;
  243. return err;
  244. }
  245. cq->resize_buf->cqe = entries - 1;
  246. return 0;
  247. }
  248. static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
  249. {
  250. u32 i;
  251. i = cq->mcq.cons_index;
  252. while (get_sw_cqe(cq, i & cq->ibcq.cqe))
  253. ++i;
  254. return i - cq->mcq.cons_index;
  255. }
  256. static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
  257. {
  258. struct mlx4_cqe *cqe;
  259. int i;
  260. i = cq->mcq.cons_index;
  261. cqe = get_cqe(cq, i & cq->ibcq.cqe);
  262. while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
  263. memcpy(get_cqe_from_buf(&cq->resize_buf->buf,
  264. (i + 1) & cq->resize_buf->cqe),
  265. get_cqe(cq, i & cq->ibcq.cqe), sizeof(struct mlx4_cqe));
  266. cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
  267. }
  268. ++cq->mcq.cons_index;
  269. }
  270. int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
  271. {
  272. struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
  273. struct mlx4_ib_cq *cq = to_mcq(ibcq);
  274. int outst_cqe;
  275. int err;
  276. mutex_lock(&cq->resize_mutex);
  277. if (entries < 1 || entries > dev->dev->caps.max_cqes) {
  278. err = -EINVAL;
  279. goto out;
  280. }
  281. entries = roundup_pow_of_two(entries + 1);
  282. if (entries == ibcq->cqe + 1) {
  283. err = 0;
  284. goto out;
  285. }
  286. if (ibcq->uobject) {
  287. err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
  288. if (err)
  289. goto out;
  290. } else {
  291. /* Can't be smaller then the number of outstanding CQEs */
  292. outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
  293. if (entries < outst_cqe + 1) {
  294. err = 0;
  295. goto out;
  296. }
  297. err = mlx4_alloc_resize_buf(dev, cq, entries);
  298. if (err)
  299. goto out;
  300. }
  301. err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
  302. if (err)
  303. goto err_buf;
  304. if (ibcq->uobject) {
  305. cq->buf = cq->resize_buf->buf;
  306. cq->ibcq.cqe = cq->resize_buf->cqe;
  307. ib_umem_release(cq->umem);
  308. cq->umem = cq->resize_umem;
  309. kfree(cq->resize_buf);
  310. cq->resize_buf = NULL;
  311. cq->resize_umem = NULL;
  312. } else {
  313. spin_lock_irq(&cq->lock);
  314. if (cq->resize_buf) {
  315. mlx4_ib_cq_resize_copy_cqes(cq);
  316. mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
  317. cq->buf = cq->resize_buf->buf;
  318. cq->ibcq.cqe = cq->resize_buf->cqe;
  319. kfree(cq->resize_buf);
  320. cq->resize_buf = NULL;
  321. }
  322. spin_unlock_irq(&cq->lock);
  323. }
  324. goto out;
  325. err_buf:
  326. if (!ibcq->uobject)
  327. mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
  328. cq->resize_buf->cqe);
  329. kfree(cq->resize_buf);
  330. cq->resize_buf = NULL;
  331. if (cq->resize_umem) {
  332. ib_umem_release(cq->resize_umem);
  333. cq->resize_umem = NULL;
  334. }
  335. out:
  336. mutex_unlock(&cq->resize_mutex);
  337. return err;
  338. }
  339. int mlx4_ib_destroy_cq(struct ib_cq *cq)
  340. {
  341. struct mlx4_ib_dev *dev = to_mdev(cq->device);
  342. struct mlx4_ib_cq *mcq = to_mcq(cq);
  343. mlx4_cq_free(dev->dev, &mcq->mcq);
  344. mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
  345. if (cq->uobject) {
  346. mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db);
  347. ib_umem_release(mcq->umem);
  348. } else {
  349. mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
  350. mlx4_db_free(dev->dev, &mcq->db);
  351. }
  352. kfree(mcq);
  353. return 0;
  354. }
  355. static void dump_cqe(void *cqe)
  356. {
  357. __be32 *buf = cqe;
  358. printk(KERN_DEBUG "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
  359. be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
  360. be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
  361. be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
  362. }
  363. static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
  364. struct ib_wc *wc)
  365. {
  366. if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
  367. printk(KERN_DEBUG "local QP operation err "
  368. "(QPN %06x, WQE index %x, vendor syndrome %02x, "
  369. "opcode = %02x)\n",
  370. be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
  371. cqe->vendor_err_syndrome,
  372. cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
  373. dump_cqe(cqe);
  374. }
  375. switch (cqe->syndrome) {
  376. case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
  377. wc->status = IB_WC_LOC_LEN_ERR;
  378. break;
  379. case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
  380. wc->status = IB_WC_LOC_QP_OP_ERR;
  381. break;
  382. case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
  383. wc->status = IB_WC_LOC_PROT_ERR;
  384. break;
  385. case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
  386. wc->status = IB_WC_WR_FLUSH_ERR;
  387. break;
  388. case MLX4_CQE_SYNDROME_MW_BIND_ERR:
  389. wc->status = IB_WC_MW_BIND_ERR;
  390. break;
  391. case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
  392. wc->status = IB_WC_BAD_RESP_ERR;
  393. break;
  394. case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
  395. wc->status = IB_WC_LOC_ACCESS_ERR;
  396. break;
  397. case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
  398. wc->status = IB_WC_REM_INV_REQ_ERR;
  399. break;
  400. case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
  401. wc->status = IB_WC_REM_ACCESS_ERR;
  402. break;
  403. case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
  404. wc->status = IB_WC_REM_OP_ERR;
  405. break;
  406. case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
  407. wc->status = IB_WC_RETRY_EXC_ERR;
  408. break;
  409. case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
  410. wc->status = IB_WC_RNR_RETRY_EXC_ERR;
  411. break;
  412. case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
  413. wc->status = IB_WC_REM_ABORT_ERR;
  414. break;
  415. default:
  416. wc->status = IB_WC_GENERAL_ERR;
  417. break;
  418. }
  419. wc->vendor_err = cqe->vendor_err_syndrome;
  420. }
  421. static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
  422. {
  423. return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
  424. MLX4_CQE_STATUS_IPV4F |
  425. MLX4_CQE_STATUS_IPV4OPT |
  426. MLX4_CQE_STATUS_IPV6 |
  427. MLX4_CQE_STATUS_IPOK)) ==
  428. cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
  429. MLX4_CQE_STATUS_IPOK)) &&
  430. (status & cpu_to_be16(MLX4_CQE_STATUS_UDP |
  431. MLX4_CQE_STATUS_TCP)) &&
  432. checksum == cpu_to_be16(0xffff);
  433. }
  434. static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
  435. struct mlx4_ib_qp **cur_qp,
  436. struct ib_wc *wc)
  437. {
  438. struct mlx4_cqe *cqe;
  439. struct mlx4_qp *mqp;
  440. struct mlx4_ib_wq *wq;
  441. struct mlx4_ib_srq *srq;
  442. int is_send;
  443. int is_error;
  444. u32 g_mlpath_rqpn;
  445. u16 wqe_ctr;
  446. repoll:
  447. cqe = next_cqe_sw(cq);
  448. if (!cqe)
  449. return -EAGAIN;
  450. ++cq->mcq.cons_index;
  451. /*
  452. * Make sure we read CQ entry contents after we've checked the
  453. * ownership bit.
  454. */
  455. rmb();
  456. is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
  457. is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
  458. MLX4_CQE_OPCODE_ERROR;
  459. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP &&
  460. is_send)) {
  461. printk(KERN_WARNING "Completion for NOP opcode detected!\n");
  462. return -EINVAL;
  463. }
  464. /* Resize CQ in progress */
  465. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
  466. if (cq->resize_buf) {
  467. struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
  468. mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
  469. cq->buf = cq->resize_buf->buf;
  470. cq->ibcq.cqe = cq->resize_buf->cqe;
  471. kfree(cq->resize_buf);
  472. cq->resize_buf = NULL;
  473. }
  474. goto repoll;
  475. }
  476. if (!*cur_qp ||
  477. (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
  478. /*
  479. * We do not have to take the QP table lock here,
  480. * because CQs will be locked while QPs are removed
  481. * from the table.
  482. */
  483. mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
  484. be32_to_cpu(cqe->vlan_my_qpn));
  485. if (unlikely(!mqp)) {
  486. printk(KERN_WARNING "CQ %06x with entry for unknown QPN %06x\n",
  487. cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK);
  488. return -EINVAL;
  489. }
  490. *cur_qp = to_mibqp(mqp);
  491. }
  492. wc->qp = &(*cur_qp)->ibqp;
  493. if (is_send) {
  494. wq = &(*cur_qp)->sq;
  495. if (!(*cur_qp)->sq_signal_bits) {
  496. wqe_ctr = be16_to_cpu(cqe->wqe_index);
  497. wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
  498. }
  499. wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
  500. ++wq->tail;
  501. } else if ((*cur_qp)->ibqp.srq) {
  502. srq = to_msrq((*cur_qp)->ibqp.srq);
  503. wqe_ctr = be16_to_cpu(cqe->wqe_index);
  504. wc->wr_id = srq->wrid[wqe_ctr];
  505. mlx4_ib_free_srq_wqe(srq, wqe_ctr);
  506. } else {
  507. wq = &(*cur_qp)->rq;
  508. wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
  509. ++wq->tail;
  510. }
  511. if (unlikely(is_error)) {
  512. mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
  513. return 0;
  514. }
  515. wc->status = IB_WC_SUCCESS;
  516. if (is_send) {
  517. wc->wc_flags = 0;
  518. switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
  519. case MLX4_OPCODE_RDMA_WRITE_IMM:
  520. wc->wc_flags |= IB_WC_WITH_IMM;
  521. case MLX4_OPCODE_RDMA_WRITE:
  522. wc->opcode = IB_WC_RDMA_WRITE;
  523. break;
  524. case MLX4_OPCODE_SEND_IMM:
  525. wc->wc_flags |= IB_WC_WITH_IMM;
  526. case MLX4_OPCODE_SEND:
  527. case MLX4_OPCODE_SEND_INVAL:
  528. wc->opcode = IB_WC_SEND;
  529. break;
  530. case MLX4_OPCODE_RDMA_READ:
  531. wc->opcode = IB_WC_RDMA_READ;
  532. wc->byte_len = be32_to_cpu(cqe->byte_cnt);
  533. break;
  534. case MLX4_OPCODE_ATOMIC_CS:
  535. wc->opcode = IB_WC_COMP_SWAP;
  536. wc->byte_len = 8;
  537. break;
  538. case MLX4_OPCODE_ATOMIC_FA:
  539. wc->opcode = IB_WC_FETCH_ADD;
  540. wc->byte_len = 8;
  541. break;
  542. case MLX4_OPCODE_BIND_MW:
  543. wc->opcode = IB_WC_BIND_MW;
  544. break;
  545. case MLX4_OPCODE_LSO:
  546. wc->opcode = IB_WC_LSO;
  547. break;
  548. case MLX4_OPCODE_FMR:
  549. wc->opcode = IB_WC_FAST_REG_MR;
  550. break;
  551. case MLX4_OPCODE_LOCAL_INVAL:
  552. wc->opcode = IB_WC_LOCAL_INV;
  553. break;
  554. }
  555. } else {
  556. wc->byte_len = be32_to_cpu(cqe->byte_cnt);
  557. switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
  558. case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
  559. wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  560. wc->wc_flags = IB_WC_WITH_IMM;
  561. wc->ex.imm_data = cqe->immed_rss_invalid;
  562. break;
  563. case MLX4_RECV_OPCODE_SEND_INVAL:
  564. wc->opcode = IB_WC_RECV;
  565. wc->wc_flags = IB_WC_WITH_INVALIDATE;
  566. wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid);
  567. break;
  568. case MLX4_RECV_OPCODE_SEND:
  569. wc->opcode = IB_WC_RECV;
  570. wc->wc_flags = 0;
  571. break;
  572. case MLX4_RECV_OPCODE_SEND_IMM:
  573. wc->opcode = IB_WC_RECV;
  574. wc->wc_flags = IB_WC_WITH_IMM;
  575. wc->ex.imm_data = cqe->immed_rss_invalid;
  576. break;
  577. }
  578. wc->slid = be16_to_cpu(cqe->rlid);
  579. wc->sl = be16_to_cpu(cqe->sl_vid >> 12);
  580. g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
  581. wc->src_qp = g_mlpath_rqpn & 0xffffff;
  582. wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
  583. wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
  584. wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
  585. wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->status, cqe->checksum);
  586. }
  587. return 0;
  588. }
  589. int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
  590. {
  591. struct mlx4_ib_cq *cq = to_mcq(ibcq);
  592. struct mlx4_ib_qp *cur_qp = NULL;
  593. unsigned long flags;
  594. int npolled;
  595. int err = 0;
  596. spin_lock_irqsave(&cq->lock, flags);
  597. for (npolled = 0; npolled < num_entries; ++npolled) {
  598. err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled);
  599. if (err)
  600. break;
  601. }
  602. if (npolled)
  603. mlx4_cq_set_ci(&cq->mcq);
  604. spin_unlock_irqrestore(&cq->lock, flags);
  605. if (err == 0 || err == -EAGAIN)
  606. return npolled;
  607. else
  608. return err;
  609. }
  610. int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
  611. {
  612. mlx4_cq_arm(&to_mcq(ibcq)->mcq,
  613. (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
  614. MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
  615. to_mdev(ibcq->device)->uar_map,
  616. MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
  617. return 0;
  618. }
  619. void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
  620. {
  621. u32 prod_index;
  622. int nfreed = 0;
  623. struct mlx4_cqe *cqe, *dest;
  624. u8 owner_bit;
  625. /*
  626. * First we need to find the current producer index, so we
  627. * know where to start cleaning from. It doesn't matter if HW
  628. * adds new entries after this loop -- the QP we're worried
  629. * about is already in RESET, so the new entries won't come
  630. * from our QP and therefore don't need to be checked.
  631. */
  632. for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
  633. if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
  634. break;
  635. /*
  636. * Now sweep backwards through the CQ, removing CQ entries
  637. * that match our QP by copying older entries on top of them.
  638. */
  639. while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
  640. cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
  641. if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
  642. if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
  643. mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
  644. ++nfreed;
  645. } else if (nfreed) {
  646. dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
  647. owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
  648. memcpy(dest, cqe, sizeof *cqe);
  649. dest->owner_sr_opcode = owner_bit |
  650. (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
  651. }
  652. }
  653. if (nfreed) {
  654. cq->mcq.cons_index += nfreed;
  655. /*
  656. * Make sure update of buffer contents is done before
  657. * updating consumer index.
  658. */
  659. wmb();
  660. mlx4_cq_set_ci(&cq->mcq);
  661. }
  662. }
  663. void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
  664. {
  665. spin_lock_irq(&cq->lock);
  666. __mlx4_ib_cq_clean(cq, qpn, srq);
  667. spin_unlock_irq(&cq->lock);
  668. }