ipath_rc.c 52 KB

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  1. /*
  2. * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
  3. * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/io.h>
  34. #include "ipath_verbs.h"
  35. #include "ipath_kernel.h"
  36. /* cut down ridiculously long IB macro names */
  37. #define OP(x) IB_OPCODE_RC_##x
  38. static u32 restart_sge(struct ipath_sge_state *ss, struct ipath_swqe *wqe,
  39. u32 psn, u32 pmtu)
  40. {
  41. u32 len;
  42. len = ((psn - wqe->psn) & IPATH_PSN_MASK) * pmtu;
  43. ss->sge = wqe->sg_list[0];
  44. ss->sg_list = wqe->sg_list + 1;
  45. ss->num_sge = wqe->wr.num_sge;
  46. ipath_skip_sge(ss, len);
  47. return wqe->length - len;
  48. }
  49. /**
  50. * ipath_init_restart- initialize the qp->s_sge after a restart
  51. * @qp: the QP who's SGE we're restarting
  52. * @wqe: the work queue to initialize the QP's SGE from
  53. *
  54. * The QP s_lock should be held and interrupts disabled.
  55. */
  56. static void ipath_init_restart(struct ipath_qp *qp, struct ipath_swqe *wqe)
  57. {
  58. struct ipath_ibdev *dev;
  59. qp->s_len = restart_sge(&qp->s_sge, wqe, qp->s_psn,
  60. ib_mtu_enum_to_int(qp->path_mtu));
  61. dev = to_idev(qp->ibqp.device);
  62. spin_lock(&dev->pending_lock);
  63. if (list_empty(&qp->timerwait))
  64. list_add_tail(&qp->timerwait,
  65. &dev->pending[dev->pending_index]);
  66. spin_unlock(&dev->pending_lock);
  67. }
  68. /**
  69. * ipath_make_rc_ack - construct a response packet (ACK, NAK, or RDMA read)
  70. * @qp: a pointer to the QP
  71. * @ohdr: a pointer to the IB header being constructed
  72. * @pmtu: the path MTU
  73. *
  74. * Return 1 if constructed; otherwise, return 0.
  75. * Note that we are in the responder's side of the QP context.
  76. * Note the QP s_lock must be held.
  77. */
  78. static int ipath_make_rc_ack(struct ipath_ibdev *dev, struct ipath_qp *qp,
  79. struct ipath_other_headers *ohdr, u32 pmtu)
  80. {
  81. struct ipath_ack_entry *e;
  82. u32 hwords;
  83. u32 len;
  84. u32 bth0;
  85. u32 bth2;
  86. /* Don't send an ACK if we aren't supposed to. */
  87. if (!(ib_ipath_state_ops[qp->state] & IPATH_PROCESS_RECV_OK))
  88. goto bail;
  89. /* header size in 32-bit words LRH+BTH = (8+12)/4. */
  90. hwords = 5;
  91. switch (qp->s_ack_state) {
  92. case OP(RDMA_READ_RESPONSE_LAST):
  93. case OP(RDMA_READ_RESPONSE_ONLY):
  94. case OP(ATOMIC_ACKNOWLEDGE):
  95. /*
  96. * We can increment the tail pointer now that the last
  97. * response has been sent instead of only being
  98. * constructed.
  99. */
  100. if (++qp->s_tail_ack_queue > IPATH_MAX_RDMA_ATOMIC)
  101. qp->s_tail_ack_queue = 0;
  102. /* FALLTHROUGH */
  103. case OP(SEND_ONLY):
  104. case OP(ACKNOWLEDGE):
  105. /* Check for no next entry in the queue. */
  106. if (qp->r_head_ack_queue == qp->s_tail_ack_queue) {
  107. if (qp->s_flags & IPATH_S_ACK_PENDING)
  108. goto normal;
  109. qp->s_ack_state = OP(ACKNOWLEDGE);
  110. goto bail;
  111. }
  112. e = &qp->s_ack_queue[qp->s_tail_ack_queue];
  113. if (e->opcode == OP(RDMA_READ_REQUEST)) {
  114. /* Copy SGE state in case we need to resend */
  115. qp->s_ack_rdma_sge = e->rdma_sge;
  116. qp->s_cur_sge = &qp->s_ack_rdma_sge;
  117. len = e->rdma_sge.sge.sge_length;
  118. if (len > pmtu) {
  119. len = pmtu;
  120. qp->s_ack_state = OP(RDMA_READ_RESPONSE_FIRST);
  121. } else {
  122. qp->s_ack_state = OP(RDMA_READ_RESPONSE_ONLY);
  123. e->sent = 1;
  124. }
  125. ohdr->u.aeth = ipath_compute_aeth(qp);
  126. hwords++;
  127. qp->s_ack_rdma_psn = e->psn;
  128. bth2 = qp->s_ack_rdma_psn++ & IPATH_PSN_MASK;
  129. } else {
  130. /* COMPARE_SWAP or FETCH_ADD */
  131. qp->s_cur_sge = NULL;
  132. len = 0;
  133. qp->s_ack_state = OP(ATOMIC_ACKNOWLEDGE);
  134. ohdr->u.at.aeth = ipath_compute_aeth(qp);
  135. ohdr->u.at.atomic_ack_eth[0] =
  136. cpu_to_be32(e->atomic_data >> 32);
  137. ohdr->u.at.atomic_ack_eth[1] =
  138. cpu_to_be32(e->atomic_data);
  139. hwords += sizeof(ohdr->u.at) / sizeof(u32);
  140. bth2 = e->psn;
  141. e->sent = 1;
  142. }
  143. bth0 = qp->s_ack_state << 24;
  144. break;
  145. case OP(RDMA_READ_RESPONSE_FIRST):
  146. qp->s_ack_state = OP(RDMA_READ_RESPONSE_MIDDLE);
  147. /* FALLTHROUGH */
  148. case OP(RDMA_READ_RESPONSE_MIDDLE):
  149. len = qp->s_ack_rdma_sge.sge.sge_length;
  150. if (len > pmtu)
  151. len = pmtu;
  152. else {
  153. ohdr->u.aeth = ipath_compute_aeth(qp);
  154. hwords++;
  155. qp->s_ack_state = OP(RDMA_READ_RESPONSE_LAST);
  156. qp->s_ack_queue[qp->s_tail_ack_queue].sent = 1;
  157. }
  158. bth0 = qp->s_ack_state << 24;
  159. bth2 = qp->s_ack_rdma_psn++ & IPATH_PSN_MASK;
  160. break;
  161. default:
  162. normal:
  163. /*
  164. * Send a regular ACK.
  165. * Set the s_ack_state so we wait until after sending
  166. * the ACK before setting s_ack_state to ACKNOWLEDGE
  167. * (see above).
  168. */
  169. qp->s_ack_state = OP(SEND_ONLY);
  170. qp->s_flags &= ~IPATH_S_ACK_PENDING;
  171. qp->s_cur_sge = NULL;
  172. if (qp->s_nak_state)
  173. ohdr->u.aeth =
  174. cpu_to_be32((qp->r_msn & IPATH_MSN_MASK) |
  175. (qp->s_nak_state <<
  176. IPATH_AETH_CREDIT_SHIFT));
  177. else
  178. ohdr->u.aeth = ipath_compute_aeth(qp);
  179. hwords++;
  180. len = 0;
  181. bth0 = OP(ACKNOWLEDGE) << 24;
  182. bth2 = qp->s_ack_psn & IPATH_PSN_MASK;
  183. }
  184. qp->s_hdrwords = hwords;
  185. qp->s_cur_size = len;
  186. ipath_make_ruc_header(dev, qp, ohdr, bth0, bth2);
  187. return 1;
  188. bail:
  189. return 0;
  190. }
  191. /**
  192. * ipath_make_rc_req - construct a request packet (SEND, RDMA r/w, ATOMIC)
  193. * @qp: a pointer to the QP
  194. *
  195. * Return 1 if constructed; otherwise, return 0.
  196. */
  197. int ipath_make_rc_req(struct ipath_qp *qp)
  198. {
  199. struct ipath_ibdev *dev = to_idev(qp->ibqp.device);
  200. struct ipath_other_headers *ohdr;
  201. struct ipath_sge_state *ss;
  202. struct ipath_swqe *wqe;
  203. u32 hwords;
  204. u32 len;
  205. u32 bth0;
  206. u32 bth2;
  207. u32 pmtu = ib_mtu_enum_to_int(qp->path_mtu);
  208. char newreq;
  209. unsigned long flags;
  210. int ret = 0;
  211. ohdr = &qp->s_hdr.u.oth;
  212. if (qp->remote_ah_attr.ah_flags & IB_AH_GRH)
  213. ohdr = &qp->s_hdr.u.l.oth;
  214. /*
  215. * The lock is needed to synchronize between the sending tasklet,
  216. * the receive interrupt handler, and timeout resends.
  217. */
  218. spin_lock_irqsave(&qp->s_lock, flags);
  219. /* Sending responses has higher priority over sending requests. */
  220. if ((qp->r_head_ack_queue != qp->s_tail_ack_queue ||
  221. (qp->s_flags & IPATH_S_ACK_PENDING) ||
  222. qp->s_ack_state != OP(ACKNOWLEDGE)) &&
  223. ipath_make_rc_ack(dev, qp, ohdr, pmtu))
  224. goto done;
  225. if (!(ib_ipath_state_ops[qp->state] & IPATH_PROCESS_SEND_OK)) {
  226. if (!(ib_ipath_state_ops[qp->state] & IPATH_FLUSH_SEND))
  227. goto bail;
  228. /* We are in the error state, flush the work request. */
  229. if (qp->s_last == qp->s_head)
  230. goto bail;
  231. /* If DMAs are in progress, we can't flush immediately. */
  232. if (atomic_read(&qp->s_dma_busy)) {
  233. qp->s_flags |= IPATH_S_WAIT_DMA;
  234. goto bail;
  235. }
  236. wqe = get_swqe_ptr(qp, qp->s_last);
  237. ipath_send_complete(qp, wqe, IB_WC_WR_FLUSH_ERR);
  238. goto done;
  239. }
  240. /* Leave BUSY set until RNR timeout. */
  241. if (qp->s_rnr_timeout) {
  242. qp->s_flags |= IPATH_S_WAITING;
  243. goto bail;
  244. }
  245. /* header size in 32-bit words LRH+BTH = (8+12)/4. */
  246. hwords = 5;
  247. bth0 = 1 << 22; /* Set M bit */
  248. /* Send a request. */
  249. wqe = get_swqe_ptr(qp, qp->s_cur);
  250. switch (qp->s_state) {
  251. default:
  252. if (!(ib_ipath_state_ops[qp->state] &
  253. IPATH_PROCESS_NEXT_SEND_OK))
  254. goto bail;
  255. /*
  256. * Resend an old request or start a new one.
  257. *
  258. * We keep track of the current SWQE so that
  259. * we don't reset the "furthest progress" state
  260. * if we need to back up.
  261. */
  262. newreq = 0;
  263. if (qp->s_cur == qp->s_tail) {
  264. /* Check if send work queue is empty. */
  265. if (qp->s_tail == qp->s_head)
  266. goto bail;
  267. /*
  268. * If a fence is requested, wait for previous
  269. * RDMA read and atomic operations to finish.
  270. */
  271. if ((wqe->wr.send_flags & IB_SEND_FENCE) &&
  272. qp->s_num_rd_atomic) {
  273. qp->s_flags |= IPATH_S_FENCE_PENDING;
  274. goto bail;
  275. }
  276. wqe->psn = qp->s_next_psn;
  277. newreq = 1;
  278. }
  279. /*
  280. * Note that we have to be careful not to modify the
  281. * original work request since we may need to resend
  282. * it.
  283. */
  284. len = wqe->length;
  285. ss = &qp->s_sge;
  286. bth2 = 0;
  287. switch (wqe->wr.opcode) {
  288. case IB_WR_SEND:
  289. case IB_WR_SEND_WITH_IMM:
  290. /* If no credit, return. */
  291. if (qp->s_lsn != (u32) -1 &&
  292. ipath_cmp24(wqe->ssn, qp->s_lsn + 1) > 0) {
  293. qp->s_flags |= IPATH_S_WAIT_SSN_CREDIT;
  294. goto bail;
  295. }
  296. wqe->lpsn = wqe->psn;
  297. if (len > pmtu) {
  298. wqe->lpsn += (len - 1) / pmtu;
  299. qp->s_state = OP(SEND_FIRST);
  300. len = pmtu;
  301. break;
  302. }
  303. if (wqe->wr.opcode == IB_WR_SEND)
  304. qp->s_state = OP(SEND_ONLY);
  305. else {
  306. qp->s_state = OP(SEND_ONLY_WITH_IMMEDIATE);
  307. /* Immediate data comes after the BTH */
  308. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  309. hwords += 1;
  310. }
  311. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  312. bth0 |= 1 << 23;
  313. bth2 = 1 << 31; /* Request ACK. */
  314. if (++qp->s_cur == qp->s_size)
  315. qp->s_cur = 0;
  316. break;
  317. case IB_WR_RDMA_WRITE:
  318. if (newreq && qp->s_lsn != (u32) -1)
  319. qp->s_lsn++;
  320. /* FALLTHROUGH */
  321. case IB_WR_RDMA_WRITE_WITH_IMM:
  322. /* If no credit, return. */
  323. if (qp->s_lsn != (u32) -1 &&
  324. ipath_cmp24(wqe->ssn, qp->s_lsn + 1) > 0) {
  325. qp->s_flags |= IPATH_S_WAIT_SSN_CREDIT;
  326. goto bail;
  327. }
  328. ohdr->u.rc.reth.vaddr =
  329. cpu_to_be64(wqe->wr.wr.rdma.remote_addr);
  330. ohdr->u.rc.reth.rkey =
  331. cpu_to_be32(wqe->wr.wr.rdma.rkey);
  332. ohdr->u.rc.reth.length = cpu_to_be32(len);
  333. hwords += sizeof(struct ib_reth) / sizeof(u32);
  334. wqe->lpsn = wqe->psn;
  335. if (len > pmtu) {
  336. wqe->lpsn += (len - 1) / pmtu;
  337. qp->s_state = OP(RDMA_WRITE_FIRST);
  338. len = pmtu;
  339. break;
  340. }
  341. if (wqe->wr.opcode == IB_WR_RDMA_WRITE)
  342. qp->s_state = OP(RDMA_WRITE_ONLY);
  343. else {
  344. qp->s_state =
  345. OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE);
  346. /* Immediate data comes after RETH */
  347. ohdr->u.rc.imm_data = wqe->wr.ex.imm_data;
  348. hwords += 1;
  349. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  350. bth0 |= 1 << 23;
  351. }
  352. bth2 = 1 << 31; /* Request ACK. */
  353. if (++qp->s_cur == qp->s_size)
  354. qp->s_cur = 0;
  355. break;
  356. case IB_WR_RDMA_READ:
  357. /*
  358. * Don't allow more operations to be started
  359. * than the QP limits allow.
  360. */
  361. if (newreq) {
  362. if (qp->s_num_rd_atomic >=
  363. qp->s_max_rd_atomic) {
  364. qp->s_flags |= IPATH_S_RDMAR_PENDING;
  365. goto bail;
  366. }
  367. qp->s_num_rd_atomic++;
  368. if (qp->s_lsn != (u32) -1)
  369. qp->s_lsn++;
  370. /*
  371. * Adjust s_next_psn to count the
  372. * expected number of responses.
  373. */
  374. if (len > pmtu)
  375. qp->s_next_psn += (len - 1) / pmtu;
  376. wqe->lpsn = qp->s_next_psn++;
  377. }
  378. ohdr->u.rc.reth.vaddr =
  379. cpu_to_be64(wqe->wr.wr.rdma.remote_addr);
  380. ohdr->u.rc.reth.rkey =
  381. cpu_to_be32(wqe->wr.wr.rdma.rkey);
  382. ohdr->u.rc.reth.length = cpu_to_be32(len);
  383. qp->s_state = OP(RDMA_READ_REQUEST);
  384. hwords += sizeof(ohdr->u.rc.reth) / sizeof(u32);
  385. ss = NULL;
  386. len = 0;
  387. if (++qp->s_cur == qp->s_size)
  388. qp->s_cur = 0;
  389. break;
  390. case IB_WR_ATOMIC_CMP_AND_SWP:
  391. case IB_WR_ATOMIC_FETCH_AND_ADD:
  392. /*
  393. * Don't allow more operations to be started
  394. * than the QP limits allow.
  395. */
  396. if (newreq) {
  397. if (qp->s_num_rd_atomic >=
  398. qp->s_max_rd_atomic) {
  399. qp->s_flags |= IPATH_S_RDMAR_PENDING;
  400. goto bail;
  401. }
  402. qp->s_num_rd_atomic++;
  403. if (qp->s_lsn != (u32) -1)
  404. qp->s_lsn++;
  405. wqe->lpsn = wqe->psn;
  406. }
  407. if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
  408. qp->s_state = OP(COMPARE_SWAP);
  409. ohdr->u.atomic_eth.swap_data = cpu_to_be64(
  410. wqe->wr.wr.atomic.swap);
  411. ohdr->u.atomic_eth.compare_data = cpu_to_be64(
  412. wqe->wr.wr.atomic.compare_add);
  413. } else {
  414. qp->s_state = OP(FETCH_ADD);
  415. ohdr->u.atomic_eth.swap_data = cpu_to_be64(
  416. wqe->wr.wr.atomic.compare_add);
  417. ohdr->u.atomic_eth.compare_data = 0;
  418. }
  419. ohdr->u.atomic_eth.vaddr[0] = cpu_to_be32(
  420. wqe->wr.wr.atomic.remote_addr >> 32);
  421. ohdr->u.atomic_eth.vaddr[1] = cpu_to_be32(
  422. wqe->wr.wr.atomic.remote_addr);
  423. ohdr->u.atomic_eth.rkey = cpu_to_be32(
  424. wqe->wr.wr.atomic.rkey);
  425. hwords += sizeof(struct ib_atomic_eth) / sizeof(u32);
  426. ss = NULL;
  427. len = 0;
  428. if (++qp->s_cur == qp->s_size)
  429. qp->s_cur = 0;
  430. break;
  431. default:
  432. goto bail;
  433. }
  434. qp->s_sge.sge = wqe->sg_list[0];
  435. qp->s_sge.sg_list = wqe->sg_list + 1;
  436. qp->s_sge.num_sge = wqe->wr.num_sge;
  437. qp->s_len = wqe->length;
  438. if (newreq) {
  439. qp->s_tail++;
  440. if (qp->s_tail >= qp->s_size)
  441. qp->s_tail = 0;
  442. }
  443. bth2 |= qp->s_psn & IPATH_PSN_MASK;
  444. if (wqe->wr.opcode == IB_WR_RDMA_READ)
  445. qp->s_psn = wqe->lpsn + 1;
  446. else {
  447. qp->s_psn++;
  448. if (ipath_cmp24(qp->s_psn, qp->s_next_psn) > 0)
  449. qp->s_next_psn = qp->s_psn;
  450. }
  451. /*
  452. * Put the QP on the pending list so lost ACKs will cause
  453. * a retry. More than one request can be pending so the
  454. * QP may already be on the dev->pending list.
  455. */
  456. spin_lock(&dev->pending_lock);
  457. if (list_empty(&qp->timerwait))
  458. list_add_tail(&qp->timerwait,
  459. &dev->pending[dev->pending_index]);
  460. spin_unlock(&dev->pending_lock);
  461. break;
  462. case OP(RDMA_READ_RESPONSE_FIRST):
  463. /*
  464. * This case can only happen if a send is restarted.
  465. * See ipath_restart_rc().
  466. */
  467. ipath_init_restart(qp, wqe);
  468. /* FALLTHROUGH */
  469. case OP(SEND_FIRST):
  470. qp->s_state = OP(SEND_MIDDLE);
  471. /* FALLTHROUGH */
  472. case OP(SEND_MIDDLE):
  473. bth2 = qp->s_psn++ & IPATH_PSN_MASK;
  474. if (ipath_cmp24(qp->s_psn, qp->s_next_psn) > 0)
  475. qp->s_next_psn = qp->s_psn;
  476. ss = &qp->s_sge;
  477. len = qp->s_len;
  478. if (len > pmtu) {
  479. len = pmtu;
  480. break;
  481. }
  482. if (wqe->wr.opcode == IB_WR_SEND)
  483. qp->s_state = OP(SEND_LAST);
  484. else {
  485. qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE);
  486. /* Immediate data comes after the BTH */
  487. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  488. hwords += 1;
  489. }
  490. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  491. bth0 |= 1 << 23;
  492. bth2 |= 1 << 31; /* Request ACK. */
  493. qp->s_cur++;
  494. if (qp->s_cur >= qp->s_size)
  495. qp->s_cur = 0;
  496. break;
  497. case OP(RDMA_READ_RESPONSE_LAST):
  498. /*
  499. * This case can only happen if a RDMA write is restarted.
  500. * See ipath_restart_rc().
  501. */
  502. ipath_init_restart(qp, wqe);
  503. /* FALLTHROUGH */
  504. case OP(RDMA_WRITE_FIRST):
  505. qp->s_state = OP(RDMA_WRITE_MIDDLE);
  506. /* FALLTHROUGH */
  507. case OP(RDMA_WRITE_MIDDLE):
  508. bth2 = qp->s_psn++ & IPATH_PSN_MASK;
  509. if (ipath_cmp24(qp->s_psn, qp->s_next_psn) > 0)
  510. qp->s_next_psn = qp->s_psn;
  511. ss = &qp->s_sge;
  512. len = qp->s_len;
  513. if (len > pmtu) {
  514. len = pmtu;
  515. break;
  516. }
  517. if (wqe->wr.opcode == IB_WR_RDMA_WRITE)
  518. qp->s_state = OP(RDMA_WRITE_LAST);
  519. else {
  520. qp->s_state = OP(RDMA_WRITE_LAST_WITH_IMMEDIATE);
  521. /* Immediate data comes after the BTH */
  522. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  523. hwords += 1;
  524. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  525. bth0 |= 1 << 23;
  526. }
  527. bth2 |= 1 << 31; /* Request ACK. */
  528. qp->s_cur++;
  529. if (qp->s_cur >= qp->s_size)
  530. qp->s_cur = 0;
  531. break;
  532. case OP(RDMA_READ_RESPONSE_MIDDLE):
  533. /*
  534. * This case can only happen if a RDMA read is restarted.
  535. * See ipath_restart_rc().
  536. */
  537. ipath_init_restart(qp, wqe);
  538. len = ((qp->s_psn - wqe->psn) & IPATH_PSN_MASK) * pmtu;
  539. ohdr->u.rc.reth.vaddr =
  540. cpu_to_be64(wqe->wr.wr.rdma.remote_addr + len);
  541. ohdr->u.rc.reth.rkey =
  542. cpu_to_be32(wqe->wr.wr.rdma.rkey);
  543. ohdr->u.rc.reth.length = cpu_to_be32(qp->s_len);
  544. qp->s_state = OP(RDMA_READ_REQUEST);
  545. hwords += sizeof(ohdr->u.rc.reth) / sizeof(u32);
  546. bth2 = qp->s_psn++ & IPATH_PSN_MASK;
  547. if (ipath_cmp24(qp->s_psn, qp->s_next_psn) > 0)
  548. qp->s_next_psn = qp->s_psn;
  549. ss = NULL;
  550. len = 0;
  551. qp->s_cur++;
  552. if (qp->s_cur == qp->s_size)
  553. qp->s_cur = 0;
  554. break;
  555. }
  556. if (ipath_cmp24(qp->s_psn, qp->s_last_psn + IPATH_PSN_CREDIT - 1) >= 0)
  557. bth2 |= 1 << 31; /* Request ACK. */
  558. qp->s_len -= len;
  559. qp->s_hdrwords = hwords;
  560. qp->s_cur_sge = ss;
  561. qp->s_cur_size = len;
  562. ipath_make_ruc_header(dev, qp, ohdr, bth0 | (qp->s_state << 24), bth2);
  563. done:
  564. ret = 1;
  565. goto unlock;
  566. bail:
  567. qp->s_flags &= ~IPATH_S_BUSY;
  568. unlock:
  569. spin_unlock_irqrestore(&qp->s_lock, flags);
  570. return ret;
  571. }
  572. /**
  573. * send_rc_ack - Construct an ACK packet and send it
  574. * @qp: a pointer to the QP
  575. *
  576. * This is called from ipath_rc_rcv() and only uses the receive
  577. * side QP state.
  578. * Note that RDMA reads and atomics are handled in the
  579. * send side QP state and tasklet.
  580. */
  581. static void send_rc_ack(struct ipath_qp *qp)
  582. {
  583. struct ipath_ibdev *dev = to_idev(qp->ibqp.device);
  584. struct ipath_devdata *dd;
  585. u16 lrh0;
  586. u32 bth0;
  587. u32 hwords;
  588. u32 __iomem *piobuf;
  589. struct ipath_ib_header hdr;
  590. struct ipath_other_headers *ohdr;
  591. unsigned long flags;
  592. spin_lock_irqsave(&qp->s_lock, flags);
  593. /* Don't send ACK or NAK if a RDMA read or atomic is pending. */
  594. if (qp->r_head_ack_queue != qp->s_tail_ack_queue ||
  595. (qp->s_flags & IPATH_S_ACK_PENDING) ||
  596. qp->s_ack_state != OP(ACKNOWLEDGE))
  597. goto queue_ack;
  598. spin_unlock_irqrestore(&qp->s_lock, flags);
  599. /* Don't try to send ACKs if the link isn't ACTIVE */
  600. dd = dev->dd;
  601. if (!(dd->ipath_flags & IPATH_LINKACTIVE))
  602. goto done;
  603. piobuf = ipath_getpiobuf(dd, 0, NULL);
  604. if (!piobuf) {
  605. /*
  606. * We are out of PIO buffers at the moment.
  607. * Pass responsibility for sending the ACK to the
  608. * send tasklet so that when a PIO buffer becomes
  609. * available, the ACK is sent ahead of other outgoing
  610. * packets.
  611. */
  612. spin_lock_irqsave(&qp->s_lock, flags);
  613. goto queue_ack;
  614. }
  615. /* Construct the header. */
  616. ohdr = &hdr.u.oth;
  617. lrh0 = IPATH_LRH_BTH;
  618. /* header size in 32-bit words LRH+BTH+AETH = (8+12+4)/4. */
  619. hwords = 6;
  620. if (unlikely(qp->remote_ah_attr.ah_flags & IB_AH_GRH)) {
  621. hwords += ipath_make_grh(dev, &hdr.u.l.grh,
  622. &qp->remote_ah_attr.grh,
  623. hwords, 0);
  624. ohdr = &hdr.u.l.oth;
  625. lrh0 = IPATH_LRH_GRH;
  626. }
  627. /* read pkey_index w/o lock (its atomic) */
  628. bth0 = ipath_get_pkey(dd, qp->s_pkey_index) |
  629. (OP(ACKNOWLEDGE) << 24) | (1 << 22);
  630. if (qp->r_nak_state)
  631. ohdr->u.aeth = cpu_to_be32((qp->r_msn & IPATH_MSN_MASK) |
  632. (qp->r_nak_state <<
  633. IPATH_AETH_CREDIT_SHIFT));
  634. else
  635. ohdr->u.aeth = ipath_compute_aeth(qp);
  636. lrh0 |= qp->remote_ah_attr.sl << 4;
  637. hdr.lrh[0] = cpu_to_be16(lrh0);
  638. hdr.lrh[1] = cpu_to_be16(qp->remote_ah_attr.dlid);
  639. hdr.lrh[2] = cpu_to_be16(hwords + SIZE_OF_CRC);
  640. hdr.lrh[3] = cpu_to_be16(dd->ipath_lid |
  641. qp->remote_ah_attr.src_path_bits);
  642. ohdr->bth[0] = cpu_to_be32(bth0);
  643. ohdr->bth[1] = cpu_to_be32(qp->remote_qpn);
  644. ohdr->bth[2] = cpu_to_be32(qp->r_ack_psn & IPATH_PSN_MASK);
  645. writeq(hwords + 1, piobuf);
  646. if (dd->ipath_flags & IPATH_PIO_FLUSH_WC) {
  647. u32 *hdrp = (u32 *) &hdr;
  648. ipath_flush_wc();
  649. __iowrite32_copy(piobuf + 2, hdrp, hwords - 1);
  650. ipath_flush_wc();
  651. __raw_writel(hdrp[hwords - 1], piobuf + hwords + 1);
  652. } else
  653. __iowrite32_copy(piobuf + 2, (u32 *) &hdr, hwords);
  654. ipath_flush_wc();
  655. dev->n_unicast_xmit++;
  656. goto done;
  657. queue_ack:
  658. if (ib_ipath_state_ops[qp->state] & IPATH_PROCESS_RECV_OK) {
  659. dev->n_rc_qacks++;
  660. qp->s_flags |= IPATH_S_ACK_PENDING;
  661. qp->s_nak_state = qp->r_nak_state;
  662. qp->s_ack_psn = qp->r_ack_psn;
  663. /* Schedule the send tasklet. */
  664. ipath_schedule_send(qp);
  665. }
  666. spin_unlock_irqrestore(&qp->s_lock, flags);
  667. done:
  668. return;
  669. }
  670. /**
  671. * reset_psn - reset the QP state to send starting from PSN
  672. * @qp: the QP
  673. * @psn: the packet sequence number to restart at
  674. *
  675. * This is called from ipath_rc_rcv() to process an incoming RC ACK
  676. * for the given QP.
  677. * Called at interrupt level with the QP s_lock held.
  678. */
  679. static void reset_psn(struct ipath_qp *qp, u32 psn)
  680. {
  681. u32 n = qp->s_last;
  682. struct ipath_swqe *wqe = get_swqe_ptr(qp, n);
  683. u32 opcode;
  684. qp->s_cur = n;
  685. /*
  686. * If we are starting the request from the beginning,
  687. * let the normal send code handle initialization.
  688. */
  689. if (ipath_cmp24(psn, wqe->psn) <= 0) {
  690. qp->s_state = OP(SEND_LAST);
  691. goto done;
  692. }
  693. /* Find the work request opcode corresponding to the given PSN. */
  694. opcode = wqe->wr.opcode;
  695. for (;;) {
  696. int diff;
  697. if (++n == qp->s_size)
  698. n = 0;
  699. if (n == qp->s_tail)
  700. break;
  701. wqe = get_swqe_ptr(qp, n);
  702. diff = ipath_cmp24(psn, wqe->psn);
  703. if (diff < 0)
  704. break;
  705. qp->s_cur = n;
  706. /*
  707. * If we are starting the request from the beginning,
  708. * let the normal send code handle initialization.
  709. */
  710. if (diff == 0) {
  711. qp->s_state = OP(SEND_LAST);
  712. goto done;
  713. }
  714. opcode = wqe->wr.opcode;
  715. }
  716. /*
  717. * Set the state to restart in the middle of a request.
  718. * Don't change the s_sge, s_cur_sge, or s_cur_size.
  719. * See ipath_make_rc_req().
  720. */
  721. switch (opcode) {
  722. case IB_WR_SEND:
  723. case IB_WR_SEND_WITH_IMM:
  724. qp->s_state = OP(RDMA_READ_RESPONSE_FIRST);
  725. break;
  726. case IB_WR_RDMA_WRITE:
  727. case IB_WR_RDMA_WRITE_WITH_IMM:
  728. qp->s_state = OP(RDMA_READ_RESPONSE_LAST);
  729. break;
  730. case IB_WR_RDMA_READ:
  731. qp->s_state = OP(RDMA_READ_RESPONSE_MIDDLE);
  732. break;
  733. default:
  734. /*
  735. * This case shouldn't happen since its only
  736. * one PSN per req.
  737. */
  738. qp->s_state = OP(SEND_LAST);
  739. }
  740. done:
  741. qp->s_psn = psn;
  742. }
  743. /**
  744. * ipath_restart_rc - back up requester to resend the last un-ACKed request
  745. * @qp: the QP to restart
  746. * @psn: packet sequence number for the request
  747. * @wc: the work completion request
  748. *
  749. * The QP s_lock should be held and interrupts disabled.
  750. */
  751. void ipath_restart_rc(struct ipath_qp *qp, u32 psn)
  752. {
  753. struct ipath_swqe *wqe = get_swqe_ptr(qp, qp->s_last);
  754. struct ipath_ibdev *dev;
  755. if (qp->s_retry == 0) {
  756. ipath_send_complete(qp, wqe, IB_WC_RETRY_EXC_ERR);
  757. ipath_error_qp(qp, IB_WC_WR_FLUSH_ERR);
  758. goto bail;
  759. }
  760. qp->s_retry--;
  761. /*
  762. * Remove the QP from the timeout queue.
  763. * Note: it may already have been removed by ipath_ib_timer().
  764. */
  765. dev = to_idev(qp->ibqp.device);
  766. spin_lock(&dev->pending_lock);
  767. if (!list_empty(&qp->timerwait))
  768. list_del_init(&qp->timerwait);
  769. if (!list_empty(&qp->piowait))
  770. list_del_init(&qp->piowait);
  771. spin_unlock(&dev->pending_lock);
  772. if (wqe->wr.opcode == IB_WR_RDMA_READ)
  773. dev->n_rc_resends++;
  774. else
  775. dev->n_rc_resends += (qp->s_psn - psn) & IPATH_PSN_MASK;
  776. reset_psn(qp, psn);
  777. ipath_schedule_send(qp);
  778. bail:
  779. return;
  780. }
  781. static inline void update_last_psn(struct ipath_qp *qp, u32 psn)
  782. {
  783. qp->s_last_psn = psn;
  784. }
  785. /**
  786. * do_rc_ack - process an incoming RC ACK
  787. * @qp: the QP the ACK came in on
  788. * @psn: the packet sequence number of the ACK
  789. * @opcode: the opcode of the request that resulted in the ACK
  790. *
  791. * This is called from ipath_rc_rcv_resp() to process an incoming RC ACK
  792. * for the given QP.
  793. * Called at interrupt level with the QP s_lock held and interrupts disabled.
  794. * Returns 1 if OK, 0 if current operation should be aborted (NAK).
  795. */
  796. static int do_rc_ack(struct ipath_qp *qp, u32 aeth, u32 psn, int opcode,
  797. u64 val)
  798. {
  799. struct ipath_ibdev *dev = to_idev(qp->ibqp.device);
  800. struct ib_wc wc;
  801. enum ib_wc_status status;
  802. struct ipath_swqe *wqe;
  803. int ret = 0;
  804. u32 ack_psn;
  805. int diff;
  806. /*
  807. * Remove the QP from the timeout queue (or RNR timeout queue).
  808. * If ipath_ib_timer() has already removed it,
  809. * it's OK since we hold the QP s_lock and ipath_restart_rc()
  810. * just won't find anything to restart if we ACK everything.
  811. */
  812. spin_lock(&dev->pending_lock);
  813. if (!list_empty(&qp->timerwait))
  814. list_del_init(&qp->timerwait);
  815. spin_unlock(&dev->pending_lock);
  816. /*
  817. * Note that NAKs implicitly ACK outstanding SEND and RDMA write
  818. * requests and implicitly NAK RDMA read and atomic requests issued
  819. * before the NAK'ed request. The MSN won't include the NAK'ed
  820. * request but will include an ACK'ed request(s).
  821. */
  822. ack_psn = psn;
  823. if (aeth >> 29)
  824. ack_psn--;
  825. wqe = get_swqe_ptr(qp, qp->s_last);
  826. /*
  827. * The MSN might be for a later WQE than the PSN indicates so
  828. * only complete WQEs that the PSN finishes.
  829. */
  830. while ((diff = ipath_cmp24(ack_psn, wqe->lpsn)) >= 0) {
  831. /*
  832. * RDMA_READ_RESPONSE_ONLY is a special case since
  833. * we want to generate completion events for everything
  834. * before the RDMA read, copy the data, then generate
  835. * the completion for the read.
  836. */
  837. if (wqe->wr.opcode == IB_WR_RDMA_READ &&
  838. opcode == OP(RDMA_READ_RESPONSE_ONLY) &&
  839. diff == 0) {
  840. ret = 1;
  841. goto bail;
  842. }
  843. /*
  844. * If this request is a RDMA read or atomic, and the ACK is
  845. * for a later operation, this ACK NAKs the RDMA read or
  846. * atomic. In other words, only a RDMA_READ_LAST or ONLY
  847. * can ACK a RDMA read and likewise for atomic ops. Note
  848. * that the NAK case can only happen if relaxed ordering is
  849. * used and requests are sent after an RDMA read or atomic
  850. * is sent but before the response is received.
  851. */
  852. if ((wqe->wr.opcode == IB_WR_RDMA_READ &&
  853. (opcode != OP(RDMA_READ_RESPONSE_LAST) || diff != 0)) ||
  854. ((wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
  855. wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD) &&
  856. (opcode != OP(ATOMIC_ACKNOWLEDGE) || diff != 0))) {
  857. /*
  858. * The last valid PSN seen is the previous
  859. * request's.
  860. */
  861. update_last_psn(qp, wqe->psn - 1);
  862. /* Retry this request. */
  863. ipath_restart_rc(qp, wqe->psn);
  864. /*
  865. * No need to process the ACK/NAK since we are
  866. * restarting an earlier request.
  867. */
  868. goto bail;
  869. }
  870. if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
  871. wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
  872. *(u64 *) wqe->sg_list[0].vaddr = val;
  873. if (qp->s_num_rd_atomic &&
  874. (wqe->wr.opcode == IB_WR_RDMA_READ ||
  875. wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
  876. wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD)) {
  877. qp->s_num_rd_atomic--;
  878. /* Restart sending task if fence is complete */
  879. if (((qp->s_flags & IPATH_S_FENCE_PENDING) &&
  880. !qp->s_num_rd_atomic) ||
  881. qp->s_flags & IPATH_S_RDMAR_PENDING)
  882. ipath_schedule_send(qp);
  883. }
  884. /* Post a send completion queue entry if requested. */
  885. if (!(qp->s_flags & IPATH_S_SIGNAL_REQ_WR) ||
  886. (wqe->wr.send_flags & IB_SEND_SIGNALED)) {
  887. memset(&wc, 0, sizeof wc);
  888. wc.wr_id = wqe->wr.wr_id;
  889. wc.status = IB_WC_SUCCESS;
  890. wc.opcode = ib_ipath_wc_opcode[wqe->wr.opcode];
  891. wc.byte_len = wqe->length;
  892. wc.qp = &qp->ibqp;
  893. wc.src_qp = qp->remote_qpn;
  894. wc.slid = qp->remote_ah_attr.dlid;
  895. wc.sl = qp->remote_ah_attr.sl;
  896. ipath_cq_enter(to_icq(qp->ibqp.send_cq), &wc, 0);
  897. }
  898. qp->s_retry = qp->s_retry_cnt;
  899. /*
  900. * If we are completing a request which is in the process of
  901. * being resent, we can stop resending it since we know the
  902. * responder has already seen it.
  903. */
  904. if (qp->s_last == qp->s_cur) {
  905. if (++qp->s_cur >= qp->s_size)
  906. qp->s_cur = 0;
  907. qp->s_last = qp->s_cur;
  908. if (qp->s_last == qp->s_tail)
  909. break;
  910. wqe = get_swqe_ptr(qp, qp->s_cur);
  911. qp->s_state = OP(SEND_LAST);
  912. qp->s_psn = wqe->psn;
  913. } else {
  914. if (++qp->s_last >= qp->s_size)
  915. qp->s_last = 0;
  916. if (qp->state == IB_QPS_SQD && qp->s_last == qp->s_cur)
  917. qp->s_draining = 0;
  918. if (qp->s_last == qp->s_tail)
  919. break;
  920. wqe = get_swqe_ptr(qp, qp->s_last);
  921. }
  922. }
  923. switch (aeth >> 29) {
  924. case 0: /* ACK */
  925. dev->n_rc_acks++;
  926. /* If this is a partial ACK, reset the retransmit timer. */
  927. if (qp->s_last != qp->s_tail) {
  928. spin_lock(&dev->pending_lock);
  929. if (list_empty(&qp->timerwait))
  930. list_add_tail(&qp->timerwait,
  931. &dev->pending[dev->pending_index]);
  932. spin_unlock(&dev->pending_lock);
  933. /*
  934. * If we get a partial ACK for a resent operation,
  935. * we can stop resending the earlier packets and
  936. * continue with the next packet the receiver wants.
  937. */
  938. if (ipath_cmp24(qp->s_psn, psn) <= 0) {
  939. reset_psn(qp, psn + 1);
  940. ipath_schedule_send(qp);
  941. }
  942. } else if (ipath_cmp24(qp->s_psn, psn) <= 0) {
  943. qp->s_state = OP(SEND_LAST);
  944. qp->s_psn = psn + 1;
  945. }
  946. ipath_get_credit(qp, aeth);
  947. qp->s_rnr_retry = qp->s_rnr_retry_cnt;
  948. qp->s_retry = qp->s_retry_cnt;
  949. update_last_psn(qp, psn);
  950. ret = 1;
  951. goto bail;
  952. case 1: /* RNR NAK */
  953. dev->n_rnr_naks++;
  954. if (qp->s_last == qp->s_tail)
  955. goto bail;
  956. if (qp->s_rnr_retry == 0) {
  957. status = IB_WC_RNR_RETRY_EXC_ERR;
  958. goto class_b;
  959. }
  960. if (qp->s_rnr_retry_cnt < 7)
  961. qp->s_rnr_retry--;
  962. /* The last valid PSN is the previous PSN. */
  963. update_last_psn(qp, psn - 1);
  964. if (wqe->wr.opcode == IB_WR_RDMA_READ)
  965. dev->n_rc_resends++;
  966. else
  967. dev->n_rc_resends +=
  968. (qp->s_psn - psn) & IPATH_PSN_MASK;
  969. reset_psn(qp, psn);
  970. qp->s_rnr_timeout =
  971. ib_ipath_rnr_table[(aeth >> IPATH_AETH_CREDIT_SHIFT) &
  972. IPATH_AETH_CREDIT_MASK];
  973. ipath_insert_rnr_queue(qp);
  974. ipath_schedule_send(qp);
  975. goto bail;
  976. case 3: /* NAK */
  977. if (qp->s_last == qp->s_tail)
  978. goto bail;
  979. /* The last valid PSN is the previous PSN. */
  980. update_last_psn(qp, psn - 1);
  981. switch ((aeth >> IPATH_AETH_CREDIT_SHIFT) &
  982. IPATH_AETH_CREDIT_MASK) {
  983. case 0: /* PSN sequence error */
  984. dev->n_seq_naks++;
  985. /*
  986. * Back up to the responder's expected PSN.
  987. * Note that we might get a NAK in the middle of an
  988. * RDMA READ response which terminates the RDMA
  989. * READ.
  990. */
  991. ipath_restart_rc(qp, psn);
  992. break;
  993. case 1: /* Invalid Request */
  994. status = IB_WC_REM_INV_REQ_ERR;
  995. dev->n_other_naks++;
  996. goto class_b;
  997. case 2: /* Remote Access Error */
  998. status = IB_WC_REM_ACCESS_ERR;
  999. dev->n_other_naks++;
  1000. goto class_b;
  1001. case 3: /* Remote Operation Error */
  1002. status = IB_WC_REM_OP_ERR;
  1003. dev->n_other_naks++;
  1004. class_b:
  1005. ipath_send_complete(qp, wqe, status);
  1006. ipath_error_qp(qp, IB_WC_WR_FLUSH_ERR);
  1007. break;
  1008. default:
  1009. /* Ignore other reserved NAK error codes */
  1010. goto reserved;
  1011. }
  1012. qp->s_rnr_retry = qp->s_rnr_retry_cnt;
  1013. goto bail;
  1014. default: /* 2: reserved */
  1015. reserved:
  1016. /* Ignore reserved NAK codes. */
  1017. goto bail;
  1018. }
  1019. bail:
  1020. return ret;
  1021. }
  1022. /**
  1023. * ipath_rc_rcv_resp - process an incoming RC response packet
  1024. * @dev: the device this packet came in on
  1025. * @ohdr: the other headers for this packet
  1026. * @data: the packet data
  1027. * @tlen: the packet length
  1028. * @qp: the QP for this packet
  1029. * @opcode: the opcode for this packet
  1030. * @psn: the packet sequence number for this packet
  1031. * @hdrsize: the header length
  1032. * @pmtu: the path MTU
  1033. * @header_in_data: true if part of the header data is in the data buffer
  1034. *
  1035. * This is called from ipath_rc_rcv() to process an incoming RC response
  1036. * packet for the given QP.
  1037. * Called at interrupt level.
  1038. */
  1039. static inline void ipath_rc_rcv_resp(struct ipath_ibdev *dev,
  1040. struct ipath_other_headers *ohdr,
  1041. void *data, u32 tlen,
  1042. struct ipath_qp *qp,
  1043. u32 opcode,
  1044. u32 psn, u32 hdrsize, u32 pmtu,
  1045. int header_in_data)
  1046. {
  1047. struct ipath_swqe *wqe;
  1048. enum ib_wc_status status;
  1049. unsigned long flags;
  1050. int diff;
  1051. u32 pad;
  1052. u32 aeth;
  1053. u64 val;
  1054. spin_lock_irqsave(&qp->s_lock, flags);
  1055. /* Double check we can process this now that we hold the s_lock. */
  1056. if (!(ib_ipath_state_ops[qp->state] & IPATH_PROCESS_RECV_OK))
  1057. goto ack_done;
  1058. /* Ignore invalid responses. */
  1059. if (ipath_cmp24(psn, qp->s_next_psn) >= 0)
  1060. goto ack_done;
  1061. /* Ignore duplicate responses. */
  1062. diff = ipath_cmp24(psn, qp->s_last_psn);
  1063. if (unlikely(diff <= 0)) {
  1064. /* Update credits for "ghost" ACKs */
  1065. if (diff == 0 && opcode == OP(ACKNOWLEDGE)) {
  1066. if (!header_in_data)
  1067. aeth = be32_to_cpu(ohdr->u.aeth);
  1068. else {
  1069. aeth = be32_to_cpu(((__be32 *) data)[0]);
  1070. data += sizeof(__be32);
  1071. }
  1072. if ((aeth >> 29) == 0)
  1073. ipath_get_credit(qp, aeth);
  1074. }
  1075. goto ack_done;
  1076. }
  1077. if (unlikely(qp->s_last == qp->s_tail))
  1078. goto ack_done;
  1079. wqe = get_swqe_ptr(qp, qp->s_last);
  1080. status = IB_WC_SUCCESS;
  1081. switch (opcode) {
  1082. case OP(ACKNOWLEDGE):
  1083. case OP(ATOMIC_ACKNOWLEDGE):
  1084. case OP(RDMA_READ_RESPONSE_FIRST):
  1085. if (!header_in_data)
  1086. aeth = be32_to_cpu(ohdr->u.aeth);
  1087. else {
  1088. aeth = be32_to_cpu(((__be32 *) data)[0]);
  1089. data += sizeof(__be32);
  1090. }
  1091. if (opcode == OP(ATOMIC_ACKNOWLEDGE)) {
  1092. if (!header_in_data) {
  1093. __be32 *p = ohdr->u.at.atomic_ack_eth;
  1094. val = ((u64) be32_to_cpu(p[0]) << 32) |
  1095. be32_to_cpu(p[1]);
  1096. } else
  1097. val = be64_to_cpu(((__be64 *) data)[0]);
  1098. } else
  1099. val = 0;
  1100. if (!do_rc_ack(qp, aeth, psn, opcode, val) ||
  1101. opcode != OP(RDMA_READ_RESPONSE_FIRST))
  1102. goto ack_done;
  1103. hdrsize += 4;
  1104. wqe = get_swqe_ptr(qp, qp->s_last);
  1105. if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
  1106. goto ack_op_err;
  1107. qp->r_flags &= ~IPATH_R_RDMAR_SEQ;
  1108. /*
  1109. * If this is a response to a resent RDMA read, we
  1110. * have to be careful to copy the data to the right
  1111. * location.
  1112. */
  1113. qp->s_rdma_read_len = restart_sge(&qp->s_rdma_read_sge,
  1114. wqe, psn, pmtu);
  1115. goto read_middle;
  1116. case OP(RDMA_READ_RESPONSE_MIDDLE):
  1117. /* no AETH, no ACK */
  1118. if (unlikely(ipath_cmp24(psn, qp->s_last_psn + 1))) {
  1119. dev->n_rdma_seq++;
  1120. if (qp->r_flags & IPATH_R_RDMAR_SEQ)
  1121. goto ack_done;
  1122. qp->r_flags |= IPATH_R_RDMAR_SEQ;
  1123. ipath_restart_rc(qp, qp->s_last_psn + 1);
  1124. goto ack_done;
  1125. }
  1126. if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
  1127. goto ack_op_err;
  1128. read_middle:
  1129. if (unlikely(tlen != (hdrsize + pmtu + 4)))
  1130. goto ack_len_err;
  1131. if (unlikely(pmtu >= qp->s_rdma_read_len))
  1132. goto ack_len_err;
  1133. /* We got a response so update the timeout. */
  1134. spin_lock(&dev->pending_lock);
  1135. if (qp->s_rnr_timeout == 0 && !list_empty(&qp->timerwait))
  1136. list_move_tail(&qp->timerwait,
  1137. &dev->pending[dev->pending_index]);
  1138. spin_unlock(&dev->pending_lock);
  1139. if (opcode == OP(RDMA_READ_RESPONSE_MIDDLE))
  1140. qp->s_retry = qp->s_retry_cnt;
  1141. /*
  1142. * Update the RDMA receive state but do the copy w/o
  1143. * holding the locks and blocking interrupts.
  1144. */
  1145. qp->s_rdma_read_len -= pmtu;
  1146. update_last_psn(qp, psn);
  1147. spin_unlock_irqrestore(&qp->s_lock, flags);
  1148. ipath_copy_sge(&qp->s_rdma_read_sge, data, pmtu);
  1149. goto bail;
  1150. case OP(RDMA_READ_RESPONSE_ONLY):
  1151. if (!header_in_data)
  1152. aeth = be32_to_cpu(ohdr->u.aeth);
  1153. else
  1154. aeth = be32_to_cpu(((__be32 *) data)[0]);
  1155. if (!do_rc_ack(qp, aeth, psn, opcode, 0))
  1156. goto ack_done;
  1157. /* Get the number of bytes the message was padded by. */
  1158. pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3;
  1159. /*
  1160. * Check that the data size is >= 0 && <= pmtu.
  1161. * Remember to account for the AETH header (4) and
  1162. * ICRC (4).
  1163. */
  1164. if (unlikely(tlen < (hdrsize + pad + 8)))
  1165. goto ack_len_err;
  1166. /*
  1167. * If this is a response to a resent RDMA read, we
  1168. * have to be careful to copy the data to the right
  1169. * location.
  1170. */
  1171. wqe = get_swqe_ptr(qp, qp->s_last);
  1172. qp->s_rdma_read_len = restart_sge(&qp->s_rdma_read_sge,
  1173. wqe, psn, pmtu);
  1174. goto read_last;
  1175. case OP(RDMA_READ_RESPONSE_LAST):
  1176. /* ACKs READ req. */
  1177. if (unlikely(ipath_cmp24(psn, qp->s_last_psn + 1))) {
  1178. dev->n_rdma_seq++;
  1179. if (qp->r_flags & IPATH_R_RDMAR_SEQ)
  1180. goto ack_done;
  1181. qp->r_flags |= IPATH_R_RDMAR_SEQ;
  1182. ipath_restart_rc(qp, qp->s_last_psn + 1);
  1183. goto ack_done;
  1184. }
  1185. if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
  1186. goto ack_op_err;
  1187. /* Get the number of bytes the message was padded by. */
  1188. pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3;
  1189. /*
  1190. * Check that the data size is >= 1 && <= pmtu.
  1191. * Remember to account for the AETH header (4) and
  1192. * ICRC (4).
  1193. */
  1194. if (unlikely(tlen <= (hdrsize + pad + 8)))
  1195. goto ack_len_err;
  1196. read_last:
  1197. tlen -= hdrsize + pad + 8;
  1198. if (unlikely(tlen != qp->s_rdma_read_len))
  1199. goto ack_len_err;
  1200. if (!header_in_data)
  1201. aeth = be32_to_cpu(ohdr->u.aeth);
  1202. else {
  1203. aeth = be32_to_cpu(((__be32 *) data)[0]);
  1204. data += sizeof(__be32);
  1205. }
  1206. ipath_copy_sge(&qp->s_rdma_read_sge, data, tlen);
  1207. (void) do_rc_ack(qp, aeth, psn,
  1208. OP(RDMA_READ_RESPONSE_LAST), 0);
  1209. goto ack_done;
  1210. }
  1211. ack_op_err:
  1212. status = IB_WC_LOC_QP_OP_ERR;
  1213. goto ack_err;
  1214. ack_len_err:
  1215. status = IB_WC_LOC_LEN_ERR;
  1216. ack_err:
  1217. ipath_send_complete(qp, wqe, status);
  1218. ipath_error_qp(qp, IB_WC_WR_FLUSH_ERR);
  1219. ack_done:
  1220. spin_unlock_irqrestore(&qp->s_lock, flags);
  1221. bail:
  1222. return;
  1223. }
  1224. /**
  1225. * ipath_rc_rcv_error - process an incoming duplicate or error RC packet
  1226. * @dev: the device this packet came in on
  1227. * @ohdr: the other headers for this packet
  1228. * @data: the packet data
  1229. * @qp: the QP for this packet
  1230. * @opcode: the opcode for this packet
  1231. * @psn: the packet sequence number for this packet
  1232. * @diff: the difference between the PSN and the expected PSN
  1233. * @header_in_data: true if part of the header data is in the data buffer
  1234. *
  1235. * This is called from ipath_rc_rcv() to process an unexpected
  1236. * incoming RC packet for the given QP.
  1237. * Called at interrupt level.
  1238. * Return 1 if no more processing is needed; otherwise return 0 to
  1239. * schedule a response to be sent.
  1240. */
  1241. static inline int ipath_rc_rcv_error(struct ipath_ibdev *dev,
  1242. struct ipath_other_headers *ohdr,
  1243. void *data,
  1244. struct ipath_qp *qp,
  1245. u32 opcode,
  1246. u32 psn,
  1247. int diff,
  1248. int header_in_data)
  1249. {
  1250. struct ipath_ack_entry *e;
  1251. u8 i, prev;
  1252. int old_req;
  1253. unsigned long flags;
  1254. if (diff > 0) {
  1255. /*
  1256. * Packet sequence error.
  1257. * A NAK will ACK earlier sends and RDMA writes.
  1258. * Don't queue the NAK if we already sent one.
  1259. */
  1260. if (!qp->r_nak_state) {
  1261. qp->r_nak_state = IB_NAK_PSN_ERROR;
  1262. /* Use the expected PSN. */
  1263. qp->r_ack_psn = qp->r_psn;
  1264. goto send_ack;
  1265. }
  1266. goto done;
  1267. }
  1268. /*
  1269. * Handle a duplicate request. Don't re-execute SEND, RDMA
  1270. * write or atomic op. Don't NAK errors, just silently drop
  1271. * the duplicate request. Note that r_sge, r_len, and
  1272. * r_rcv_len may be in use so don't modify them.
  1273. *
  1274. * We are supposed to ACK the earliest duplicate PSN but we
  1275. * can coalesce an outstanding duplicate ACK. We have to
  1276. * send the earliest so that RDMA reads can be restarted at
  1277. * the requester's expected PSN.
  1278. *
  1279. * First, find where this duplicate PSN falls within the
  1280. * ACKs previously sent.
  1281. */
  1282. psn &= IPATH_PSN_MASK;
  1283. e = NULL;
  1284. old_req = 1;
  1285. spin_lock_irqsave(&qp->s_lock, flags);
  1286. /* Double check we can process this now that we hold the s_lock. */
  1287. if (!(ib_ipath_state_ops[qp->state] & IPATH_PROCESS_RECV_OK))
  1288. goto unlock_done;
  1289. for (i = qp->r_head_ack_queue; ; i = prev) {
  1290. if (i == qp->s_tail_ack_queue)
  1291. old_req = 0;
  1292. if (i)
  1293. prev = i - 1;
  1294. else
  1295. prev = IPATH_MAX_RDMA_ATOMIC;
  1296. if (prev == qp->r_head_ack_queue) {
  1297. e = NULL;
  1298. break;
  1299. }
  1300. e = &qp->s_ack_queue[prev];
  1301. if (!e->opcode) {
  1302. e = NULL;
  1303. break;
  1304. }
  1305. if (ipath_cmp24(psn, e->psn) >= 0) {
  1306. if (prev == qp->s_tail_ack_queue)
  1307. old_req = 0;
  1308. break;
  1309. }
  1310. }
  1311. switch (opcode) {
  1312. case OP(RDMA_READ_REQUEST): {
  1313. struct ib_reth *reth;
  1314. u32 offset;
  1315. u32 len;
  1316. /*
  1317. * If we didn't find the RDMA read request in the ack queue,
  1318. * or the send tasklet is already backed up to send an
  1319. * earlier entry, we can ignore this request.
  1320. */
  1321. if (!e || e->opcode != OP(RDMA_READ_REQUEST) || old_req)
  1322. goto unlock_done;
  1323. /* RETH comes after BTH */
  1324. if (!header_in_data)
  1325. reth = &ohdr->u.rc.reth;
  1326. else {
  1327. reth = (struct ib_reth *)data;
  1328. data += sizeof(*reth);
  1329. }
  1330. /*
  1331. * Address range must be a subset of the original
  1332. * request and start on pmtu boundaries.
  1333. * We reuse the old ack_queue slot since the requester
  1334. * should not back up and request an earlier PSN for the
  1335. * same request.
  1336. */
  1337. offset = ((psn - e->psn) & IPATH_PSN_MASK) *
  1338. ib_mtu_enum_to_int(qp->path_mtu);
  1339. len = be32_to_cpu(reth->length);
  1340. if (unlikely(offset + len > e->rdma_sge.sge.sge_length))
  1341. goto unlock_done;
  1342. if (len != 0) {
  1343. u32 rkey = be32_to_cpu(reth->rkey);
  1344. u64 vaddr = be64_to_cpu(reth->vaddr);
  1345. int ok;
  1346. ok = ipath_rkey_ok(qp, &e->rdma_sge,
  1347. len, vaddr, rkey,
  1348. IB_ACCESS_REMOTE_READ);
  1349. if (unlikely(!ok))
  1350. goto unlock_done;
  1351. } else {
  1352. e->rdma_sge.sg_list = NULL;
  1353. e->rdma_sge.num_sge = 0;
  1354. e->rdma_sge.sge.mr = NULL;
  1355. e->rdma_sge.sge.vaddr = NULL;
  1356. e->rdma_sge.sge.length = 0;
  1357. e->rdma_sge.sge.sge_length = 0;
  1358. }
  1359. e->psn = psn;
  1360. qp->s_ack_state = OP(ACKNOWLEDGE);
  1361. qp->s_tail_ack_queue = prev;
  1362. break;
  1363. }
  1364. case OP(COMPARE_SWAP):
  1365. case OP(FETCH_ADD): {
  1366. /*
  1367. * If we didn't find the atomic request in the ack queue
  1368. * or the send tasklet is already backed up to send an
  1369. * earlier entry, we can ignore this request.
  1370. */
  1371. if (!e || e->opcode != (u8) opcode || old_req)
  1372. goto unlock_done;
  1373. qp->s_ack_state = OP(ACKNOWLEDGE);
  1374. qp->s_tail_ack_queue = prev;
  1375. break;
  1376. }
  1377. default:
  1378. if (old_req)
  1379. goto unlock_done;
  1380. /*
  1381. * Resend the most recent ACK if this request is
  1382. * after all the previous RDMA reads and atomics.
  1383. */
  1384. if (i == qp->r_head_ack_queue) {
  1385. spin_unlock_irqrestore(&qp->s_lock, flags);
  1386. qp->r_nak_state = 0;
  1387. qp->r_ack_psn = qp->r_psn - 1;
  1388. goto send_ack;
  1389. }
  1390. /*
  1391. * Try to send a simple ACK to work around a Mellanox bug
  1392. * which doesn't accept a RDMA read response or atomic
  1393. * response as an ACK for earlier SENDs or RDMA writes.
  1394. */
  1395. if (qp->r_head_ack_queue == qp->s_tail_ack_queue &&
  1396. !(qp->s_flags & IPATH_S_ACK_PENDING) &&
  1397. qp->s_ack_state == OP(ACKNOWLEDGE)) {
  1398. spin_unlock_irqrestore(&qp->s_lock, flags);
  1399. qp->r_nak_state = 0;
  1400. qp->r_ack_psn = qp->s_ack_queue[i].psn - 1;
  1401. goto send_ack;
  1402. }
  1403. /*
  1404. * Resend the RDMA read or atomic op which
  1405. * ACKs this duplicate request.
  1406. */
  1407. qp->s_ack_state = OP(ACKNOWLEDGE);
  1408. qp->s_tail_ack_queue = i;
  1409. break;
  1410. }
  1411. qp->r_nak_state = 0;
  1412. ipath_schedule_send(qp);
  1413. unlock_done:
  1414. spin_unlock_irqrestore(&qp->s_lock, flags);
  1415. done:
  1416. return 1;
  1417. send_ack:
  1418. return 0;
  1419. }
  1420. void ipath_rc_error(struct ipath_qp *qp, enum ib_wc_status err)
  1421. {
  1422. unsigned long flags;
  1423. int lastwqe;
  1424. spin_lock_irqsave(&qp->s_lock, flags);
  1425. lastwqe = ipath_error_qp(qp, err);
  1426. spin_unlock_irqrestore(&qp->s_lock, flags);
  1427. if (lastwqe) {
  1428. struct ib_event ev;
  1429. ev.device = qp->ibqp.device;
  1430. ev.element.qp = &qp->ibqp;
  1431. ev.event = IB_EVENT_QP_LAST_WQE_REACHED;
  1432. qp->ibqp.event_handler(&ev, qp->ibqp.qp_context);
  1433. }
  1434. }
  1435. static inline void ipath_update_ack_queue(struct ipath_qp *qp, unsigned n)
  1436. {
  1437. unsigned next;
  1438. next = n + 1;
  1439. if (next > IPATH_MAX_RDMA_ATOMIC)
  1440. next = 0;
  1441. if (n == qp->s_tail_ack_queue) {
  1442. qp->s_tail_ack_queue = next;
  1443. qp->s_ack_state = OP(ACKNOWLEDGE);
  1444. }
  1445. }
  1446. /**
  1447. * ipath_rc_rcv - process an incoming RC packet
  1448. * @dev: the device this packet came in on
  1449. * @hdr: the header of this packet
  1450. * @has_grh: true if the header has a GRH
  1451. * @data: the packet data
  1452. * @tlen: the packet length
  1453. * @qp: the QP for this packet
  1454. *
  1455. * This is called from ipath_qp_rcv() to process an incoming RC packet
  1456. * for the given QP.
  1457. * Called at interrupt level.
  1458. */
  1459. void ipath_rc_rcv(struct ipath_ibdev *dev, struct ipath_ib_header *hdr,
  1460. int has_grh, void *data, u32 tlen, struct ipath_qp *qp)
  1461. {
  1462. struct ipath_other_headers *ohdr;
  1463. u32 opcode;
  1464. u32 hdrsize;
  1465. u32 psn;
  1466. u32 pad;
  1467. struct ib_wc wc;
  1468. u32 pmtu = ib_mtu_enum_to_int(qp->path_mtu);
  1469. int diff;
  1470. struct ib_reth *reth;
  1471. int header_in_data;
  1472. unsigned long flags;
  1473. /* Validate the SLID. See Ch. 9.6.1.5 */
  1474. if (unlikely(be16_to_cpu(hdr->lrh[3]) != qp->remote_ah_attr.dlid))
  1475. goto done;
  1476. /* Check for GRH */
  1477. if (!has_grh) {
  1478. ohdr = &hdr->u.oth;
  1479. hdrsize = 8 + 12; /* LRH + BTH */
  1480. psn = be32_to_cpu(ohdr->bth[2]);
  1481. header_in_data = 0;
  1482. } else {
  1483. ohdr = &hdr->u.l.oth;
  1484. hdrsize = 8 + 40 + 12; /* LRH + GRH + BTH */
  1485. /*
  1486. * The header with GRH is 60 bytes and the core driver sets
  1487. * the eager header buffer size to 56 bytes so the last 4
  1488. * bytes of the BTH header (PSN) is in the data buffer.
  1489. */
  1490. header_in_data = dev->dd->ipath_rcvhdrentsize == 16;
  1491. if (header_in_data) {
  1492. psn = be32_to_cpu(((__be32 *) data)[0]);
  1493. data += sizeof(__be32);
  1494. } else
  1495. psn = be32_to_cpu(ohdr->bth[2]);
  1496. }
  1497. /*
  1498. * Process responses (ACKs) before anything else. Note that the
  1499. * packet sequence number will be for something in the send work
  1500. * queue rather than the expected receive packet sequence number.
  1501. * In other words, this QP is the requester.
  1502. */
  1503. opcode = be32_to_cpu(ohdr->bth[0]) >> 24;
  1504. if (opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
  1505. opcode <= OP(ATOMIC_ACKNOWLEDGE)) {
  1506. ipath_rc_rcv_resp(dev, ohdr, data, tlen, qp, opcode, psn,
  1507. hdrsize, pmtu, header_in_data);
  1508. goto done;
  1509. }
  1510. /* Compute 24 bits worth of difference. */
  1511. diff = ipath_cmp24(psn, qp->r_psn);
  1512. if (unlikely(diff)) {
  1513. if (ipath_rc_rcv_error(dev, ohdr, data, qp, opcode,
  1514. psn, diff, header_in_data))
  1515. goto done;
  1516. goto send_ack;
  1517. }
  1518. /* Check for opcode sequence errors. */
  1519. switch (qp->r_state) {
  1520. case OP(SEND_FIRST):
  1521. case OP(SEND_MIDDLE):
  1522. if (opcode == OP(SEND_MIDDLE) ||
  1523. opcode == OP(SEND_LAST) ||
  1524. opcode == OP(SEND_LAST_WITH_IMMEDIATE))
  1525. break;
  1526. goto nack_inv;
  1527. case OP(RDMA_WRITE_FIRST):
  1528. case OP(RDMA_WRITE_MIDDLE):
  1529. if (opcode == OP(RDMA_WRITE_MIDDLE) ||
  1530. opcode == OP(RDMA_WRITE_LAST) ||
  1531. opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
  1532. break;
  1533. goto nack_inv;
  1534. default:
  1535. if (opcode == OP(SEND_MIDDLE) ||
  1536. opcode == OP(SEND_LAST) ||
  1537. opcode == OP(SEND_LAST_WITH_IMMEDIATE) ||
  1538. opcode == OP(RDMA_WRITE_MIDDLE) ||
  1539. opcode == OP(RDMA_WRITE_LAST) ||
  1540. opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
  1541. goto nack_inv;
  1542. /*
  1543. * Note that it is up to the requester to not send a new
  1544. * RDMA read or atomic operation before receiving an ACK
  1545. * for the previous operation.
  1546. */
  1547. break;
  1548. }
  1549. memset(&wc, 0, sizeof wc);
  1550. /* OK, process the packet. */
  1551. switch (opcode) {
  1552. case OP(SEND_FIRST):
  1553. if (!ipath_get_rwqe(qp, 0))
  1554. goto rnr_nak;
  1555. qp->r_rcv_len = 0;
  1556. /* FALLTHROUGH */
  1557. case OP(SEND_MIDDLE):
  1558. case OP(RDMA_WRITE_MIDDLE):
  1559. send_middle:
  1560. /* Check for invalid length PMTU or posted rwqe len. */
  1561. if (unlikely(tlen != (hdrsize + pmtu + 4)))
  1562. goto nack_inv;
  1563. qp->r_rcv_len += pmtu;
  1564. if (unlikely(qp->r_rcv_len > qp->r_len))
  1565. goto nack_inv;
  1566. ipath_copy_sge(&qp->r_sge, data, pmtu);
  1567. break;
  1568. case OP(RDMA_WRITE_LAST_WITH_IMMEDIATE):
  1569. /* consume RWQE */
  1570. if (!ipath_get_rwqe(qp, 1))
  1571. goto rnr_nak;
  1572. goto send_last_imm;
  1573. case OP(SEND_ONLY):
  1574. case OP(SEND_ONLY_WITH_IMMEDIATE):
  1575. if (!ipath_get_rwqe(qp, 0))
  1576. goto rnr_nak;
  1577. qp->r_rcv_len = 0;
  1578. if (opcode == OP(SEND_ONLY))
  1579. goto send_last;
  1580. /* FALLTHROUGH */
  1581. case OP(SEND_LAST_WITH_IMMEDIATE):
  1582. send_last_imm:
  1583. if (header_in_data) {
  1584. wc.ex.imm_data = *(__be32 *) data;
  1585. data += sizeof(__be32);
  1586. } else {
  1587. /* Immediate data comes after BTH */
  1588. wc.ex.imm_data = ohdr->u.imm_data;
  1589. }
  1590. hdrsize += 4;
  1591. wc.wc_flags = IB_WC_WITH_IMM;
  1592. /* FALLTHROUGH */
  1593. case OP(SEND_LAST):
  1594. case OP(RDMA_WRITE_LAST):
  1595. send_last:
  1596. /* Get the number of bytes the message was padded by. */
  1597. pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3;
  1598. /* Check for invalid length. */
  1599. /* XXX LAST len should be >= 1 */
  1600. if (unlikely(tlen < (hdrsize + pad + 4)))
  1601. goto nack_inv;
  1602. /* Don't count the CRC. */
  1603. tlen -= (hdrsize + pad + 4);
  1604. wc.byte_len = tlen + qp->r_rcv_len;
  1605. if (unlikely(wc.byte_len > qp->r_len))
  1606. goto nack_inv;
  1607. ipath_copy_sge(&qp->r_sge, data, tlen);
  1608. qp->r_msn++;
  1609. if (!test_and_clear_bit(IPATH_R_WRID_VALID, &qp->r_aflags))
  1610. break;
  1611. wc.wr_id = qp->r_wr_id;
  1612. wc.status = IB_WC_SUCCESS;
  1613. if (opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE) ||
  1614. opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE))
  1615. wc.opcode = IB_WC_RECV_RDMA_WITH_IMM;
  1616. else
  1617. wc.opcode = IB_WC_RECV;
  1618. wc.qp = &qp->ibqp;
  1619. wc.src_qp = qp->remote_qpn;
  1620. wc.slid = qp->remote_ah_attr.dlid;
  1621. wc.sl = qp->remote_ah_attr.sl;
  1622. /* Signal completion event if the solicited bit is set. */
  1623. ipath_cq_enter(to_icq(qp->ibqp.recv_cq), &wc,
  1624. (ohdr->bth[0] &
  1625. __constant_cpu_to_be32(1 << 23)) != 0);
  1626. break;
  1627. case OP(RDMA_WRITE_FIRST):
  1628. case OP(RDMA_WRITE_ONLY):
  1629. case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE):
  1630. if (unlikely(!(qp->qp_access_flags &
  1631. IB_ACCESS_REMOTE_WRITE)))
  1632. goto nack_inv;
  1633. /* consume RWQE */
  1634. /* RETH comes after BTH */
  1635. if (!header_in_data)
  1636. reth = &ohdr->u.rc.reth;
  1637. else {
  1638. reth = (struct ib_reth *)data;
  1639. data += sizeof(*reth);
  1640. }
  1641. hdrsize += sizeof(*reth);
  1642. qp->r_len = be32_to_cpu(reth->length);
  1643. qp->r_rcv_len = 0;
  1644. if (qp->r_len != 0) {
  1645. u32 rkey = be32_to_cpu(reth->rkey);
  1646. u64 vaddr = be64_to_cpu(reth->vaddr);
  1647. int ok;
  1648. /* Check rkey & NAK */
  1649. ok = ipath_rkey_ok(qp, &qp->r_sge,
  1650. qp->r_len, vaddr, rkey,
  1651. IB_ACCESS_REMOTE_WRITE);
  1652. if (unlikely(!ok))
  1653. goto nack_acc;
  1654. } else {
  1655. qp->r_sge.sg_list = NULL;
  1656. qp->r_sge.sge.mr = NULL;
  1657. qp->r_sge.sge.vaddr = NULL;
  1658. qp->r_sge.sge.length = 0;
  1659. qp->r_sge.sge.sge_length = 0;
  1660. }
  1661. if (opcode == OP(RDMA_WRITE_FIRST))
  1662. goto send_middle;
  1663. else if (opcode == OP(RDMA_WRITE_ONLY))
  1664. goto send_last;
  1665. if (!ipath_get_rwqe(qp, 1))
  1666. goto rnr_nak;
  1667. goto send_last_imm;
  1668. case OP(RDMA_READ_REQUEST): {
  1669. struct ipath_ack_entry *e;
  1670. u32 len;
  1671. u8 next;
  1672. if (unlikely(!(qp->qp_access_flags &
  1673. IB_ACCESS_REMOTE_READ)))
  1674. goto nack_inv;
  1675. next = qp->r_head_ack_queue + 1;
  1676. if (next > IPATH_MAX_RDMA_ATOMIC)
  1677. next = 0;
  1678. spin_lock_irqsave(&qp->s_lock, flags);
  1679. /* Double check we can process this while holding the s_lock. */
  1680. if (!(ib_ipath_state_ops[qp->state] & IPATH_PROCESS_RECV_OK))
  1681. goto unlock;
  1682. if (unlikely(next == qp->s_tail_ack_queue)) {
  1683. if (!qp->s_ack_queue[next].sent)
  1684. goto nack_inv_unlck;
  1685. ipath_update_ack_queue(qp, next);
  1686. }
  1687. e = &qp->s_ack_queue[qp->r_head_ack_queue];
  1688. /* RETH comes after BTH */
  1689. if (!header_in_data)
  1690. reth = &ohdr->u.rc.reth;
  1691. else {
  1692. reth = (struct ib_reth *)data;
  1693. data += sizeof(*reth);
  1694. }
  1695. len = be32_to_cpu(reth->length);
  1696. if (len) {
  1697. u32 rkey = be32_to_cpu(reth->rkey);
  1698. u64 vaddr = be64_to_cpu(reth->vaddr);
  1699. int ok;
  1700. /* Check rkey & NAK */
  1701. ok = ipath_rkey_ok(qp, &e->rdma_sge, len, vaddr,
  1702. rkey, IB_ACCESS_REMOTE_READ);
  1703. if (unlikely(!ok))
  1704. goto nack_acc_unlck;
  1705. /*
  1706. * Update the next expected PSN. We add 1 later
  1707. * below, so only add the remainder here.
  1708. */
  1709. if (len > pmtu)
  1710. qp->r_psn += (len - 1) / pmtu;
  1711. } else {
  1712. e->rdma_sge.sg_list = NULL;
  1713. e->rdma_sge.num_sge = 0;
  1714. e->rdma_sge.sge.mr = NULL;
  1715. e->rdma_sge.sge.vaddr = NULL;
  1716. e->rdma_sge.sge.length = 0;
  1717. e->rdma_sge.sge.sge_length = 0;
  1718. }
  1719. e->opcode = opcode;
  1720. e->sent = 0;
  1721. e->psn = psn;
  1722. /*
  1723. * We need to increment the MSN here instead of when we
  1724. * finish sending the result since a duplicate request would
  1725. * increment it more than once.
  1726. */
  1727. qp->r_msn++;
  1728. qp->r_psn++;
  1729. qp->r_state = opcode;
  1730. qp->r_nak_state = 0;
  1731. qp->r_head_ack_queue = next;
  1732. /* Schedule the send tasklet. */
  1733. ipath_schedule_send(qp);
  1734. goto unlock;
  1735. }
  1736. case OP(COMPARE_SWAP):
  1737. case OP(FETCH_ADD): {
  1738. struct ib_atomic_eth *ateth;
  1739. struct ipath_ack_entry *e;
  1740. u64 vaddr;
  1741. atomic64_t *maddr;
  1742. u64 sdata;
  1743. u32 rkey;
  1744. u8 next;
  1745. if (unlikely(!(qp->qp_access_flags &
  1746. IB_ACCESS_REMOTE_ATOMIC)))
  1747. goto nack_inv;
  1748. next = qp->r_head_ack_queue + 1;
  1749. if (next > IPATH_MAX_RDMA_ATOMIC)
  1750. next = 0;
  1751. spin_lock_irqsave(&qp->s_lock, flags);
  1752. /* Double check we can process this while holding the s_lock. */
  1753. if (!(ib_ipath_state_ops[qp->state] & IPATH_PROCESS_RECV_OK))
  1754. goto unlock;
  1755. if (unlikely(next == qp->s_tail_ack_queue)) {
  1756. if (!qp->s_ack_queue[next].sent)
  1757. goto nack_inv_unlck;
  1758. ipath_update_ack_queue(qp, next);
  1759. }
  1760. if (!header_in_data)
  1761. ateth = &ohdr->u.atomic_eth;
  1762. else
  1763. ateth = (struct ib_atomic_eth *)data;
  1764. vaddr = ((u64) be32_to_cpu(ateth->vaddr[0]) << 32) |
  1765. be32_to_cpu(ateth->vaddr[1]);
  1766. if (unlikely(vaddr & (sizeof(u64) - 1)))
  1767. goto nack_inv_unlck;
  1768. rkey = be32_to_cpu(ateth->rkey);
  1769. /* Check rkey & NAK */
  1770. if (unlikely(!ipath_rkey_ok(qp, &qp->r_sge,
  1771. sizeof(u64), vaddr, rkey,
  1772. IB_ACCESS_REMOTE_ATOMIC)))
  1773. goto nack_acc_unlck;
  1774. /* Perform atomic OP and save result. */
  1775. maddr = (atomic64_t *) qp->r_sge.sge.vaddr;
  1776. sdata = be64_to_cpu(ateth->swap_data);
  1777. e = &qp->s_ack_queue[qp->r_head_ack_queue];
  1778. e->atomic_data = (opcode == OP(FETCH_ADD)) ?
  1779. (u64) atomic64_add_return(sdata, maddr) - sdata :
  1780. (u64) cmpxchg((u64 *) qp->r_sge.sge.vaddr,
  1781. be64_to_cpu(ateth->compare_data),
  1782. sdata);
  1783. e->opcode = opcode;
  1784. e->sent = 0;
  1785. e->psn = psn & IPATH_PSN_MASK;
  1786. qp->r_msn++;
  1787. qp->r_psn++;
  1788. qp->r_state = opcode;
  1789. qp->r_nak_state = 0;
  1790. qp->r_head_ack_queue = next;
  1791. /* Schedule the send tasklet. */
  1792. ipath_schedule_send(qp);
  1793. goto unlock;
  1794. }
  1795. default:
  1796. /* NAK unknown opcodes. */
  1797. goto nack_inv;
  1798. }
  1799. qp->r_psn++;
  1800. qp->r_state = opcode;
  1801. qp->r_ack_psn = psn;
  1802. qp->r_nak_state = 0;
  1803. /* Send an ACK if requested or required. */
  1804. if (psn & (1 << 31))
  1805. goto send_ack;
  1806. goto done;
  1807. rnr_nak:
  1808. qp->r_nak_state = IB_RNR_NAK | qp->r_min_rnr_timer;
  1809. qp->r_ack_psn = qp->r_psn;
  1810. goto send_ack;
  1811. nack_inv_unlck:
  1812. spin_unlock_irqrestore(&qp->s_lock, flags);
  1813. nack_inv:
  1814. ipath_rc_error(qp, IB_WC_LOC_QP_OP_ERR);
  1815. qp->r_nak_state = IB_NAK_INVALID_REQUEST;
  1816. qp->r_ack_psn = qp->r_psn;
  1817. goto send_ack;
  1818. nack_acc_unlck:
  1819. spin_unlock_irqrestore(&qp->s_lock, flags);
  1820. nack_acc:
  1821. ipath_rc_error(qp, IB_WC_LOC_PROT_ERR);
  1822. qp->r_nak_state = IB_NAK_REMOTE_ACCESS_ERROR;
  1823. qp->r_ack_psn = qp->r_psn;
  1824. send_ack:
  1825. send_rc_ack(qp);
  1826. goto done;
  1827. unlock:
  1828. spin_unlock_irqrestore(&qp->s_lock, flags);
  1829. done:
  1830. return;
  1831. }