c2.c 33 KB

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  1. /*
  2. * Copyright (c) 2005 Ammasso, Inc. All rights reserved.
  3. * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/module.h>
  34. #include <linux/moduleparam.h>
  35. #include <linux/pci.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/etherdevice.h>
  38. #include <linux/inetdevice.h>
  39. #include <linux/delay.h>
  40. #include <linux/ethtool.h>
  41. #include <linux/mii.h>
  42. #include <linux/if_vlan.h>
  43. #include <linux/crc32.h>
  44. #include <linux/in.h>
  45. #include <linux/ip.h>
  46. #include <linux/tcp.h>
  47. #include <linux/init.h>
  48. #include <linux/dma-mapping.h>
  49. #include <asm/io.h>
  50. #include <asm/irq.h>
  51. #include <asm/byteorder.h>
  52. #include <rdma/ib_smi.h>
  53. #include "c2.h"
  54. #include "c2_provider.h"
  55. MODULE_AUTHOR("Tom Tucker <tom@opengridcomputing.com>");
  56. MODULE_DESCRIPTION("Ammasso AMSO1100 Low-level iWARP Driver");
  57. MODULE_LICENSE("Dual BSD/GPL");
  58. MODULE_VERSION(DRV_VERSION);
  59. static const u32 default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  60. | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  61. static int debug = -1; /* defaults above */
  62. module_param(debug, int, 0);
  63. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  64. static int c2_up(struct net_device *netdev);
  65. static int c2_down(struct net_device *netdev);
  66. static int c2_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
  67. static void c2_tx_interrupt(struct net_device *netdev);
  68. static void c2_rx_interrupt(struct net_device *netdev);
  69. static irqreturn_t c2_interrupt(int irq, void *dev_id);
  70. static void c2_tx_timeout(struct net_device *netdev);
  71. static int c2_change_mtu(struct net_device *netdev, int new_mtu);
  72. static void c2_reset(struct c2_port *c2_port);
  73. static struct net_device_stats *c2_get_stats(struct net_device *netdev);
  74. static struct pci_device_id c2_pci_table[] = {
  75. { PCI_DEVICE(0x18b8, 0xb001) },
  76. { 0 }
  77. };
  78. MODULE_DEVICE_TABLE(pci, c2_pci_table);
  79. static void c2_print_macaddr(struct net_device *netdev)
  80. {
  81. pr_debug("%s: MAC %02X:%02X:%02X:%02X:%02X:%02X, "
  82. "IRQ %u\n", netdev->name,
  83. netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
  84. netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5],
  85. netdev->irq);
  86. }
  87. static void c2_set_rxbufsize(struct c2_port *c2_port)
  88. {
  89. struct net_device *netdev = c2_port->netdev;
  90. if (netdev->mtu > RX_BUF_SIZE)
  91. c2_port->rx_buf_size =
  92. netdev->mtu + ETH_HLEN + sizeof(struct c2_rxp_hdr) +
  93. NET_IP_ALIGN;
  94. else
  95. c2_port->rx_buf_size = sizeof(struct c2_rxp_hdr) + RX_BUF_SIZE;
  96. }
  97. /*
  98. * Allocate TX ring elements and chain them together.
  99. * One-to-one association of adapter descriptors with ring elements.
  100. */
  101. static int c2_tx_ring_alloc(struct c2_ring *tx_ring, void *vaddr,
  102. dma_addr_t base, void __iomem * mmio_txp_ring)
  103. {
  104. struct c2_tx_desc *tx_desc;
  105. struct c2_txp_desc __iomem *txp_desc;
  106. struct c2_element *elem;
  107. int i;
  108. tx_ring->start = kmalloc(sizeof(*elem) * tx_ring->count, GFP_KERNEL);
  109. if (!tx_ring->start)
  110. return -ENOMEM;
  111. elem = tx_ring->start;
  112. tx_desc = vaddr;
  113. txp_desc = mmio_txp_ring;
  114. for (i = 0; i < tx_ring->count; i++, elem++, tx_desc++, txp_desc++) {
  115. tx_desc->len = 0;
  116. tx_desc->status = 0;
  117. /* Set TXP_HTXD_UNINIT */
  118. __raw_writeq((__force u64) cpu_to_be64(0x1122334455667788ULL),
  119. (void __iomem *) txp_desc + C2_TXP_ADDR);
  120. __raw_writew(0, (void __iomem *) txp_desc + C2_TXP_LEN);
  121. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_UNINIT),
  122. (void __iomem *) txp_desc + C2_TXP_FLAGS);
  123. elem->skb = NULL;
  124. elem->ht_desc = tx_desc;
  125. elem->hw_desc = txp_desc;
  126. if (i == tx_ring->count - 1) {
  127. elem->next = tx_ring->start;
  128. tx_desc->next_offset = base;
  129. } else {
  130. elem->next = elem + 1;
  131. tx_desc->next_offset =
  132. base + (i + 1) * sizeof(*tx_desc);
  133. }
  134. }
  135. tx_ring->to_use = tx_ring->to_clean = tx_ring->start;
  136. return 0;
  137. }
  138. /*
  139. * Allocate RX ring elements and chain them together.
  140. * One-to-one association of adapter descriptors with ring elements.
  141. */
  142. static int c2_rx_ring_alloc(struct c2_ring *rx_ring, void *vaddr,
  143. dma_addr_t base, void __iomem * mmio_rxp_ring)
  144. {
  145. struct c2_rx_desc *rx_desc;
  146. struct c2_rxp_desc __iomem *rxp_desc;
  147. struct c2_element *elem;
  148. int i;
  149. rx_ring->start = kmalloc(sizeof(*elem) * rx_ring->count, GFP_KERNEL);
  150. if (!rx_ring->start)
  151. return -ENOMEM;
  152. elem = rx_ring->start;
  153. rx_desc = vaddr;
  154. rxp_desc = mmio_rxp_ring;
  155. for (i = 0; i < rx_ring->count; i++, elem++, rx_desc++, rxp_desc++) {
  156. rx_desc->len = 0;
  157. rx_desc->status = 0;
  158. /* Set RXP_HRXD_UNINIT */
  159. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_OK),
  160. (void __iomem *) rxp_desc + C2_RXP_STATUS);
  161. __raw_writew(0, (void __iomem *) rxp_desc + C2_RXP_COUNT);
  162. __raw_writew(0, (void __iomem *) rxp_desc + C2_RXP_LEN);
  163. __raw_writeq((__force u64) cpu_to_be64(0x99aabbccddeeffULL),
  164. (void __iomem *) rxp_desc + C2_RXP_ADDR);
  165. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_UNINIT),
  166. (void __iomem *) rxp_desc + C2_RXP_FLAGS);
  167. elem->skb = NULL;
  168. elem->ht_desc = rx_desc;
  169. elem->hw_desc = rxp_desc;
  170. if (i == rx_ring->count - 1) {
  171. elem->next = rx_ring->start;
  172. rx_desc->next_offset = base;
  173. } else {
  174. elem->next = elem + 1;
  175. rx_desc->next_offset =
  176. base + (i + 1) * sizeof(*rx_desc);
  177. }
  178. }
  179. rx_ring->to_use = rx_ring->to_clean = rx_ring->start;
  180. return 0;
  181. }
  182. /* Setup buffer for receiving */
  183. static inline int c2_rx_alloc(struct c2_port *c2_port, struct c2_element *elem)
  184. {
  185. struct c2_dev *c2dev = c2_port->c2dev;
  186. struct c2_rx_desc *rx_desc = elem->ht_desc;
  187. struct sk_buff *skb;
  188. dma_addr_t mapaddr;
  189. u32 maplen;
  190. struct c2_rxp_hdr *rxp_hdr;
  191. skb = dev_alloc_skb(c2_port->rx_buf_size);
  192. if (unlikely(!skb)) {
  193. pr_debug("%s: out of memory for receive\n",
  194. c2_port->netdev->name);
  195. return -ENOMEM;
  196. }
  197. /* Zero out the rxp hdr in the sk_buff */
  198. memset(skb->data, 0, sizeof(*rxp_hdr));
  199. skb->dev = c2_port->netdev;
  200. maplen = c2_port->rx_buf_size;
  201. mapaddr =
  202. pci_map_single(c2dev->pcidev, skb->data, maplen,
  203. PCI_DMA_FROMDEVICE);
  204. /* Set the sk_buff RXP_header to RXP_HRXD_READY */
  205. rxp_hdr = (struct c2_rxp_hdr *) skb->data;
  206. rxp_hdr->flags = RXP_HRXD_READY;
  207. __raw_writew(0, elem->hw_desc + C2_RXP_STATUS);
  208. __raw_writew((__force u16) cpu_to_be16((u16) maplen - sizeof(*rxp_hdr)),
  209. elem->hw_desc + C2_RXP_LEN);
  210. __raw_writeq((__force u64) cpu_to_be64(mapaddr), elem->hw_desc + C2_RXP_ADDR);
  211. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_READY),
  212. elem->hw_desc + C2_RXP_FLAGS);
  213. elem->skb = skb;
  214. elem->mapaddr = mapaddr;
  215. elem->maplen = maplen;
  216. rx_desc->len = maplen;
  217. return 0;
  218. }
  219. /*
  220. * Allocate buffers for the Rx ring
  221. * For receive: rx_ring.to_clean is next received frame
  222. */
  223. static int c2_rx_fill(struct c2_port *c2_port)
  224. {
  225. struct c2_ring *rx_ring = &c2_port->rx_ring;
  226. struct c2_element *elem;
  227. int ret = 0;
  228. elem = rx_ring->start;
  229. do {
  230. if (c2_rx_alloc(c2_port, elem)) {
  231. ret = 1;
  232. break;
  233. }
  234. } while ((elem = elem->next) != rx_ring->start);
  235. rx_ring->to_clean = rx_ring->start;
  236. return ret;
  237. }
  238. /* Free all buffers in RX ring, assumes receiver stopped */
  239. static void c2_rx_clean(struct c2_port *c2_port)
  240. {
  241. struct c2_dev *c2dev = c2_port->c2dev;
  242. struct c2_ring *rx_ring = &c2_port->rx_ring;
  243. struct c2_element *elem;
  244. struct c2_rx_desc *rx_desc;
  245. elem = rx_ring->start;
  246. do {
  247. rx_desc = elem->ht_desc;
  248. rx_desc->len = 0;
  249. __raw_writew(0, elem->hw_desc + C2_RXP_STATUS);
  250. __raw_writew(0, elem->hw_desc + C2_RXP_COUNT);
  251. __raw_writew(0, elem->hw_desc + C2_RXP_LEN);
  252. __raw_writeq((__force u64) cpu_to_be64(0x99aabbccddeeffULL),
  253. elem->hw_desc + C2_RXP_ADDR);
  254. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_UNINIT),
  255. elem->hw_desc + C2_RXP_FLAGS);
  256. if (elem->skb) {
  257. pci_unmap_single(c2dev->pcidev, elem->mapaddr,
  258. elem->maplen, PCI_DMA_FROMDEVICE);
  259. dev_kfree_skb(elem->skb);
  260. elem->skb = NULL;
  261. }
  262. } while ((elem = elem->next) != rx_ring->start);
  263. }
  264. static inline int c2_tx_free(struct c2_dev *c2dev, struct c2_element *elem)
  265. {
  266. struct c2_tx_desc *tx_desc = elem->ht_desc;
  267. tx_desc->len = 0;
  268. pci_unmap_single(c2dev->pcidev, elem->mapaddr, elem->maplen,
  269. PCI_DMA_TODEVICE);
  270. if (elem->skb) {
  271. dev_kfree_skb_any(elem->skb);
  272. elem->skb = NULL;
  273. }
  274. return 0;
  275. }
  276. /* Free all buffers in TX ring, assumes transmitter stopped */
  277. static void c2_tx_clean(struct c2_port *c2_port)
  278. {
  279. struct c2_ring *tx_ring = &c2_port->tx_ring;
  280. struct c2_element *elem;
  281. struct c2_txp_desc txp_htxd;
  282. int retry;
  283. unsigned long flags;
  284. spin_lock_irqsave(&c2_port->tx_lock, flags);
  285. elem = tx_ring->start;
  286. do {
  287. retry = 0;
  288. do {
  289. txp_htxd.flags =
  290. readw(elem->hw_desc + C2_TXP_FLAGS);
  291. if (txp_htxd.flags == TXP_HTXD_READY) {
  292. retry = 1;
  293. __raw_writew(0,
  294. elem->hw_desc + C2_TXP_LEN);
  295. __raw_writeq(0,
  296. elem->hw_desc + C2_TXP_ADDR);
  297. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_DONE),
  298. elem->hw_desc + C2_TXP_FLAGS);
  299. c2_port->netstats.tx_dropped++;
  300. break;
  301. } else {
  302. __raw_writew(0,
  303. elem->hw_desc + C2_TXP_LEN);
  304. __raw_writeq((__force u64) cpu_to_be64(0x1122334455667788ULL),
  305. elem->hw_desc + C2_TXP_ADDR);
  306. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_UNINIT),
  307. elem->hw_desc + C2_TXP_FLAGS);
  308. }
  309. c2_tx_free(c2_port->c2dev, elem);
  310. } while ((elem = elem->next) != tx_ring->start);
  311. } while (retry);
  312. c2_port->tx_avail = c2_port->tx_ring.count - 1;
  313. c2_port->c2dev->cur_tx = tx_ring->to_use - tx_ring->start;
  314. if (c2_port->tx_avail > MAX_SKB_FRAGS + 1)
  315. netif_wake_queue(c2_port->netdev);
  316. spin_unlock_irqrestore(&c2_port->tx_lock, flags);
  317. }
  318. /*
  319. * Process transmit descriptors marked 'DONE' by the firmware,
  320. * freeing up their unneeded sk_buffs.
  321. */
  322. static void c2_tx_interrupt(struct net_device *netdev)
  323. {
  324. struct c2_port *c2_port = netdev_priv(netdev);
  325. struct c2_dev *c2dev = c2_port->c2dev;
  326. struct c2_ring *tx_ring = &c2_port->tx_ring;
  327. struct c2_element *elem;
  328. struct c2_txp_desc txp_htxd;
  329. spin_lock(&c2_port->tx_lock);
  330. for (elem = tx_ring->to_clean; elem != tx_ring->to_use;
  331. elem = elem->next) {
  332. txp_htxd.flags =
  333. be16_to_cpu((__force __be16) readw(elem->hw_desc + C2_TXP_FLAGS));
  334. if (txp_htxd.flags != TXP_HTXD_DONE)
  335. break;
  336. if (netif_msg_tx_done(c2_port)) {
  337. /* PCI reads are expensive in fast path */
  338. txp_htxd.len =
  339. be16_to_cpu((__force __be16) readw(elem->hw_desc + C2_TXP_LEN));
  340. pr_debug("%s: tx done slot %3Zu status 0x%x len "
  341. "%5u bytes\n",
  342. netdev->name, elem - tx_ring->start,
  343. txp_htxd.flags, txp_htxd.len);
  344. }
  345. c2_tx_free(c2dev, elem);
  346. ++(c2_port->tx_avail);
  347. }
  348. tx_ring->to_clean = elem;
  349. if (netif_queue_stopped(netdev)
  350. && c2_port->tx_avail > MAX_SKB_FRAGS + 1)
  351. netif_wake_queue(netdev);
  352. spin_unlock(&c2_port->tx_lock);
  353. }
  354. static void c2_rx_error(struct c2_port *c2_port, struct c2_element *elem)
  355. {
  356. struct c2_rx_desc *rx_desc = elem->ht_desc;
  357. struct c2_rxp_hdr *rxp_hdr = (struct c2_rxp_hdr *) elem->skb->data;
  358. if (rxp_hdr->status != RXP_HRXD_OK ||
  359. rxp_hdr->len > (rx_desc->len - sizeof(*rxp_hdr))) {
  360. pr_debug("BAD RXP_HRXD\n");
  361. pr_debug(" rx_desc : %p\n", rx_desc);
  362. pr_debug(" index : %Zu\n",
  363. elem - c2_port->rx_ring.start);
  364. pr_debug(" len : %u\n", rx_desc->len);
  365. pr_debug(" rxp_hdr : %p [PA %p]\n", rxp_hdr,
  366. (void *) __pa((unsigned long) rxp_hdr));
  367. pr_debug(" flags : 0x%x\n", rxp_hdr->flags);
  368. pr_debug(" status: 0x%x\n", rxp_hdr->status);
  369. pr_debug(" len : %u\n", rxp_hdr->len);
  370. pr_debug(" rsvd : 0x%x\n", rxp_hdr->rsvd);
  371. }
  372. /* Setup the skb for reuse since we're dropping this pkt */
  373. elem->skb->data = elem->skb->head;
  374. skb_reset_tail_pointer(elem->skb);
  375. /* Zero out the rxp hdr in the sk_buff */
  376. memset(elem->skb->data, 0, sizeof(*rxp_hdr));
  377. /* Write the descriptor to the adapter's rx ring */
  378. __raw_writew(0, elem->hw_desc + C2_RXP_STATUS);
  379. __raw_writew(0, elem->hw_desc + C2_RXP_COUNT);
  380. __raw_writew((__force u16) cpu_to_be16((u16) elem->maplen - sizeof(*rxp_hdr)),
  381. elem->hw_desc + C2_RXP_LEN);
  382. __raw_writeq((__force u64) cpu_to_be64(elem->mapaddr),
  383. elem->hw_desc + C2_RXP_ADDR);
  384. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_READY),
  385. elem->hw_desc + C2_RXP_FLAGS);
  386. pr_debug("packet dropped\n");
  387. c2_port->netstats.rx_dropped++;
  388. }
  389. static void c2_rx_interrupt(struct net_device *netdev)
  390. {
  391. struct c2_port *c2_port = netdev_priv(netdev);
  392. struct c2_dev *c2dev = c2_port->c2dev;
  393. struct c2_ring *rx_ring = &c2_port->rx_ring;
  394. struct c2_element *elem;
  395. struct c2_rx_desc *rx_desc;
  396. struct c2_rxp_hdr *rxp_hdr;
  397. struct sk_buff *skb;
  398. dma_addr_t mapaddr;
  399. u32 maplen, buflen;
  400. unsigned long flags;
  401. spin_lock_irqsave(&c2dev->lock, flags);
  402. /* Begin where we left off */
  403. rx_ring->to_clean = rx_ring->start + c2dev->cur_rx;
  404. for (elem = rx_ring->to_clean; elem->next != rx_ring->to_clean;
  405. elem = elem->next) {
  406. rx_desc = elem->ht_desc;
  407. mapaddr = elem->mapaddr;
  408. maplen = elem->maplen;
  409. skb = elem->skb;
  410. rxp_hdr = (struct c2_rxp_hdr *) skb->data;
  411. if (rxp_hdr->flags != RXP_HRXD_DONE)
  412. break;
  413. buflen = rxp_hdr->len;
  414. /* Sanity check the RXP header */
  415. if (rxp_hdr->status != RXP_HRXD_OK ||
  416. buflen > (rx_desc->len - sizeof(*rxp_hdr))) {
  417. c2_rx_error(c2_port, elem);
  418. continue;
  419. }
  420. /*
  421. * Allocate and map a new skb for replenishing the host
  422. * RX desc
  423. */
  424. if (c2_rx_alloc(c2_port, elem)) {
  425. c2_rx_error(c2_port, elem);
  426. continue;
  427. }
  428. /* Unmap the old skb */
  429. pci_unmap_single(c2dev->pcidev, mapaddr, maplen,
  430. PCI_DMA_FROMDEVICE);
  431. prefetch(skb->data);
  432. /*
  433. * Skip past the leading 8 bytes comprising of the
  434. * "struct c2_rxp_hdr", prepended by the adapter
  435. * to the usual Ethernet header ("struct ethhdr"),
  436. * to the start of the raw Ethernet packet.
  437. *
  438. * Fix up the various fields in the sk_buff before
  439. * passing it up to netif_rx(). The transfer size
  440. * (in bytes) specified by the adapter len field of
  441. * the "struct rxp_hdr_t" does NOT include the
  442. * "sizeof(struct c2_rxp_hdr)".
  443. */
  444. skb->data += sizeof(*rxp_hdr);
  445. skb_set_tail_pointer(skb, buflen);
  446. skb->len = buflen;
  447. skb->protocol = eth_type_trans(skb, netdev);
  448. netif_rx(skb);
  449. netdev->last_rx = jiffies;
  450. c2_port->netstats.rx_packets++;
  451. c2_port->netstats.rx_bytes += buflen;
  452. }
  453. /* Save where we left off */
  454. rx_ring->to_clean = elem;
  455. c2dev->cur_rx = elem - rx_ring->start;
  456. C2_SET_CUR_RX(c2dev, c2dev->cur_rx);
  457. spin_unlock_irqrestore(&c2dev->lock, flags);
  458. }
  459. /*
  460. * Handle netisr0 TX & RX interrupts.
  461. */
  462. static irqreturn_t c2_interrupt(int irq, void *dev_id)
  463. {
  464. unsigned int netisr0, dmaisr;
  465. int handled = 0;
  466. struct c2_dev *c2dev = (struct c2_dev *) dev_id;
  467. /* Process CCILNET interrupts */
  468. netisr0 = readl(c2dev->regs + C2_NISR0);
  469. if (netisr0) {
  470. /*
  471. * There is an issue with the firmware that always
  472. * provides the status of RX for both TX & RX
  473. * interrupts. So process both queues here.
  474. */
  475. c2_rx_interrupt(c2dev->netdev);
  476. c2_tx_interrupt(c2dev->netdev);
  477. /* Clear the interrupt */
  478. writel(netisr0, c2dev->regs + C2_NISR0);
  479. handled++;
  480. }
  481. /* Process RNIC interrupts */
  482. dmaisr = readl(c2dev->regs + C2_DISR);
  483. if (dmaisr) {
  484. writel(dmaisr, c2dev->regs + C2_DISR);
  485. c2_rnic_interrupt(c2dev);
  486. handled++;
  487. }
  488. if (handled) {
  489. return IRQ_HANDLED;
  490. } else {
  491. return IRQ_NONE;
  492. }
  493. }
  494. static int c2_up(struct net_device *netdev)
  495. {
  496. struct c2_port *c2_port = netdev_priv(netdev);
  497. struct c2_dev *c2dev = c2_port->c2dev;
  498. struct c2_element *elem;
  499. struct c2_rxp_hdr *rxp_hdr;
  500. struct in_device *in_dev;
  501. size_t rx_size, tx_size;
  502. int ret, i;
  503. unsigned int netimr0;
  504. if (netif_msg_ifup(c2_port))
  505. pr_debug("%s: enabling interface\n", netdev->name);
  506. /* Set the Rx buffer size based on MTU */
  507. c2_set_rxbufsize(c2_port);
  508. /* Allocate DMA'able memory for Tx/Rx host descriptor rings */
  509. rx_size = c2_port->rx_ring.count * sizeof(struct c2_rx_desc);
  510. tx_size = c2_port->tx_ring.count * sizeof(struct c2_tx_desc);
  511. c2_port->mem_size = tx_size + rx_size;
  512. c2_port->mem = pci_alloc_consistent(c2dev->pcidev, c2_port->mem_size,
  513. &c2_port->dma);
  514. if (c2_port->mem == NULL) {
  515. pr_debug("Unable to allocate memory for "
  516. "host descriptor rings\n");
  517. return -ENOMEM;
  518. }
  519. memset(c2_port->mem, 0, c2_port->mem_size);
  520. /* Create the Rx host descriptor ring */
  521. if ((ret =
  522. c2_rx_ring_alloc(&c2_port->rx_ring, c2_port->mem, c2_port->dma,
  523. c2dev->mmio_rxp_ring))) {
  524. pr_debug("Unable to create RX ring\n");
  525. goto bail0;
  526. }
  527. /* Allocate Rx buffers for the host descriptor ring */
  528. if (c2_rx_fill(c2_port)) {
  529. pr_debug("Unable to fill RX ring\n");
  530. goto bail1;
  531. }
  532. /* Create the Tx host descriptor ring */
  533. if ((ret = c2_tx_ring_alloc(&c2_port->tx_ring, c2_port->mem + rx_size,
  534. c2_port->dma + rx_size,
  535. c2dev->mmio_txp_ring))) {
  536. pr_debug("Unable to create TX ring\n");
  537. goto bail1;
  538. }
  539. /* Set the TX pointer to where we left off */
  540. c2_port->tx_avail = c2_port->tx_ring.count - 1;
  541. c2_port->tx_ring.to_use = c2_port->tx_ring.to_clean =
  542. c2_port->tx_ring.start + c2dev->cur_tx;
  543. /* missing: Initialize MAC */
  544. BUG_ON(c2_port->tx_ring.to_use != c2_port->tx_ring.to_clean);
  545. /* Reset the adapter, ensures the driver is in sync with the RXP */
  546. c2_reset(c2_port);
  547. /* Reset the READY bit in the sk_buff RXP headers & adapter HRXDQ */
  548. for (i = 0, elem = c2_port->rx_ring.start; i < c2_port->rx_ring.count;
  549. i++, elem++) {
  550. rxp_hdr = (struct c2_rxp_hdr *) elem->skb->data;
  551. rxp_hdr->flags = 0;
  552. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_READY),
  553. elem->hw_desc + C2_RXP_FLAGS);
  554. }
  555. /* Enable network packets */
  556. netif_start_queue(netdev);
  557. /* Enable IRQ */
  558. writel(0, c2dev->regs + C2_IDIS);
  559. netimr0 = readl(c2dev->regs + C2_NIMR0);
  560. netimr0 &= ~(C2_PCI_HTX_INT | C2_PCI_HRX_INT);
  561. writel(netimr0, c2dev->regs + C2_NIMR0);
  562. /* Tell the stack to ignore arp requests for ipaddrs bound to
  563. * other interfaces. This is needed to prevent the host stack
  564. * from responding to arp requests to the ipaddr bound on the
  565. * rdma interface.
  566. */
  567. in_dev = in_dev_get(netdev);
  568. IN_DEV_CONF_SET(in_dev, ARP_IGNORE, 1);
  569. in_dev_put(in_dev);
  570. return 0;
  571. bail1:
  572. c2_rx_clean(c2_port);
  573. kfree(c2_port->rx_ring.start);
  574. bail0:
  575. pci_free_consistent(c2dev->pcidev, c2_port->mem_size, c2_port->mem,
  576. c2_port->dma);
  577. return ret;
  578. }
  579. static int c2_down(struct net_device *netdev)
  580. {
  581. struct c2_port *c2_port = netdev_priv(netdev);
  582. struct c2_dev *c2dev = c2_port->c2dev;
  583. if (netif_msg_ifdown(c2_port))
  584. pr_debug("%s: disabling interface\n",
  585. netdev->name);
  586. /* Wait for all the queued packets to get sent */
  587. c2_tx_interrupt(netdev);
  588. /* Disable network packets */
  589. netif_stop_queue(netdev);
  590. /* Disable IRQs by clearing the interrupt mask */
  591. writel(1, c2dev->regs + C2_IDIS);
  592. writel(0, c2dev->regs + C2_NIMR0);
  593. /* missing: Stop transmitter */
  594. /* missing: Stop receiver */
  595. /* Reset the adapter, ensures the driver is in sync with the RXP */
  596. c2_reset(c2_port);
  597. /* missing: Turn off LEDs here */
  598. /* Free all buffers in the host descriptor rings */
  599. c2_tx_clean(c2_port);
  600. c2_rx_clean(c2_port);
  601. /* Free the host descriptor rings */
  602. kfree(c2_port->rx_ring.start);
  603. kfree(c2_port->tx_ring.start);
  604. pci_free_consistent(c2dev->pcidev, c2_port->mem_size, c2_port->mem,
  605. c2_port->dma);
  606. return 0;
  607. }
  608. static void c2_reset(struct c2_port *c2_port)
  609. {
  610. struct c2_dev *c2dev = c2_port->c2dev;
  611. unsigned int cur_rx = c2dev->cur_rx;
  612. /* Tell the hardware to quiesce */
  613. C2_SET_CUR_RX(c2dev, cur_rx | C2_PCI_HRX_QUI);
  614. /*
  615. * The hardware will reset the C2_PCI_HRX_QUI bit once
  616. * the RXP is quiesced. Wait 2 seconds for this.
  617. */
  618. ssleep(2);
  619. cur_rx = C2_GET_CUR_RX(c2dev);
  620. if (cur_rx & C2_PCI_HRX_QUI)
  621. pr_debug("c2_reset: failed to quiesce the hardware!\n");
  622. cur_rx &= ~C2_PCI_HRX_QUI;
  623. c2dev->cur_rx = cur_rx;
  624. pr_debug("Current RX: %u\n", c2dev->cur_rx);
  625. }
  626. static int c2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
  627. {
  628. struct c2_port *c2_port = netdev_priv(netdev);
  629. struct c2_dev *c2dev = c2_port->c2dev;
  630. struct c2_ring *tx_ring = &c2_port->tx_ring;
  631. struct c2_element *elem;
  632. dma_addr_t mapaddr;
  633. u32 maplen;
  634. unsigned long flags;
  635. unsigned int i;
  636. spin_lock_irqsave(&c2_port->tx_lock, flags);
  637. if (unlikely(c2_port->tx_avail < (skb_shinfo(skb)->nr_frags + 1))) {
  638. netif_stop_queue(netdev);
  639. spin_unlock_irqrestore(&c2_port->tx_lock, flags);
  640. pr_debug("%s: Tx ring full when queue awake!\n",
  641. netdev->name);
  642. return NETDEV_TX_BUSY;
  643. }
  644. maplen = skb_headlen(skb);
  645. mapaddr =
  646. pci_map_single(c2dev->pcidev, skb->data, maplen, PCI_DMA_TODEVICE);
  647. elem = tx_ring->to_use;
  648. elem->skb = skb;
  649. elem->mapaddr = mapaddr;
  650. elem->maplen = maplen;
  651. /* Tell HW to xmit */
  652. __raw_writeq((__force u64) cpu_to_be64(mapaddr),
  653. elem->hw_desc + C2_TXP_ADDR);
  654. __raw_writew((__force u16) cpu_to_be16(maplen),
  655. elem->hw_desc + C2_TXP_LEN);
  656. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_READY),
  657. elem->hw_desc + C2_TXP_FLAGS);
  658. c2_port->netstats.tx_packets++;
  659. c2_port->netstats.tx_bytes += maplen;
  660. /* Loop thru additional data fragments and queue them */
  661. if (skb_shinfo(skb)->nr_frags) {
  662. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  663. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  664. maplen = frag->size;
  665. mapaddr =
  666. pci_map_page(c2dev->pcidev, frag->page,
  667. frag->page_offset, maplen,
  668. PCI_DMA_TODEVICE);
  669. elem = elem->next;
  670. elem->skb = NULL;
  671. elem->mapaddr = mapaddr;
  672. elem->maplen = maplen;
  673. /* Tell HW to xmit */
  674. __raw_writeq((__force u64) cpu_to_be64(mapaddr),
  675. elem->hw_desc + C2_TXP_ADDR);
  676. __raw_writew((__force u16) cpu_to_be16(maplen),
  677. elem->hw_desc + C2_TXP_LEN);
  678. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_READY),
  679. elem->hw_desc + C2_TXP_FLAGS);
  680. c2_port->netstats.tx_packets++;
  681. c2_port->netstats.tx_bytes += maplen;
  682. }
  683. }
  684. tx_ring->to_use = elem->next;
  685. c2_port->tx_avail -= (skb_shinfo(skb)->nr_frags + 1);
  686. if (c2_port->tx_avail <= MAX_SKB_FRAGS + 1) {
  687. netif_stop_queue(netdev);
  688. if (netif_msg_tx_queued(c2_port))
  689. pr_debug("%s: transmit queue full\n",
  690. netdev->name);
  691. }
  692. spin_unlock_irqrestore(&c2_port->tx_lock, flags);
  693. netdev->trans_start = jiffies;
  694. return NETDEV_TX_OK;
  695. }
  696. static struct net_device_stats *c2_get_stats(struct net_device *netdev)
  697. {
  698. struct c2_port *c2_port = netdev_priv(netdev);
  699. return &c2_port->netstats;
  700. }
  701. static void c2_tx_timeout(struct net_device *netdev)
  702. {
  703. struct c2_port *c2_port = netdev_priv(netdev);
  704. if (netif_msg_timer(c2_port))
  705. pr_debug("%s: tx timeout\n", netdev->name);
  706. c2_tx_clean(c2_port);
  707. }
  708. static int c2_change_mtu(struct net_device *netdev, int new_mtu)
  709. {
  710. int ret = 0;
  711. if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
  712. return -EINVAL;
  713. netdev->mtu = new_mtu;
  714. if (netif_running(netdev)) {
  715. c2_down(netdev);
  716. c2_up(netdev);
  717. }
  718. return ret;
  719. }
  720. /* Initialize network device */
  721. static struct net_device *c2_devinit(struct c2_dev *c2dev,
  722. void __iomem * mmio_addr)
  723. {
  724. struct c2_port *c2_port = NULL;
  725. struct net_device *netdev = alloc_etherdev(sizeof(*c2_port));
  726. if (!netdev) {
  727. pr_debug("c2_port etherdev alloc failed");
  728. return NULL;
  729. }
  730. SET_NETDEV_DEV(netdev, &c2dev->pcidev->dev);
  731. netdev->open = c2_up;
  732. netdev->stop = c2_down;
  733. netdev->hard_start_xmit = c2_xmit_frame;
  734. netdev->get_stats = c2_get_stats;
  735. netdev->tx_timeout = c2_tx_timeout;
  736. netdev->change_mtu = c2_change_mtu;
  737. netdev->watchdog_timeo = C2_TX_TIMEOUT;
  738. netdev->irq = c2dev->pcidev->irq;
  739. c2_port = netdev_priv(netdev);
  740. c2_port->netdev = netdev;
  741. c2_port->c2dev = c2dev;
  742. c2_port->msg_enable = netif_msg_init(debug, default_msg);
  743. c2_port->tx_ring.count = C2_NUM_TX_DESC;
  744. c2_port->rx_ring.count = C2_NUM_RX_DESC;
  745. spin_lock_init(&c2_port->tx_lock);
  746. /* Copy our 48-bit ethernet hardware address */
  747. memcpy_fromio(netdev->dev_addr, mmio_addr + C2_REGS_ENADDR, 6);
  748. /* Validate the MAC address */
  749. if (!is_valid_ether_addr(netdev->dev_addr)) {
  750. pr_debug("Invalid MAC Address\n");
  751. c2_print_macaddr(netdev);
  752. free_netdev(netdev);
  753. return NULL;
  754. }
  755. c2dev->netdev = netdev;
  756. return netdev;
  757. }
  758. static int __devinit c2_probe(struct pci_dev *pcidev,
  759. const struct pci_device_id *ent)
  760. {
  761. int ret = 0, i;
  762. unsigned long reg0_start, reg0_flags, reg0_len;
  763. unsigned long reg2_start, reg2_flags, reg2_len;
  764. unsigned long reg4_start, reg4_flags, reg4_len;
  765. unsigned kva_map_size;
  766. struct net_device *netdev = NULL;
  767. struct c2_dev *c2dev = NULL;
  768. void __iomem *mmio_regs = NULL;
  769. printk(KERN_INFO PFX "AMSO1100 Gigabit Ethernet driver v%s loaded\n",
  770. DRV_VERSION);
  771. /* Enable PCI device */
  772. ret = pci_enable_device(pcidev);
  773. if (ret) {
  774. printk(KERN_ERR PFX "%s: Unable to enable PCI device\n",
  775. pci_name(pcidev));
  776. goto bail0;
  777. }
  778. reg0_start = pci_resource_start(pcidev, BAR_0);
  779. reg0_len = pci_resource_len(pcidev, BAR_0);
  780. reg0_flags = pci_resource_flags(pcidev, BAR_0);
  781. reg2_start = pci_resource_start(pcidev, BAR_2);
  782. reg2_len = pci_resource_len(pcidev, BAR_2);
  783. reg2_flags = pci_resource_flags(pcidev, BAR_2);
  784. reg4_start = pci_resource_start(pcidev, BAR_4);
  785. reg4_len = pci_resource_len(pcidev, BAR_4);
  786. reg4_flags = pci_resource_flags(pcidev, BAR_4);
  787. pr_debug("BAR0 size = 0x%lX bytes\n", reg0_len);
  788. pr_debug("BAR2 size = 0x%lX bytes\n", reg2_len);
  789. pr_debug("BAR4 size = 0x%lX bytes\n", reg4_len);
  790. /* Make sure PCI base addr are MMIO */
  791. if (!(reg0_flags & IORESOURCE_MEM) ||
  792. !(reg2_flags & IORESOURCE_MEM) || !(reg4_flags & IORESOURCE_MEM)) {
  793. printk(KERN_ERR PFX "PCI regions not an MMIO resource\n");
  794. ret = -ENODEV;
  795. goto bail1;
  796. }
  797. /* Check for weird/broken PCI region reporting */
  798. if ((reg0_len < C2_REG0_SIZE) ||
  799. (reg2_len < C2_REG2_SIZE) || (reg4_len < C2_REG4_SIZE)) {
  800. printk(KERN_ERR PFX "Invalid PCI region sizes\n");
  801. ret = -ENODEV;
  802. goto bail1;
  803. }
  804. /* Reserve PCI I/O and memory resources */
  805. ret = pci_request_regions(pcidev, DRV_NAME);
  806. if (ret) {
  807. printk(KERN_ERR PFX "%s: Unable to request regions\n",
  808. pci_name(pcidev));
  809. goto bail1;
  810. }
  811. if ((sizeof(dma_addr_t) > 4)) {
  812. ret = pci_set_dma_mask(pcidev, DMA_64BIT_MASK);
  813. if (ret < 0) {
  814. printk(KERN_ERR PFX "64b DMA configuration failed\n");
  815. goto bail2;
  816. }
  817. } else {
  818. ret = pci_set_dma_mask(pcidev, DMA_32BIT_MASK);
  819. if (ret < 0) {
  820. printk(KERN_ERR PFX "32b DMA configuration failed\n");
  821. goto bail2;
  822. }
  823. }
  824. /* Enables bus-mastering on the device */
  825. pci_set_master(pcidev);
  826. /* Remap the adapter PCI registers in BAR4 */
  827. mmio_regs = ioremap_nocache(reg4_start + C2_PCI_REGS_OFFSET,
  828. sizeof(struct c2_adapter_pci_regs));
  829. if (!mmio_regs) {
  830. printk(KERN_ERR PFX
  831. "Unable to remap adapter PCI registers in BAR4\n");
  832. ret = -EIO;
  833. goto bail2;
  834. }
  835. /* Validate PCI regs magic */
  836. for (i = 0; i < sizeof(c2_magic); i++) {
  837. if (c2_magic[i] != readb(mmio_regs + C2_REGS_MAGIC + i)) {
  838. printk(KERN_ERR PFX "Downlevel Firmware boot loader "
  839. "[%d/%Zd: got 0x%x, exp 0x%x]. Use the cc_flash "
  840. "utility to update your boot loader\n",
  841. i + 1, sizeof(c2_magic),
  842. readb(mmio_regs + C2_REGS_MAGIC + i),
  843. c2_magic[i]);
  844. printk(KERN_ERR PFX "Adapter not claimed\n");
  845. iounmap(mmio_regs);
  846. ret = -EIO;
  847. goto bail2;
  848. }
  849. }
  850. /* Validate the adapter version */
  851. if (be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_VERS)) != C2_VERSION) {
  852. printk(KERN_ERR PFX "Version mismatch "
  853. "[fw=%u, c2=%u], Adapter not claimed\n",
  854. be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_VERS)),
  855. C2_VERSION);
  856. ret = -EINVAL;
  857. iounmap(mmio_regs);
  858. goto bail2;
  859. }
  860. /* Validate the adapter IVN */
  861. if (be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_IVN)) != C2_IVN) {
  862. printk(KERN_ERR PFX "Downlevel FIrmware level. You should be using "
  863. "the OpenIB device support kit. "
  864. "[fw=0x%x, c2=0x%x], Adapter not claimed\n",
  865. be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_IVN)),
  866. C2_IVN);
  867. ret = -EINVAL;
  868. iounmap(mmio_regs);
  869. goto bail2;
  870. }
  871. /* Allocate hardware structure */
  872. c2dev = (struct c2_dev *) ib_alloc_device(sizeof(*c2dev));
  873. if (!c2dev) {
  874. printk(KERN_ERR PFX "%s: Unable to alloc hardware struct\n",
  875. pci_name(pcidev));
  876. ret = -ENOMEM;
  877. iounmap(mmio_regs);
  878. goto bail2;
  879. }
  880. memset(c2dev, 0, sizeof(*c2dev));
  881. spin_lock_init(&c2dev->lock);
  882. c2dev->pcidev = pcidev;
  883. c2dev->cur_tx = 0;
  884. /* Get the last RX index */
  885. c2dev->cur_rx =
  886. (be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_HRX_CUR)) -
  887. 0xffffc000) / sizeof(struct c2_rxp_desc);
  888. /* Request an interrupt line for the driver */
  889. ret = request_irq(pcidev->irq, c2_interrupt, IRQF_SHARED, DRV_NAME, c2dev);
  890. if (ret) {
  891. printk(KERN_ERR PFX "%s: requested IRQ %u is busy\n",
  892. pci_name(pcidev), pcidev->irq);
  893. iounmap(mmio_regs);
  894. goto bail3;
  895. }
  896. /* Set driver specific data */
  897. pci_set_drvdata(pcidev, c2dev);
  898. /* Initialize network device */
  899. if ((netdev = c2_devinit(c2dev, mmio_regs)) == NULL) {
  900. iounmap(mmio_regs);
  901. goto bail4;
  902. }
  903. /* Save off the actual size prior to unmapping mmio_regs */
  904. kva_map_size = be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_PCI_WINSIZE));
  905. /* Unmap the adapter PCI registers in BAR4 */
  906. iounmap(mmio_regs);
  907. /* Register network device */
  908. ret = register_netdev(netdev);
  909. if (ret) {
  910. printk(KERN_ERR PFX "Unable to register netdev, ret = %d\n",
  911. ret);
  912. goto bail5;
  913. }
  914. /* Disable network packets */
  915. netif_stop_queue(netdev);
  916. /* Remap the adapter HRXDQ PA space to kernel VA space */
  917. c2dev->mmio_rxp_ring = ioremap_nocache(reg4_start + C2_RXP_HRXDQ_OFFSET,
  918. C2_RXP_HRXDQ_SIZE);
  919. if (!c2dev->mmio_rxp_ring) {
  920. printk(KERN_ERR PFX "Unable to remap MMIO HRXDQ region\n");
  921. ret = -EIO;
  922. goto bail6;
  923. }
  924. /* Remap the adapter HTXDQ PA space to kernel VA space */
  925. c2dev->mmio_txp_ring = ioremap_nocache(reg4_start + C2_TXP_HTXDQ_OFFSET,
  926. C2_TXP_HTXDQ_SIZE);
  927. if (!c2dev->mmio_txp_ring) {
  928. printk(KERN_ERR PFX "Unable to remap MMIO HTXDQ region\n");
  929. ret = -EIO;
  930. goto bail7;
  931. }
  932. /* Save off the current RX index in the last 4 bytes of the TXP Ring */
  933. C2_SET_CUR_RX(c2dev, c2dev->cur_rx);
  934. /* Remap the PCI registers in adapter BAR0 to kernel VA space */
  935. c2dev->regs = ioremap_nocache(reg0_start, reg0_len);
  936. if (!c2dev->regs) {
  937. printk(KERN_ERR PFX "Unable to remap BAR0\n");
  938. ret = -EIO;
  939. goto bail8;
  940. }
  941. /* Remap the PCI registers in adapter BAR4 to kernel VA space */
  942. c2dev->pa = reg4_start + C2_PCI_REGS_OFFSET;
  943. c2dev->kva = ioremap_nocache(reg4_start + C2_PCI_REGS_OFFSET,
  944. kva_map_size);
  945. if (!c2dev->kva) {
  946. printk(KERN_ERR PFX "Unable to remap BAR4\n");
  947. ret = -EIO;
  948. goto bail9;
  949. }
  950. /* Print out the MAC address */
  951. c2_print_macaddr(netdev);
  952. ret = c2_rnic_init(c2dev);
  953. if (ret) {
  954. printk(KERN_ERR PFX "c2_rnic_init failed: %d\n", ret);
  955. goto bail10;
  956. }
  957. if (c2_register_device(c2dev))
  958. goto bail10;
  959. return 0;
  960. bail10:
  961. iounmap(c2dev->kva);
  962. bail9:
  963. iounmap(c2dev->regs);
  964. bail8:
  965. iounmap(c2dev->mmio_txp_ring);
  966. bail7:
  967. iounmap(c2dev->mmio_rxp_ring);
  968. bail6:
  969. unregister_netdev(netdev);
  970. bail5:
  971. free_netdev(netdev);
  972. bail4:
  973. free_irq(pcidev->irq, c2dev);
  974. bail3:
  975. ib_dealloc_device(&c2dev->ibdev);
  976. bail2:
  977. pci_release_regions(pcidev);
  978. bail1:
  979. pci_disable_device(pcidev);
  980. bail0:
  981. return ret;
  982. }
  983. static void __devexit c2_remove(struct pci_dev *pcidev)
  984. {
  985. struct c2_dev *c2dev = pci_get_drvdata(pcidev);
  986. struct net_device *netdev = c2dev->netdev;
  987. /* Unregister with OpenIB */
  988. c2_unregister_device(c2dev);
  989. /* Clean up the RNIC resources */
  990. c2_rnic_term(c2dev);
  991. /* Remove network device from the kernel */
  992. unregister_netdev(netdev);
  993. /* Free network device */
  994. free_netdev(netdev);
  995. /* Free the interrupt line */
  996. free_irq(pcidev->irq, c2dev);
  997. /* missing: Turn LEDs off here */
  998. /* Unmap adapter PA space */
  999. iounmap(c2dev->kva);
  1000. iounmap(c2dev->regs);
  1001. iounmap(c2dev->mmio_txp_ring);
  1002. iounmap(c2dev->mmio_rxp_ring);
  1003. /* Free the hardware structure */
  1004. ib_dealloc_device(&c2dev->ibdev);
  1005. /* Release reserved PCI I/O and memory resources */
  1006. pci_release_regions(pcidev);
  1007. /* Disable PCI device */
  1008. pci_disable_device(pcidev);
  1009. /* Clear driver specific data */
  1010. pci_set_drvdata(pcidev, NULL);
  1011. }
  1012. static struct pci_driver c2_pci_driver = {
  1013. .name = DRV_NAME,
  1014. .id_table = c2_pci_table,
  1015. .probe = c2_probe,
  1016. .remove = __devexit_p(c2_remove),
  1017. };
  1018. static int __init c2_init_module(void)
  1019. {
  1020. return pci_register_driver(&c2_pci_driver);
  1021. }
  1022. static void __exit c2_exit_module(void)
  1023. {
  1024. pci_unregister_driver(&c2_pci_driver);
  1025. }
  1026. module_init(c2_init_module);
  1027. module_exit(c2_exit_module);