video1394.c 42 KB

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  1. /*
  2. * video1394.c - video driver for OHCI 1394 boards
  3. * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
  4. * Peter Schlaile <udbz@rz.uni-karlsruhe.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software Foundation,
  18. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. * NOTES:
  21. *
  22. * ioctl return codes:
  23. * EFAULT is only for invalid address for the argp
  24. * EINVAL for out of range values
  25. * EBUSY when trying to use an already used resource
  26. * ESRCH when trying to free/stop a not used resource
  27. * EAGAIN for resource allocation failure that could perhaps succeed later
  28. * ENOTTY for unsupported ioctl request
  29. *
  30. */
  31. #include <linux/kernel.h>
  32. #include <linux/list.h>
  33. #include <linux/slab.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/wait.h>
  36. #include <linux/errno.h>
  37. #include <linux/module.h>
  38. #include <linux/init.h>
  39. #include <linux/pci.h>
  40. #include <linux/fs.h>
  41. #include <linux/poll.h>
  42. #include <linux/delay.h>
  43. #include <linux/bitops.h>
  44. #include <linux/types.h>
  45. #include <linux/vmalloc.h>
  46. #include <linux/timex.h>
  47. #include <linux/mm.h>
  48. #include <linux/compat.h>
  49. #include <linux/cdev.h>
  50. #include "dma.h"
  51. #include "highlevel.h"
  52. #include "hosts.h"
  53. #include "ieee1394.h"
  54. #include "ieee1394_core.h"
  55. #include "ieee1394_hotplug.h"
  56. #include "ieee1394_types.h"
  57. #include "nodemgr.h"
  58. #include "ohci1394.h"
  59. #include "video1394.h"
  60. #define ISO_CHANNELS 64
  61. struct it_dma_prg {
  62. struct dma_cmd begin;
  63. quadlet_t data[4];
  64. struct dma_cmd end;
  65. quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
  66. };
  67. struct dma_iso_ctx {
  68. struct ti_ohci *ohci;
  69. int type; /* OHCI_ISO_TRANSMIT or OHCI_ISO_RECEIVE */
  70. struct ohci1394_iso_tasklet iso_tasklet;
  71. int channel;
  72. int ctx;
  73. int last_buffer;
  74. int * next_buffer; /* For ISO Transmit of video packets
  75. to write the correct SYT field
  76. into the next block */
  77. unsigned int num_desc;
  78. unsigned int buf_size;
  79. unsigned int frame_size;
  80. unsigned int packet_size;
  81. unsigned int left_size;
  82. unsigned int nb_cmd;
  83. struct dma_region dma;
  84. struct dma_prog_region *prg_reg;
  85. struct dma_cmd **ir_prg;
  86. struct it_dma_prg **it_prg;
  87. unsigned int *buffer_status;
  88. unsigned int *buffer_prg_assignment;
  89. struct timeval *buffer_time; /* time when the buffer was received */
  90. unsigned int *last_used_cmd; /* For ISO Transmit with
  91. variable sized packets only ! */
  92. int ctrlClear;
  93. int ctrlSet;
  94. int cmdPtr;
  95. int ctxMatch;
  96. wait_queue_head_t waitq;
  97. spinlock_t lock;
  98. unsigned int syt_offset;
  99. int flags;
  100. struct list_head link;
  101. };
  102. struct file_ctx {
  103. struct ti_ohci *ohci;
  104. struct list_head context_list;
  105. struct dma_iso_ctx *current_ctx;
  106. };
  107. #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
  108. #define VIDEO1394_DEBUG
  109. #endif
  110. #ifdef DBGMSG
  111. #undef DBGMSG
  112. #endif
  113. #ifdef VIDEO1394_DEBUG
  114. #define DBGMSG(card, fmt, args...) \
  115. printk(KERN_INFO "video1394_%d: " fmt "\n" , card , ## args)
  116. #else
  117. #define DBGMSG(card, fmt, args...) do {} while (0)
  118. #endif
  119. /* print general (card independent) information */
  120. #define PRINT_G(level, fmt, args...) \
  121. printk(level "video1394: " fmt "\n" , ## args)
  122. /* print card specific information */
  123. #define PRINT(level, card, fmt, args...) \
  124. printk(level "video1394_%d: " fmt "\n" , card , ## args)
  125. static void wakeup_dma_ir_ctx(unsigned long l);
  126. static void wakeup_dma_it_ctx(unsigned long l);
  127. static struct hpsb_highlevel video1394_highlevel;
  128. static int free_dma_iso_ctx(struct dma_iso_ctx *d)
  129. {
  130. int i;
  131. DBGMSG(d->ohci->host->id, "Freeing dma_iso_ctx %d", d->ctx);
  132. ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
  133. if (d->iso_tasklet.link.next != NULL)
  134. ohci1394_unregister_iso_tasklet(d->ohci, &d->iso_tasklet);
  135. dma_region_free(&d->dma);
  136. if (d->prg_reg) {
  137. for (i = 0; i < d->num_desc; i++)
  138. dma_prog_region_free(&d->prg_reg[i]);
  139. kfree(d->prg_reg);
  140. }
  141. kfree(d->ir_prg);
  142. kfree(d->it_prg);
  143. kfree(d->buffer_status);
  144. kfree(d->buffer_prg_assignment);
  145. kfree(d->buffer_time);
  146. kfree(d->last_used_cmd);
  147. kfree(d->next_buffer);
  148. list_del(&d->link);
  149. kfree(d);
  150. return 0;
  151. }
  152. static struct dma_iso_ctx *
  153. alloc_dma_iso_ctx(struct ti_ohci *ohci, int type, int num_desc,
  154. int buf_size, int channel, unsigned int packet_size)
  155. {
  156. struct dma_iso_ctx *d;
  157. int i;
  158. d = kzalloc(sizeof(*d), GFP_KERNEL);
  159. if (!d) {
  160. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma_iso_ctx");
  161. return NULL;
  162. }
  163. d->ohci = ohci;
  164. d->type = type;
  165. d->channel = channel;
  166. d->num_desc = num_desc;
  167. d->frame_size = buf_size;
  168. d->buf_size = PAGE_ALIGN(buf_size);
  169. d->last_buffer = -1;
  170. INIT_LIST_HEAD(&d->link);
  171. init_waitqueue_head(&d->waitq);
  172. /* Init the regions for easy cleanup */
  173. dma_region_init(&d->dma);
  174. if (dma_region_alloc(&d->dma, (d->num_desc - 1) * d->buf_size, ohci->dev,
  175. PCI_DMA_BIDIRECTIONAL)) {
  176. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma buffer");
  177. free_dma_iso_ctx(d);
  178. return NULL;
  179. }
  180. if (type == OHCI_ISO_RECEIVE)
  181. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  182. wakeup_dma_ir_ctx,
  183. (unsigned long) d);
  184. else
  185. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  186. wakeup_dma_it_ctx,
  187. (unsigned long) d);
  188. if (ohci1394_register_iso_tasklet(ohci, &d->iso_tasklet) < 0) {
  189. PRINT(KERN_ERR, ohci->host->id, "no free iso %s contexts",
  190. type == OHCI_ISO_RECEIVE ? "receive" : "transmit");
  191. free_dma_iso_ctx(d);
  192. return NULL;
  193. }
  194. d->ctx = d->iso_tasklet.context;
  195. d->prg_reg = kmalloc(d->num_desc * sizeof(*d->prg_reg), GFP_KERNEL);
  196. if (!d->prg_reg) {
  197. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate ir prg regs");
  198. free_dma_iso_ctx(d);
  199. return NULL;
  200. }
  201. /* Makes for easier cleanup */
  202. for (i = 0; i < d->num_desc; i++)
  203. dma_prog_region_init(&d->prg_reg[i]);
  204. if (type == OHCI_ISO_RECEIVE) {
  205. d->ctrlSet = OHCI1394_IsoRcvContextControlSet+32*d->ctx;
  206. d->ctrlClear = OHCI1394_IsoRcvContextControlClear+32*d->ctx;
  207. d->cmdPtr = OHCI1394_IsoRcvCommandPtr+32*d->ctx;
  208. d->ctxMatch = OHCI1394_IsoRcvContextMatch+32*d->ctx;
  209. d->ir_prg = kzalloc(d->num_desc * sizeof(*d->ir_prg),
  210. GFP_KERNEL);
  211. if (!d->ir_prg) {
  212. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  213. free_dma_iso_ctx(d);
  214. return NULL;
  215. }
  216. d->nb_cmd = d->buf_size / PAGE_SIZE + 1;
  217. d->left_size = (d->frame_size % PAGE_SIZE) ?
  218. d->frame_size % PAGE_SIZE : PAGE_SIZE;
  219. for (i = 0;i < d->num_desc; i++) {
  220. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  221. sizeof(struct dma_cmd), ohci->dev)) {
  222. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  223. free_dma_iso_ctx(d);
  224. return NULL;
  225. }
  226. d->ir_prg[i] = (struct dma_cmd *)d->prg_reg[i].kvirt;
  227. }
  228. } else { /* OHCI_ISO_TRANSMIT */
  229. d->ctrlSet = OHCI1394_IsoXmitContextControlSet+16*d->ctx;
  230. d->ctrlClear = OHCI1394_IsoXmitContextControlClear+16*d->ctx;
  231. d->cmdPtr = OHCI1394_IsoXmitCommandPtr+16*d->ctx;
  232. d->it_prg = kzalloc(d->num_desc * sizeof(*d->it_prg),
  233. GFP_KERNEL);
  234. if (!d->it_prg) {
  235. PRINT(KERN_ERR, ohci->host->id,
  236. "Failed to allocate dma it prg");
  237. free_dma_iso_ctx(d);
  238. return NULL;
  239. }
  240. d->packet_size = packet_size;
  241. if (PAGE_SIZE % packet_size || packet_size>4096) {
  242. PRINT(KERN_ERR, ohci->host->id,
  243. "Packet size %d (page_size: %ld) "
  244. "not yet supported\n",
  245. packet_size, PAGE_SIZE);
  246. free_dma_iso_ctx(d);
  247. return NULL;
  248. }
  249. d->nb_cmd = d->frame_size / d->packet_size;
  250. if (d->frame_size % d->packet_size) {
  251. d->nb_cmd++;
  252. d->left_size = d->frame_size % d->packet_size;
  253. } else
  254. d->left_size = d->packet_size;
  255. for (i = 0; i < d->num_desc; i++) {
  256. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  257. sizeof(struct it_dma_prg), ohci->dev)) {
  258. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma it prg");
  259. free_dma_iso_ctx(d);
  260. return NULL;
  261. }
  262. d->it_prg[i] = (struct it_dma_prg *)d->prg_reg[i].kvirt;
  263. }
  264. }
  265. d->buffer_status =
  266. kzalloc(d->num_desc * sizeof(*d->buffer_status), GFP_KERNEL);
  267. d->buffer_prg_assignment =
  268. kzalloc(d->num_desc * sizeof(*d->buffer_prg_assignment), GFP_KERNEL);
  269. d->buffer_time =
  270. kzalloc(d->num_desc * sizeof(*d->buffer_time), GFP_KERNEL);
  271. d->last_used_cmd =
  272. kzalloc(d->num_desc * sizeof(*d->last_used_cmd), GFP_KERNEL);
  273. d->next_buffer =
  274. kzalloc(d->num_desc * sizeof(*d->next_buffer), GFP_KERNEL);
  275. if (!d->buffer_status || !d->buffer_prg_assignment || !d->buffer_time ||
  276. !d->last_used_cmd || !d->next_buffer) {
  277. PRINT(KERN_ERR, ohci->host->id,
  278. "Failed to allocate dma_iso_ctx member");
  279. free_dma_iso_ctx(d);
  280. return NULL;
  281. }
  282. spin_lock_init(&d->lock);
  283. DBGMSG(ohci->host->id, "Iso %s DMA: %d buffers "
  284. "of size %d allocated for a frame size %d, each with %d prgs",
  285. (type == OHCI_ISO_RECEIVE) ? "receive" : "transmit",
  286. d->num_desc - 1, d->buf_size, d->frame_size, d->nb_cmd);
  287. return d;
  288. }
  289. static void reset_ir_status(struct dma_iso_ctx *d, int n)
  290. {
  291. int i;
  292. d->ir_prg[n][0].status = cpu_to_le32(4);
  293. d->ir_prg[n][1].status = cpu_to_le32(PAGE_SIZE-4);
  294. for (i = 2; i < d->nb_cmd - 1; i++)
  295. d->ir_prg[n][i].status = cpu_to_le32(PAGE_SIZE);
  296. d->ir_prg[n][i].status = cpu_to_le32(d->left_size);
  297. }
  298. static void reprogram_dma_ir_prg(struct dma_iso_ctx *d, int n, int buffer, int flags)
  299. {
  300. struct dma_cmd *ir_prg = d->ir_prg[n];
  301. unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
  302. int i;
  303. d->buffer_prg_assignment[n] = buffer;
  304. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  305. (unsigned long)d->dma.kvirt));
  306. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  307. (buf + 4) - (unsigned long)d->dma.kvirt));
  308. for (i=2;i<d->nb_cmd-1;i++) {
  309. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  310. (buf+(i-1)*PAGE_SIZE) -
  311. (unsigned long)d->dma.kvirt));
  312. }
  313. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  314. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  315. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  316. (buf+(i-1)*PAGE_SIZE) - (unsigned long)d->dma.kvirt));
  317. }
  318. static void initialize_dma_ir_prg(struct dma_iso_ctx *d, int n, int flags)
  319. {
  320. struct dma_cmd *ir_prg = d->ir_prg[n];
  321. struct dma_prog_region *ir_reg = &d->prg_reg[n];
  322. unsigned long buf = (unsigned long)d->dma.kvirt;
  323. int i;
  324. /* the first descriptor will read only 4 bytes */
  325. ir_prg[0].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  326. DMA_CTL_BRANCH | 4);
  327. /* set the sync flag */
  328. if (flags & VIDEO1394_SYNC_FRAMES)
  329. ir_prg[0].control |= cpu_to_le32(DMA_CTL_WAIT);
  330. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  331. (unsigned long)d->dma.kvirt));
  332. ir_prg[0].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  333. 1 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  334. /* If there is *not* only one DMA page per frame (hence, d->nb_cmd==2) */
  335. if (d->nb_cmd > 2) {
  336. /* The second descriptor will read PAGE_SIZE-4 bytes */
  337. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  338. DMA_CTL_BRANCH | (PAGE_SIZE-4));
  339. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf + 4) -
  340. (unsigned long)d->dma.kvirt));
  341. ir_prg[1].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  342. 2 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  343. for (i = 2; i < d->nb_cmd - 1; i++) {
  344. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  345. DMA_CTL_BRANCH | PAGE_SIZE);
  346. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  347. (buf+(i-1)*PAGE_SIZE) -
  348. (unsigned long)d->dma.kvirt));
  349. ir_prg[i].branchAddress =
  350. cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  351. (i + 1) * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  352. }
  353. /* The last descriptor will generate an interrupt */
  354. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  355. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  356. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  357. (buf+(i-1)*PAGE_SIZE) -
  358. (unsigned long)d->dma.kvirt));
  359. } else {
  360. /* Only one DMA page is used. Read d->left_size immediately and */
  361. /* generate an interrupt as this is also the last page. */
  362. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  363. DMA_CTL_IRQ | DMA_CTL_BRANCH | (d->left_size-4));
  364. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  365. (buf + 4) - (unsigned long)d->dma.kvirt));
  366. }
  367. }
  368. static void initialize_dma_ir_ctx(struct dma_iso_ctx *d, int tag, int flags)
  369. {
  370. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  371. int i;
  372. d->flags = flags;
  373. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  374. for (i=0;i<d->num_desc;i++) {
  375. initialize_dma_ir_prg(d, i, flags);
  376. reset_ir_status(d, i);
  377. }
  378. /* reset the ctrl register */
  379. reg_write(ohci, d->ctrlClear, 0xf0000000);
  380. /* Set bufferFill */
  381. reg_write(ohci, d->ctrlSet, 0x80000000);
  382. /* Set isoch header */
  383. if (flags & VIDEO1394_INCLUDE_ISO_HEADERS)
  384. reg_write(ohci, d->ctrlSet, 0x40000000);
  385. /* Set the context match register to match on all tags,
  386. sync for sync tag, and listen to d->channel */
  387. reg_write(ohci, d->ctxMatch, 0xf0000000|((tag&0xf)<<8)|d->channel);
  388. /* Set up isoRecvIntMask to generate interrupts */
  389. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1<<d->ctx);
  390. }
  391. /* find which context is listening to this channel */
  392. static struct dma_iso_ctx *
  393. find_ctx(struct list_head *list, int type, int channel)
  394. {
  395. struct dma_iso_ctx *ctx;
  396. list_for_each_entry(ctx, list, link) {
  397. if (ctx->type == type && ctx->channel == channel)
  398. return ctx;
  399. }
  400. return NULL;
  401. }
  402. static void wakeup_dma_ir_ctx(unsigned long l)
  403. {
  404. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  405. int i;
  406. spin_lock(&d->lock);
  407. for (i = 0; i < d->num_desc; i++) {
  408. if (d->ir_prg[i][d->nb_cmd-1].status & cpu_to_le32(0xFFFF0000)) {
  409. reset_ir_status(d, i);
  410. d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
  411. do_gettimeofday(&d->buffer_time[d->buffer_prg_assignment[i]]);
  412. dma_region_sync_for_cpu(&d->dma,
  413. d->buffer_prg_assignment[i] * d->buf_size,
  414. d->buf_size);
  415. }
  416. }
  417. spin_unlock(&d->lock);
  418. if (waitqueue_active(&d->waitq))
  419. wake_up_interruptible(&d->waitq);
  420. }
  421. static inline void put_timestamp(struct ti_ohci *ohci, struct dma_iso_ctx * d,
  422. int n)
  423. {
  424. unsigned char* buf = d->dma.kvirt + n * d->buf_size;
  425. u32 cycleTimer;
  426. u32 timeStamp;
  427. if (n == -1) {
  428. return;
  429. }
  430. cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  431. timeStamp = ((cycleTimer & 0x0fff) + d->syt_offset); /* 11059 = 450 us */
  432. timeStamp = (timeStamp % 3072 + ((timeStamp / 3072) << 12)
  433. + (cycleTimer & 0xf000)) & 0xffff;
  434. buf[6] = timeStamp >> 8;
  435. buf[7] = timeStamp & 0xff;
  436. /* if first packet is empty packet, then put timestamp into the next full one too */
  437. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  438. buf += d->packet_size;
  439. buf[6] = timeStamp >> 8;
  440. buf[7] = timeStamp & 0xff;
  441. }
  442. /* do the next buffer frame too in case of irq latency */
  443. n = d->next_buffer[n];
  444. if (n == -1) {
  445. return;
  446. }
  447. buf = d->dma.kvirt + n * d->buf_size;
  448. timeStamp += (d->last_used_cmd[n] << 12) & 0xffff;
  449. buf[6] = timeStamp >> 8;
  450. buf[7] = timeStamp & 0xff;
  451. /* if first packet is empty packet, then put timestamp into the next full one too */
  452. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  453. buf += d->packet_size;
  454. buf[6] = timeStamp >> 8;
  455. buf[7] = timeStamp & 0xff;
  456. }
  457. #if 0
  458. printk("curr: %d, next: %d, cycleTimer: %08x timeStamp: %08x\n",
  459. curr, n, cycleTimer, timeStamp);
  460. #endif
  461. }
  462. static void wakeup_dma_it_ctx(unsigned long l)
  463. {
  464. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  465. struct ti_ohci *ohci = d->ohci;
  466. int i;
  467. spin_lock(&d->lock);
  468. for (i = 0; i < d->num_desc; i++) {
  469. if (d->it_prg[i][d->last_used_cmd[i]].end.status &
  470. cpu_to_le32(0xFFFF0000)) {
  471. int next = d->next_buffer[i];
  472. put_timestamp(ohci, d, next);
  473. d->it_prg[i][d->last_used_cmd[i]].end.status = 0;
  474. d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
  475. }
  476. }
  477. spin_unlock(&d->lock);
  478. if (waitqueue_active(&d->waitq))
  479. wake_up_interruptible(&d->waitq);
  480. }
  481. static void reprogram_dma_it_prg(struct dma_iso_ctx *d, int n, int buffer)
  482. {
  483. struct it_dma_prg *it_prg = d->it_prg[n];
  484. unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
  485. int i;
  486. d->buffer_prg_assignment[n] = buffer;
  487. for (i=0;i<d->nb_cmd;i++) {
  488. it_prg[i].end.address =
  489. cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  490. (buf+i*d->packet_size) - (unsigned long)d->dma.kvirt));
  491. }
  492. }
  493. static void initialize_dma_it_prg(struct dma_iso_ctx *d, int n, int sync_tag)
  494. {
  495. struct it_dma_prg *it_prg = d->it_prg[n];
  496. struct dma_prog_region *it_reg = &d->prg_reg[n];
  497. unsigned long buf = (unsigned long)d->dma.kvirt;
  498. int i;
  499. d->last_used_cmd[n] = d->nb_cmd - 1;
  500. for (i=0;i<d->nb_cmd;i++) {
  501. it_prg[i].begin.control = cpu_to_le32(DMA_CTL_OUTPUT_MORE |
  502. DMA_CTL_IMMEDIATE | 8) ;
  503. it_prg[i].begin.address = 0;
  504. it_prg[i].begin.status = 0;
  505. it_prg[i].data[0] = cpu_to_le32(
  506. (IEEE1394_SPEED_100 << 16)
  507. | (/* tag */ 1 << 14)
  508. | (d->channel << 8)
  509. | (TCODE_ISO_DATA << 4));
  510. if (i==0) it_prg[i].data[0] |= cpu_to_le32(sync_tag);
  511. it_prg[i].data[1] = cpu_to_le32(d->packet_size << 16);
  512. it_prg[i].data[2] = 0;
  513. it_prg[i].data[3] = 0;
  514. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST |
  515. DMA_CTL_BRANCH);
  516. it_prg[i].end.address =
  517. cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf+i*d->packet_size) -
  518. (unsigned long)d->dma.kvirt));
  519. if (i<d->nb_cmd-1) {
  520. it_prg[i].end.control |= cpu_to_le32(d->packet_size);
  521. it_prg[i].begin.branchAddress =
  522. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  523. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  524. it_prg[i].end.branchAddress =
  525. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  526. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  527. } else {
  528. /* the last prg generates an interrupt */
  529. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  530. DMA_CTL_IRQ | d->left_size);
  531. /* the last prg doesn't branch */
  532. it_prg[i].begin.branchAddress = 0;
  533. it_prg[i].end.branchAddress = 0;
  534. }
  535. it_prg[i].end.status = 0;
  536. }
  537. }
  538. static void initialize_dma_it_prg_var_packet_queue(
  539. struct dma_iso_ctx *d, int n, unsigned int * packet_sizes,
  540. struct ti_ohci *ohci)
  541. {
  542. struct it_dma_prg *it_prg = d->it_prg[n];
  543. struct dma_prog_region *it_reg = &d->prg_reg[n];
  544. int i;
  545. #if 0
  546. if (n != -1) {
  547. put_timestamp(ohci, d, n);
  548. }
  549. #endif
  550. d->last_used_cmd[n] = d->nb_cmd - 1;
  551. for (i = 0; i < d->nb_cmd; i++) {
  552. unsigned int size;
  553. if (packet_sizes[i] > d->packet_size) {
  554. size = d->packet_size;
  555. } else {
  556. size = packet_sizes[i];
  557. }
  558. it_prg[i].data[1] = cpu_to_le32(size << 16);
  559. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH);
  560. if (i < d->nb_cmd-1 && packet_sizes[i+1] != 0) {
  561. it_prg[i].end.control |= cpu_to_le32(size);
  562. it_prg[i].begin.branchAddress =
  563. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  564. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  565. it_prg[i].end.branchAddress =
  566. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  567. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  568. } else {
  569. /* the last prg generates an interrupt */
  570. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  571. DMA_CTL_IRQ | size);
  572. /* the last prg doesn't branch */
  573. it_prg[i].begin.branchAddress = 0;
  574. it_prg[i].end.branchAddress = 0;
  575. d->last_used_cmd[n] = i;
  576. break;
  577. }
  578. }
  579. }
  580. static void initialize_dma_it_ctx(struct dma_iso_ctx *d, int sync_tag,
  581. unsigned int syt_offset, int flags)
  582. {
  583. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  584. int i;
  585. d->flags = flags;
  586. d->syt_offset = (syt_offset == 0 ? 11000 : syt_offset);
  587. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  588. for (i=0;i<d->num_desc;i++)
  589. initialize_dma_it_prg(d, i, sync_tag);
  590. /* Set up isoRecvIntMask to generate interrupts */
  591. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1<<d->ctx);
  592. }
  593. static inline unsigned video1394_buffer_state(struct dma_iso_ctx *d,
  594. unsigned int buffer)
  595. {
  596. unsigned long flags;
  597. unsigned int ret;
  598. spin_lock_irqsave(&d->lock, flags);
  599. ret = d->buffer_status[buffer];
  600. spin_unlock_irqrestore(&d->lock, flags);
  601. return ret;
  602. }
  603. static long video1394_ioctl(struct file *file,
  604. unsigned int cmd, unsigned long arg)
  605. {
  606. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  607. struct ti_ohci *ohci = ctx->ohci;
  608. unsigned long flags;
  609. void __user *argp = (void __user *)arg;
  610. switch(cmd)
  611. {
  612. case VIDEO1394_IOC_LISTEN_CHANNEL:
  613. case VIDEO1394_IOC_TALK_CHANNEL:
  614. {
  615. struct video1394_mmap v;
  616. u64 mask;
  617. struct dma_iso_ctx *d;
  618. int i;
  619. if (copy_from_user(&v, argp, sizeof(v)))
  620. return -EFAULT;
  621. /* if channel < 0, find lowest available one */
  622. if (v.channel < 0) {
  623. mask = (u64)0x1;
  624. for (i=0; ; i++) {
  625. if (i == ISO_CHANNELS) {
  626. PRINT(KERN_ERR, ohci->host->id,
  627. "No free channel found");
  628. return -EAGAIN;
  629. }
  630. if (!(ohci->ISO_channel_usage & mask)) {
  631. v.channel = i;
  632. PRINT(KERN_INFO, ohci->host->id, "Found free channel %d", i);
  633. break;
  634. }
  635. mask = mask << 1;
  636. }
  637. } else if (v.channel >= ISO_CHANNELS) {
  638. PRINT(KERN_ERR, ohci->host->id,
  639. "Iso channel %d out of bounds", v.channel);
  640. return -EINVAL;
  641. } else {
  642. mask = (u64)0x1<<v.channel;
  643. }
  644. DBGMSG(ohci->host->id, "mask: %08X%08X usage: %08X%08X\n",
  645. (u32)(mask>>32),(u32)(mask&0xffffffff),
  646. (u32)(ohci->ISO_channel_usage>>32),
  647. (u32)(ohci->ISO_channel_usage&0xffffffff));
  648. if (ohci->ISO_channel_usage & mask) {
  649. PRINT(KERN_ERR, ohci->host->id,
  650. "Channel %d is already taken", v.channel);
  651. return -EBUSY;
  652. }
  653. if (v.buf_size == 0 || v.buf_size > VIDEO1394_MAX_SIZE) {
  654. PRINT(KERN_ERR, ohci->host->id,
  655. "Invalid %d length buffer requested",v.buf_size);
  656. return -EINVAL;
  657. }
  658. if (v.nb_buffers == 0 || v.nb_buffers > VIDEO1394_MAX_SIZE) {
  659. PRINT(KERN_ERR, ohci->host->id,
  660. "Invalid %d buffers requested",v.nb_buffers);
  661. return -EINVAL;
  662. }
  663. if (v.nb_buffers * v.buf_size > VIDEO1394_MAX_SIZE) {
  664. PRINT(KERN_ERR, ohci->host->id,
  665. "%d buffers of size %d bytes is too big",
  666. v.nb_buffers, v.buf_size);
  667. return -EINVAL;
  668. }
  669. if (cmd == VIDEO1394_IOC_LISTEN_CHANNEL) {
  670. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_RECEIVE,
  671. v.nb_buffers + 1, v.buf_size,
  672. v.channel, 0);
  673. if (d == NULL) {
  674. PRINT(KERN_ERR, ohci->host->id,
  675. "Couldn't allocate ir context");
  676. return -EAGAIN;
  677. }
  678. initialize_dma_ir_ctx(d, v.sync_tag, v.flags);
  679. ctx->current_ctx = d;
  680. v.buf_size = d->buf_size;
  681. list_add_tail(&d->link, &ctx->context_list);
  682. DBGMSG(ohci->host->id,
  683. "iso context %d listen on channel %d",
  684. d->ctx, v.channel);
  685. }
  686. else {
  687. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_TRANSMIT,
  688. v.nb_buffers + 1, v.buf_size,
  689. v.channel, v.packet_size);
  690. if (d == NULL) {
  691. PRINT(KERN_ERR, ohci->host->id,
  692. "Couldn't allocate it context");
  693. return -EAGAIN;
  694. }
  695. initialize_dma_it_ctx(d, v.sync_tag,
  696. v.syt_offset, v.flags);
  697. ctx->current_ctx = d;
  698. v.buf_size = d->buf_size;
  699. list_add_tail(&d->link, &ctx->context_list);
  700. DBGMSG(ohci->host->id,
  701. "Iso context %d talk on channel %d", d->ctx,
  702. v.channel);
  703. }
  704. if (copy_to_user(argp, &v, sizeof(v))) {
  705. /* FIXME : free allocated dma resources */
  706. return -EFAULT;
  707. }
  708. ohci->ISO_channel_usage |= mask;
  709. return 0;
  710. }
  711. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  712. case VIDEO1394_IOC_UNTALK_CHANNEL:
  713. {
  714. int channel;
  715. u64 mask;
  716. struct dma_iso_ctx *d;
  717. if (copy_from_user(&channel, argp, sizeof(int)))
  718. return -EFAULT;
  719. if (channel < 0 || channel >= ISO_CHANNELS) {
  720. PRINT(KERN_ERR, ohci->host->id,
  721. "Iso channel %d out of bound", channel);
  722. return -EINVAL;
  723. }
  724. mask = (u64)0x1<<channel;
  725. if (!(ohci->ISO_channel_usage & mask)) {
  726. PRINT(KERN_ERR, ohci->host->id,
  727. "Channel %d is not being used", channel);
  728. return -ESRCH;
  729. }
  730. /* Mark this channel as unused */
  731. ohci->ISO_channel_usage &= ~mask;
  732. if (cmd == VIDEO1394_IOC_UNLISTEN_CHANNEL)
  733. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, channel);
  734. else
  735. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, channel);
  736. if (d == NULL) return -ESRCH;
  737. DBGMSG(ohci->host->id, "Iso context %d "
  738. "stop talking on channel %d", d->ctx, channel);
  739. free_dma_iso_ctx(d);
  740. return 0;
  741. }
  742. case VIDEO1394_IOC_LISTEN_QUEUE_BUFFER:
  743. {
  744. struct video1394_wait v;
  745. struct dma_iso_ctx *d;
  746. int next_prg;
  747. if (unlikely(copy_from_user(&v, argp, sizeof(v))))
  748. return -EFAULT;
  749. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  750. if (unlikely(d == NULL))
  751. return -EFAULT;
  752. if (unlikely((v.buffer<0) || (v.buffer>=d->num_desc - 1))) {
  753. PRINT(KERN_ERR, ohci->host->id,
  754. "Buffer %d out of range",v.buffer);
  755. return -EINVAL;
  756. }
  757. spin_lock_irqsave(&d->lock,flags);
  758. if (unlikely(d->buffer_status[v.buffer]==VIDEO1394_BUFFER_QUEUED)) {
  759. PRINT(KERN_ERR, ohci->host->id,
  760. "Buffer %d is already used",v.buffer);
  761. spin_unlock_irqrestore(&d->lock,flags);
  762. return -EBUSY;
  763. }
  764. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  765. next_prg = (d->last_buffer + 1) % d->num_desc;
  766. if (d->last_buffer>=0)
  767. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress =
  768. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0)
  769. & 0xfffffff0) | 0x1);
  770. d->last_buffer = next_prg;
  771. reprogram_dma_ir_prg(d, d->last_buffer, v.buffer, d->flags);
  772. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress = 0;
  773. spin_unlock_irqrestore(&d->lock,flags);
  774. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  775. {
  776. DBGMSG(ohci->host->id, "Starting iso DMA ctx=%d",d->ctx);
  777. /* Tell the controller where the first program is */
  778. reg_write(ohci, d->cmdPtr,
  779. dma_prog_region_offset_to_bus(&d->prg_reg[d->last_buffer], 0) | 0x1);
  780. /* Run IR context */
  781. reg_write(ohci, d->ctrlSet, 0x8000);
  782. }
  783. else {
  784. /* Wake up dma context if necessary */
  785. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  786. DBGMSG(ohci->host->id,
  787. "Waking up iso dma ctx=%d", d->ctx);
  788. reg_write(ohci, d->ctrlSet, 0x1000);
  789. }
  790. }
  791. return 0;
  792. }
  793. case VIDEO1394_IOC_LISTEN_WAIT_BUFFER:
  794. case VIDEO1394_IOC_LISTEN_POLL_BUFFER:
  795. {
  796. struct video1394_wait v;
  797. struct dma_iso_ctx *d;
  798. int i = 0;
  799. if (unlikely(copy_from_user(&v, argp, sizeof(v))))
  800. return -EFAULT;
  801. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  802. if (unlikely(d == NULL))
  803. return -EFAULT;
  804. if (unlikely((v.buffer<0) || (v.buffer>d->num_desc - 1))) {
  805. PRINT(KERN_ERR, ohci->host->id,
  806. "Buffer %d out of range",v.buffer);
  807. return -EINVAL;
  808. }
  809. /*
  810. * I change the way it works so that it returns
  811. * the last received frame.
  812. */
  813. spin_lock_irqsave(&d->lock, flags);
  814. switch(d->buffer_status[v.buffer]) {
  815. case VIDEO1394_BUFFER_READY:
  816. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  817. break;
  818. case VIDEO1394_BUFFER_QUEUED:
  819. if (cmd == VIDEO1394_IOC_LISTEN_POLL_BUFFER) {
  820. /* for polling, return error code EINTR */
  821. spin_unlock_irqrestore(&d->lock, flags);
  822. return -EINTR;
  823. }
  824. spin_unlock_irqrestore(&d->lock, flags);
  825. wait_event_interruptible(d->waitq,
  826. video1394_buffer_state(d, v.buffer) ==
  827. VIDEO1394_BUFFER_READY);
  828. if (signal_pending(current))
  829. return -EINTR;
  830. spin_lock_irqsave(&d->lock, flags);
  831. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  832. break;
  833. default:
  834. PRINT(KERN_ERR, ohci->host->id,
  835. "Buffer %d is not queued",v.buffer);
  836. spin_unlock_irqrestore(&d->lock, flags);
  837. return -ESRCH;
  838. }
  839. /* set time of buffer */
  840. v.filltime = d->buffer_time[v.buffer];
  841. /*
  842. * Look ahead to see how many more buffers have been received
  843. */
  844. i=0;
  845. while (d->buffer_status[(v.buffer+1)%(d->num_desc - 1)]==
  846. VIDEO1394_BUFFER_READY) {
  847. v.buffer=(v.buffer+1)%(d->num_desc - 1);
  848. i++;
  849. }
  850. spin_unlock_irqrestore(&d->lock, flags);
  851. v.buffer=i;
  852. if (unlikely(copy_to_user(argp, &v, sizeof(v))))
  853. return -EFAULT;
  854. return 0;
  855. }
  856. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  857. {
  858. struct video1394_wait v;
  859. unsigned int *psizes = NULL;
  860. struct dma_iso_ctx *d;
  861. int next_prg;
  862. if (copy_from_user(&v, argp, sizeof(v)))
  863. return -EFAULT;
  864. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  865. if (d == NULL) return -EFAULT;
  866. if ((v.buffer<0) || (v.buffer>=d->num_desc - 1)) {
  867. PRINT(KERN_ERR, ohci->host->id,
  868. "Buffer %d out of range",v.buffer);
  869. return -EINVAL;
  870. }
  871. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  872. int buf_size = d->nb_cmd * sizeof(*psizes);
  873. struct video1394_queue_variable __user *p = argp;
  874. unsigned int __user *qv;
  875. if (get_user(qv, &p->packet_sizes))
  876. return -EFAULT;
  877. psizes = kmalloc(buf_size, GFP_KERNEL);
  878. if (!psizes)
  879. return -ENOMEM;
  880. if (copy_from_user(psizes, qv, buf_size)) {
  881. kfree(psizes);
  882. return -EFAULT;
  883. }
  884. }
  885. spin_lock_irqsave(&d->lock,flags);
  886. /* last_buffer is last_prg */
  887. next_prg = (d->last_buffer + 1) % d->num_desc;
  888. if (d->buffer_status[v.buffer]!=VIDEO1394_BUFFER_FREE) {
  889. PRINT(KERN_ERR, ohci->host->id,
  890. "Buffer %d is already used",v.buffer);
  891. spin_unlock_irqrestore(&d->lock,flags);
  892. kfree(psizes);
  893. return -EBUSY;
  894. }
  895. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  896. initialize_dma_it_prg_var_packet_queue(
  897. d, next_prg, psizes, ohci);
  898. }
  899. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  900. if (d->last_buffer >= 0) {
  901. d->it_prg[d->last_buffer]
  902. [ d->last_used_cmd[d->last_buffer] ].end.branchAddress =
  903. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
  904. 0) & 0xfffffff0) | 0x3);
  905. d->it_prg[d->last_buffer]
  906. [ d->last_used_cmd[d->last_buffer] ].begin.branchAddress =
  907. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
  908. 0) & 0xfffffff0) | 0x3);
  909. d->next_buffer[d->last_buffer] = (v.buffer + 1) % (d->num_desc - 1);
  910. }
  911. d->last_buffer = next_prg;
  912. reprogram_dma_it_prg(d, d->last_buffer, v.buffer);
  913. d->next_buffer[d->last_buffer] = -1;
  914. d->it_prg[d->last_buffer][d->last_used_cmd[d->last_buffer]].end.branchAddress = 0;
  915. spin_unlock_irqrestore(&d->lock,flags);
  916. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  917. {
  918. DBGMSG(ohci->host->id, "Starting iso transmit DMA ctx=%d",
  919. d->ctx);
  920. put_timestamp(ohci, d, d->last_buffer);
  921. dma_region_sync_for_device(&d->dma,
  922. v.buffer * d->buf_size, d->buf_size);
  923. /* Tell the controller where the first program is */
  924. reg_write(ohci, d->cmdPtr,
  925. dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0) | 0x3);
  926. /* Run IT context */
  927. reg_write(ohci, d->ctrlSet, 0x8000);
  928. }
  929. else {
  930. /* Wake up dma context if necessary */
  931. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  932. DBGMSG(ohci->host->id,
  933. "Waking up iso transmit dma ctx=%d",
  934. d->ctx);
  935. put_timestamp(ohci, d, d->last_buffer);
  936. dma_region_sync_for_device(&d->dma,
  937. v.buffer * d->buf_size, d->buf_size);
  938. reg_write(ohci, d->ctrlSet, 0x1000);
  939. }
  940. }
  941. kfree(psizes);
  942. return 0;
  943. }
  944. case VIDEO1394_IOC_TALK_WAIT_BUFFER:
  945. {
  946. struct video1394_wait v;
  947. struct dma_iso_ctx *d;
  948. if (copy_from_user(&v, argp, sizeof(v)))
  949. return -EFAULT;
  950. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  951. if (d == NULL) return -EFAULT;
  952. if ((v.buffer<0) || (v.buffer>=d->num_desc-1)) {
  953. PRINT(KERN_ERR, ohci->host->id,
  954. "Buffer %d out of range",v.buffer);
  955. return -EINVAL;
  956. }
  957. switch(d->buffer_status[v.buffer]) {
  958. case VIDEO1394_BUFFER_READY:
  959. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  960. return 0;
  961. case VIDEO1394_BUFFER_QUEUED:
  962. wait_event_interruptible(d->waitq,
  963. (d->buffer_status[v.buffer] == VIDEO1394_BUFFER_READY));
  964. if (signal_pending(current))
  965. return -EINTR;
  966. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  967. return 0;
  968. default:
  969. PRINT(KERN_ERR, ohci->host->id,
  970. "Buffer %d is not queued",v.buffer);
  971. return -ESRCH;
  972. }
  973. }
  974. default:
  975. return -ENOTTY;
  976. }
  977. }
  978. /*
  979. * This maps the vmalloced and reserved buffer to user space.
  980. *
  981. * FIXME:
  982. * - PAGE_READONLY should suffice!?
  983. * - remap_pfn_range is kind of inefficient for page by page remapping.
  984. * But e.g. pte_alloc() does not work in modules ... :-(
  985. */
  986. static int video1394_mmap(struct file *file, struct vm_area_struct *vma)
  987. {
  988. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  989. if (ctx->current_ctx == NULL) {
  990. PRINT(KERN_ERR, ctx->ohci->host->id,
  991. "Current iso context not set");
  992. return -EINVAL;
  993. }
  994. return dma_region_mmap(&ctx->current_ctx->dma, file, vma);
  995. }
  996. static unsigned int video1394_poll(struct file *file, poll_table *pt)
  997. {
  998. struct file_ctx *ctx;
  999. unsigned int mask = 0;
  1000. unsigned long flags;
  1001. struct dma_iso_ctx *d;
  1002. int i;
  1003. ctx = file->private_data;
  1004. d = ctx->current_ctx;
  1005. if (d == NULL) {
  1006. PRINT(KERN_ERR, ctx->ohci->host->id,
  1007. "Current iso context not set");
  1008. return POLLERR;
  1009. }
  1010. poll_wait(file, &d->waitq, pt);
  1011. spin_lock_irqsave(&d->lock, flags);
  1012. for (i = 0; i < d->num_desc; i++) {
  1013. if (d->buffer_status[i] == VIDEO1394_BUFFER_READY) {
  1014. mask |= POLLIN | POLLRDNORM;
  1015. break;
  1016. }
  1017. }
  1018. spin_unlock_irqrestore(&d->lock, flags);
  1019. return mask;
  1020. }
  1021. static int video1394_open(struct inode *inode, struct file *file)
  1022. {
  1023. int i = ieee1394_file_to_instance(file);
  1024. struct ti_ohci *ohci;
  1025. struct file_ctx *ctx;
  1026. ohci = hpsb_get_hostinfo_bykey(&video1394_highlevel, i);
  1027. if (ohci == NULL)
  1028. return -EIO;
  1029. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  1030. if (!ctx) {
  1031. PRINT(KERN_ERR, ohci->host->id, "Cannot malloc file_ctx");
  1032. return -ENOMEM;
  1033. }
  1034. ctx->ohci = ohci;
  1035. INIT_LIST_HEAD(&ctx->context_list);
  1036. ctx->current_ctx = NULL;
  1037. file->private_data = ctx;
  1038. return 0;
  1039. }
  1040. static int video1394_release(struct inode *inode, struct file *file)
  1041. {
  1042. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  1043. struct ti_ohci *ohci = ctx->ohci;
  1044. struct list_head *lh, *next;
  1045. u64 mask;
  1046. list_for_each_safe(lh, next, &ctx->context_list) {
  1047. struct dma_iso_ctx *d;
  1048. d = list_entry(lh, struct dma_iso_ctx, link);
  1049. mask = (u64) 1 << d->channel;
  1050. if (!(ohci->ISO_channel_usage & mask))
  1051. PRINT(KERN_ERR, ohci->host->id, "On release: Channel %d "
  1052. "is not being used", d->channel);
  1053. else
  1054. ohci->ISO_channel_usage &= ~mask;
  1055. DBGMSG(ohci->host->id, "On release: Iso %s context "
  1056. "%d stop listening on channel %d",
  1057. d->type == OHCI_ISO_RECEIVE ? "receive" : "transmit",
  1058. d->ctx, d->channel);
  1059. free_dma_iso_ctx(d);
  1060. }
  1061. kfree(ctx);
  1062. file->private_data = NULL;
  1063. return 0;
  1064. }
  1065. #ifdef CONFIG_COMPAT
  1066. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg);
  1067. #endif
  1068. static struct cdev video1394_cdev;
  1069. static const struct file_operations video1394_fops=
  1070. {
  1071. .owner = THIS_MODULE,
  1072. .unlocked_ioctl = video1394_ioctl,
  1073. #ifdef CONFIG_COMPAT
  1074. .compat_ioctl = video1394_compat_ioctl,
  1075. #endif
  1076. .poll = video1394_poll,
  1077. .mmap = video1394_mmap,
  1078. .open = video1394_open,
  1079. .release = video1394_release
  1080. };
  1081. /*** HOTPLUG STUFF **********************************************************/
  1082. /*
  1083. * Export information about protocols/devices supported by this driver.
  1084. */
  1085. #ifdef MODULE
  1086. static struct ieee1394_device_id video1394_id_table[] = {
  1087. {
  1088. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1089. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1090. .version = CAMERA_SW_VERSION_ENTRY & 0xffffff
  1091. },
  1092. {
  1093. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1094. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1095. .version = (CAMERA_SW_VERSION_ENTRY + 1) & 0xffffff
  1096. },
  1097. {
  1098. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1099. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1100. .version = (CAMERA_SW_VERSION_ENTRY + 2) & 0xffffff
  1101. },
  1102. { }
  1103. };
  1104. MODULE_DEVICE_TABLE(ieee1394, video1394_id_table);
  1105. #endif /* MODULE */
  1106. static struct hpsb_protocol_driver video1394_driver = {
  1107. .name = VIDEO1394_DRIVER_NAME,
  1108. };
  1109. static void video1394_add_host (struct hpsb_host *host)
  1110. {
  1111. struct ti_ohci *ohci;
  1112. int minor;
  1113. /* We only work with the OHCI-1394 driver */
  1114. if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
  1115. return;
  1116. ohci = (struct ti_ohci *)host->hostdata;
  1117. if (!hpsb_create_hostinfo(&video1394_highlevel, host, 0)) {
  1118. PRINT(KERN_ERR, ohci->host->id, "Cannot allocate hostinfo");
  1119. return;
  1120. }
  1121. hpsb_set_hostinfo(&video1394_highlevel, host, ohci);
  1122. hpsb_set_hostinfo_key(&video1394_highlevel, host, ohci->host->id);
  1123. minor = IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id;
  1124. device_create_drvdata(hpsb_protocol_class, NULL,
  1125. MKDEV(IEEE1394_MAJOR, minor), NULL,
  1126. "%s-%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1127. }
  1128. static void video1394_remove_host (struct hpsb_host *host)
  1129. {
  1130. struct ti_ohci *ohci = hpsb_get_hostinfo(&video1394_highlevel, host);
  1131. if (ohci)
  1132. device_destroy(hpsb_protocol_class, MKDEV(IEEE1394_MAJOR,
  1133. IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id));
  1134. return;
  1135. }
  1136. static struct hpsb_highlevel video1394_highlevel = {
  1137. .name = VIDEO1394_DRIVER_NAME,
  1138. .add_host = video1394_add_host,
  1139. .remove_host = video1394_remove_host,
  1140. };
  1141. MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
  1142. MODULE_DESCRIPTION("driver for digital video on OHCI board");
  1143. MODULE_SUPPORTED_DEVICE(VIDEO1394_DRIVER_NAME);
  1144. MODULE_LICENSE("GPL");
  1145. #ifdef CONFIG_COMPAT
  1146. #define VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER \
  1147. _IOW ('#', 0x12, struct video1394_wait32)
  1148. #define VIDEO1394_IOC32_LISTEN_WAIT_BUFFER \
  1149. _IOWR('#', 0x13, struct video1394_wait32)
  1150. #define VIDEO1394_IOC32_TALK_WAIT_BUFFER \
  1151. _IOW ('#', 0x17, struct video1394_wait32)
  1152. #define VIDEO1394_IOC32_LISTEN_POLL_BUFFER \
  1153. _IOWR('#', 0x18, struct video1394_wait32)
  1154. struct video1394_wait32 {
  1155. u32 channel;
  1156. u32 buffer;
  1157. struct compat_timeval filltime;
  1158. };
  1159. static int video1394_wr_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1160. {
  1161. struct video1394_wait32 __user *argp = (void __user *)arg;
  1162. struct video1394_wait32 wait32;
  1163. struct video1394_wait wait;
  1164. mm_segment_t old_fs;
  1165. int ret;
  1166. if (copy_from_user(&wait32, argp, sizeof(wait32)))
  1167. return -EFAULT;
  1168. wait.channel = wait32.channel;
  1169. wait.buffer = wait32.buffer;
  1170. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1171. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1172. old_fs = get_fs();
  1173. set_fs(KERNEL_DS);
  1174. if (cmd == VIDEO1394_IOC32_LISTEN_WAIT_BUFFER)
  1175. ret = video1394_ioctl(file,
  1176. VIDEO1394_IOC_LISTEN_WAIT_BUFFER,
  1177. (unsigned long) &wait);
  1178. else
  1179. ret = video1394_ioctl(file,
  1180. VIDEO1394_IOC_LISTEN_POLL_BUFFER,
  1181. (unsigned long) &wait);
  1182. set_fs(old_fs);
  1183. if (!ret) {
  1184. wait32.channel = wait.channel;
  1185. wait32.buffer = wait.buffer;
  1186. wait32.filltime.tv_sec = (int)wait.filltime.tv_sec;
  1187. wait32.filltime.tv_usec = (int)wait.filltime.tv_usec;
  1188. if (copy_to_user(argp, &wait32, sizeof(wait32)))
  1189. ret = -EFAULT;
  1190. }
  1191. return ret;
  1192. }
  1193. static int video1394_w_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1194. {
  1195. struct video1394_wait32 wait32;
  1196. struct video1394_wait wait;
  1197. mm_segment_t old_fs;
  1198. int ret;
  1199. if (copy_from_user(&wait32, (void __user *)arg, sizeof(wait32)))
  1200. return -EFAULT;
  1201. wait.channel = wait32.channel;
  1202. wait.buffer = wait32.buffer;
  1203. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1204. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1205. old_fs = get_fs();
  1206. set_fs(KERNEL_DS);
  1207. if (cmd == VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER)
  1208. ret = video1394_ioctl(file,
  1209. VIDEO1394_IOC_LISTEN_QUEUE_BUFFER,
  1210. (unsigned long) &wait);
  1211. else
  1212. ret = video1394_ioctl(file,
  1213. VIDEO1394_IOC_TALK_WAIT_BUFFER,
  1214. (unsigned long) &wait);
  1215. set_fs(old_fs);
  1216. return ret;
  1217. }
  1218. static int video1394_queue_buf32(struct file *file, unsigned int cmd, unsigned long arg)
  1219. {
  1220. return -EFAULT; /* ??? was there before. */
  1221. return video1394_ioctl(file,
  1222. VIDEO1394_IOC_TALK_QUEUE_BUFFER, arg);
  1223. }
  1224. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg)
  1225. {
  1226. switch (cmd) {
  1227. case VIDEO1394_IOC_LISTEN_CHANNEL:
  1228. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  1229. case VIDEO1394_IOC_TALK_CHANNEL:
  1230. case VIDEO1394_IOC_UNTALK_CHANNEL:
  1231. return video1394_ioctl(f, cmd, arg);
  1232. case VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER:
  1233. return video1394_w_wait32(f, cmd, arg);
  1234. case VIDEO1394_IOC32_LISTEN_WAIT_BUFFER:
  1235. return video1394_wr_wait32(f, cmd, arg);
  1236. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  1237. return video1394_queue_buf32(f, cmd, arg);
  1238. case VIDEO1394_IOC32_TALK_WAIT_BUFFER:
  1239. return video1394_w_wait32(f, cmd, arg);
  1240. case VIDEO1394_IOC32_LISTEN_POLL_BUFFER:
  1241. return video1394_wr_wait32(f, cmd, arg);
  1242. default:
  1243. return -ENOIOCTLCMD;
  1244. }
  1245. }
  1246. #endif /* CONFIG_COMPAT */
  1247. static void __exit video1394_exit_module (void)
  1248. {
  1249. hpsb_unregister_protocol(&video1394_driver);
  1250. hpsb_unregister_highlevel(&video1394_highlevel);
  1251. cdev_del(&video1394_cdev);
  1252. PRINT_G(KERN_INFO, "Removed " VIDEO1394_DRIVER_NAME " module");
  1253. }
  1254. static int __init video1394_init_module (void)
  1255. {
  1256. int ret;
  1257. hpsb_init_highlevel(&video1394_highlevel);
  1258. cdev_init(&video1394_cdev, &video1394_fops);
  1259. video1394_cdev.owner = THIS_MODULE;
  1260. ret = cdev_add(&video1394_cdev, IEEE1394_VIDEO1394_DEV, 16);
  1261. if (ret) {
  1262. PRINT_G(KERN_ERR, "video1394: unable to get minor device block");
  1263. return ret;
  1264. }
  1265. hpsb_register_highlevel(&video1394_highlevel);
  1266. ret = hpsb_register_protocol(&video1394_driver);
  1267. if (ret) {
  1268. PRINT_G(KERN_ERR, "video1394: failed to register protocol");
  1269. hpsb_unregister_highlevel(&video1394_highlevel);
  1270. cdev_del(&video1394_cdev);
  1271. return ret;
  1272. }
  1273. PRINT_G(KERN_INFO, "Installed " VIDEO1394_DRIVER_NAME " module");
  1274. return 0;
  1275. }
  1276. module_init(video1394_init_module);
  1277. module_exit(video1394_exit_module);