i2c-pasemi.c 11 KB

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  1. /*
  2. * Copyright (C) 2006-2007 PA Semi, Inc
  3. *
  4. * SMBus host driver for PA Semi PWRficient
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/module.h>
  20. #include <linux/pci.h>
  21. #include <linux/kernel.h>
  22. #include <linux/stddef.h>
  23. #include <linux/sched.h>
  24. #include <linux/i2c.h>
  25. #include <linux/delay.h>
  26. #include <asm/io.h>
  27. static struct pci_driver pasemi_smb_driver;
  28. struct pasemi_smbus {
  29. struct pci_dev *dev;
  30. struct i2c_adapter adapter;
  31. unsigned long base;
  32. int size;
  33. };
  34. /* Register offsets */
  35. #define REG_MTXFIFO 0x00
  36. #define REG_MRXFIFO 0x04
  37. #define REG_SMSTA 0x14
  38. #define REG_CTL 0x1c
  39. /* Register defs */
  40. #define MTXFIFO_READ 0x00000400
  41. #define MTXFIFO_STOP 0x00000200
  42. #define MTXFIFO_START 0x00000100
  43. #define MTXFIFO_DATA_M 0x000000ff
  44. #define MRXFIFO_EMPTY 0x00000100
  45. #define MRXFIFO_DATA_M 0x000000ff
  46. #define SMSTA_XEN 0x08000000
  47. #define SMSTA_MTN 0x00200000
  48. #define CTL_MRR 0x00000400
  49. #define CTL_MTR 0x00000200
  50. #define CTL_CLK_M 0x000000ff
  51. #define CLK_100K_DIV 84
  52. #define CLK_400K_DIV 21
  53. static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val)
  54. {
  55. dev_dbg(&smbus->dev->dev, "smbus write reg %lx val %08x\n",
  56. smbus->base + reg, val);
  57. outl(val, smbus->base + reg);
  58. }
  59. static inline int reg_read(struct pasemi_smbus *smbus, int reg)
  60. {
  61. int ret;
  62. ret = inl(smbus->base + reg);
  63. dev_dbg(&smbus->dev->dev, "smbus read reg %lx val %08x\n",
  64. smbus->base + reg, ret);
  65. return ret;
  66. }
  67. #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg))
  68. #define RXFIFO_RD(smbus) reg_read((smbus), REG_MRXFIFO)
  69. static void pasemi_smb_clear(struct pasemi_smbus *smbus)
  70. {
  71. unsigned int status;
  72. status = reg_read(smbus, REG_SMSTA);
  73. reg_write(smbus, REG_SMSTA, status);
  74. }
  75. static unsigned int pasemi_smb_waitready(struct pasemi_smbus *smbus)
  76. {
  77. int timeout = 10;
  78. unsigned int status;
  79. status = reg_read(smbus, REG_SMSTA);
  80. while (!(status & SMSTA_XEN) && timeout--) {
  81. msleep(1);
  82. status = reg_read(smbus, REG_SMSTA);
  83. }
  84. /* Got NACK? */
  85. if (status & SMSTA_MTN)
  86. return -ENXIO;
  87. if (timeout < 0) {
  88. dev_warn(&smbus->dev->dev, "Timeout, status 0x%08x\n", status);
  89. reg_write(smbus, REG_SMSTA, status);
  90. return -ETIME;
  91. }
  92. /* Clear XEN */
  93. reg_write(smbus, REG_SMSTA, SMSTA_XEN);
  94. return 0;
  95. }
  96. static int pasemi_i2c_xfer_msg(struct i2c_adapter *adapter,
  97. struct i2c_msg *msg, int stop)
  98. {
  99. struct pasemi_smbus *smbus = adapter->algo_data;
  100. int read, i, err;
  101. u32 rd;
  102. read = msg->flags & I2C_M_RD ? 1 : 0;
  103. TXFIFO_WR(smbus, MTXFIFO_START | (msg->addr << 1) | read);
  104. if (read) {
  105. TXFIFO_WR(smbus, msg->len | MTXFIFO_READ |
  106. (stop ? MTXFIFO_STOP : 0));
  107. err = pasemi_smb_waitready(smbus);
  108. if (err)
  109. goto reset_out;
  110. for (i = 0; i < msg->len; i++) {
  111. rd = RXFIFO_RD(smbus);
  112. if (rd & MRXFIFO_EMPTY) {
  113. err = -ENODATA;
  114. goto reset_out;
  115. }
  116. msg->buf[i] = rd & MRXFIFO_DATA_M;
  117. }
  118. } else {
  119. for (i = 0; i < msg->len - 1; i++)
  120. TXFIFO_WR(smbus, msg->buf[i]);
  121. TXFIFO_WR(smbus, msg->buf[msg->len-1] |
  122. (stop ? MTXFIFO_STOP : 0));
  123. }
  124. return 0;
  125. reset_out:
  126. reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
  127. (CLK_100K_DIV & CTL_CLK_M)));
  128. return err;
  129. }
  130. static int pasemi_i2c_xfer(struct i2c_adapter *adapter,
  131. struct i2c_msg *msgs, int num)
  132. {
  133. struct pasemi_smbus *smbus = adapter->algo_data;
  134. int ret, i;
  135. pasemi_smb_clear(smbus);
  136. ret = 0;
  137. for (i = 0; i < num && !ret; i++)
  138. ret = pasemi_i2c_xfer_msg(adapter, &msgs[i], (i == (num - 1)));
  139. return ret ? ret : num;
  140. }
  141. static int pasemi_smb_xfer(struct i2c_adapter *adapter,
  142. u16 addr, unsigned short flags, char read_write, u8 command,
  143. int size, union i2c_smbus_data *data)
  144. {
  145. struct pasemi_smbus *smbus = adapter->algo_data;
  146. unsigned int rd;
  147. int read_flag, err;
  148. int len = 0, i;
  149. /* All our ops take 8-bit shifted addresses */
  150. addr <<= 1;
  151. read_flag = read_write == I2C_SMBUS_READ;
  152. pasemi_smb_clear(smbus);
  153. switch (size) {
  154. case I2C_SMBUS_QUICK:
  155. TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START |
  156. MTXFIFO_STOP);
  157. break;
  158. case I2C_SMBUS_BYTE:
  159. TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START);
  160. if (read_write)
  161. TXFIFO_WR(smbus, 1 | MTXFIFO_STOP | MTXFIFO_READ);
  162. else
  163. TXFIFO_WR(smbus, MTXFIFO_STOP | command);
  164. break;
  165. case I2C_SMBUS_BYTE_DATA:
  166. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  167. TXFIFO_WR(smbus, command);
  168. if (read_write) {
  169. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
  170. TXFIFO_WR(smbus, 1 | MTXFIFO_READ | MTXFIFO_STOP);
  171. } else {
  172. TXFIFO_WR(smbus, MTXFIFO_STOP | data->byte);
  173. }
  174. break;
  175. case I2C_SMBUS_WORD_DATA:
  176. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  177. TXFIFO_WR(smbus, command);
  178. if (read_write) {
  179. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
  180. TXFIFO_WR(smbus, 2 | MTXFIFO_READ | MTXFIFO_STOP);
  181. } else {
  182. TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
  183. TXFIFO_WR(smbus, MTXFIFO_STOP | (data->word >> 8));
  184. }
  185. break;
  186. case I2C_SMBUS_BLOCK_DATA:
  187. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  188. TXFIFO_WR(smbus, command);
  189. if (read_write) {
  190. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
  191. TXFIFO_WR(smbus, 1 | MTXFIFO_READ);
  192. rd = RXFIFO_RD(smbus);
  193. len = min_t(u8, (rd & MRXFIFO_DATA_M),
  194. I2C_SMBUS_BLOCK_MAX);
  195. TXFIFO_WR(smbus, len | MTXFIFO_READ |
  196. MTXFIFO_STOP);
  197. } else {
  198. len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX);
  199. TXFIFO_WR(smbus, len);
  200. for (i = 1; i < len; i++)
  201. TXFIFO_WR(smbus, data->block[i]);
  202. TXFIFO_WR(smbus, data->block[len] | MTXFIFO_STOP);
  203. }
  204. break;
  205. case I2C_SMBUS_PROC_CALL:
  206. read_write = I2C_SMBUS_READ;
  207. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  208. TXFIFO_WR(smbus, command);
  209. TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
  210. TXFIFO_WR(smbus, (data->word >> 8) & MTXFIFO_DATA_M);
  211. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
  212. TXFIFO_WR(smbus, 2 | MTXFIFO_STOP | MTXFIFO_READ);
  213. break;
  214. case I2C_SMBUS_BLOCK_PROC_CALL:
  215. len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX - 1);
  216. read_write = I2C_SMBUS_READ;
  217. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  218. TXFIFO_WR(smbus, command);
  219. TXFIFO_WR(smbus, len);
  220. for (i = 1; i <= len; i++)
  221. TXFIFO_WR(smbus, data->block[i]);
  222. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ);
  223. TXFIFO_WR(smbus, MTXFIFO_READ | 1);
  224. rd = RXFIFO_RD(smbus);
  225. len = min_t(u8, (rd & MRXFIFO_DATA_M),
  226. I2C_SMBUS_BLOCK_MAX - len);
  227. TXFIFO_WR(smbus, len | MTXFIFO_READ | MTXFIFO_STOP);
  228. break;
  229. default:
  230. dev_warn(&adapter->dev, "Unsupported transaction %d\n", size);
  231. return -EINVAL;
  232. }
  233. err = pasemi_smb_waitready(smbus);
  234. if (err)
  235. goto reset_out;
  236. if (read_write == I2C_SMBUS_WRITE)
  237. return 0;
  238. switch (size) {
  239. case I2C_SMBUS_BYTE:
  240. case I2C_SMBUS_BYTE_DATA:
  241. rd = RXFIFO_RD(smbus);
  242. if (rd & MRXFIFO_EMPTY) {
  243. err = -ENODATA;
  244. goto reset_out;
  245. }
  246. data->byte = rd & MRXFIFO_DATA_M;
  247. break;
  248. case I2C_SMBUS_WORD_DATA:
  249. case I2C_SMBUS_PROC_CALL:
  250. rd = RXFIFO_RD(smbus);
  251. if (rd & MRXFIFO_EMPTY) {
  252. err = -ENODATA;
  253. goto reset_out;
  254. }
  255. data->word = rd & MRXFIFO_DATA_M;
  256. rd = RXFIFO_RD(smbus);
  257. if (rd & MRXFIFO_EMPTY) {
  258. err = -ENODATA;
  259. goto reset_out;
  260. }
  261. data->word |= (rd & MRXFIFO_DATA_M) << 8;
  262. break;
  263. case I2C_SMBUS_BLOCK_DATA:
  264. case I2C_SMBUS_BLOCK_PROC_CALL:
  265. data->block[0] = len;
  266. for (i = 1; i <= len; i ++) {
  267. rd = RXFIFO_RD(smbus);
  268. if (rd & MRXFIFO_EMPTY) {
  269. err = -ENODATA;
  270. goto reset_out;
  271. }
  272. data->block[i] = rd & MRXFIFO_DATA_M;
  273. }
  274. break;
  275. }
  276. return 0;
  277. reset_out:
  278. reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
  279. (CLK_100K_DIV & CTL_CLK_M)));
  280. return err;
  281. }
  282. static u32 pasemi_smb_func(struct i2c_adapter *adapter)
  283. {
  284. return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
  285. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
  286. I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
  287. I2C_FUNC_SMBUS_BLOCK_PROC_CALL | I2C_FUNC_I2C;
  288. }
  289. static const struct i2c_algorithm smbus_algorithm = {
  290. .master_xfer = pasemi_i2c_xfer,
  291. .smbus_xfer = pasemi_smb_xfer,
  292. .functionality = pasemi_smb_func,
  293. };
  294. static int __devinit pasemi_smb_probe(struct pci_dev *dev,
  295. const struct pci_device_id *id)
  296. {
  297. struct pasemi_smbus *smbus;
  298. int error;
  299. if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
  300. return -ENODEV;
  301. smbus = kzalloc(sizeof(struct pasemi_smbus), GFP_KERNEL);
  302. if (!smbus)
  303. return -ENOMEM;
  304. smbus->dev = dev;
  305. smbus->base = pci_resource_start(dev, 0);
  306. smbus->size = pci_resource_len(dev, 0);
  307. if (!request_region(smbus->base, smbus->size,
  308. pasemi_smb_driver.name)) {
  309. error = -EBUSY;
  310. goto out_kfree;
  311. }
  312. smbus->adapter.owner = THIS_MODULE;
  313. snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
  314. "PA Semi SMBus adapter at 0x%lx", smbus->base);
  315. smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
  316. smbus->adapter.algo = &smbus_algorithm;
  317. smbus->adapter.algo_data = smbus;
  318. smbus->adapter.nr = PCI_FUNC(dev->devfn);
  319. /* set up the sysfs linkage to our parent device */
  320. smbus->adapter.dev.parent = &dev->dev;
  321. reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
  322. (CLK_100K_DIV & CTL_CLK_M)));
  323. error = i2c_add_numbered_adapter(&smbus->adapter);
  324. if (error)
  325. goto out_release_region;
  326. pci_set_drvdata(dev, smbus);
  327. return 0;
  328. out_release_region:
  329. release_region(smbus->base, smbus->size);
  330. out_kfree:
  331. kfree(smbus);
  332. return error;
  333. }
  334. static void __devexit pasemi_smb_remove(struct pci_dev *dev)
  335. {
  336. struct pasemi_smbus *smbus = pci_get_drvdata(dev);
  337. i2c_del_adapter(&smbus->adapter);
  338. release_region(smbus->base, smbus->size);
  339. kfree(smbus);
  340. }
  341. static struct pci_device_id pasemi_smb_ids[] = {
  342. { PCI_DEVICE(0x1959, 0xa003) },
  343. { 0, }
  344. };
  345. MODULE_DEVICE_TABLE(pci, pasemi_smb_ids);
  346. static struct pci_driver pasemi_smb_driver = {
  347. .name = "i2c-pasemi",
  348. .id_table = pasemi_smb_ids,
  349. .probe = pasemi_smb_probe,
  350. .remove = __devexit_p(pasemi_smb_remove),
  351. };
  352. static int __init pasemi_smb_init(void)
  353. {
  354. return pci_register_driver(&pasemi_smb_driver);
  355. }
  356. static void __exit pasemi_smb_exit(void)
  357. {
  358. pci_unregister_driver(&pasemi_smb_driver);
  359. }
  360. MODULE_LICENSE("GPL");
  361. MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
  362. MODULE_DESCRIPTION("PA Semi PWRficient SMBus driver");
  363. module_init(pasemi_smb_init);
  364. module_exit(pasemi_smb_exit);