hwmon-vid.c 8.4 KB

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  1. /*
  2. * hwmon-vid.c - VID/VRM/VRD voltage conversions
  3. *
  4. * Copyright (c) 2004 Rudolf Marek <r.marek@assembler.cz>
  5. *
  6. * Partly imported from i2c-vid.h of the lm_sensors project
  7. * Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com>
  8. * With assistance from Trent Piepho <xyzzy@speakeasy.org>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23. */
  24. #include <linux/module.h>
  25. #include <linux/kernel.h>
  26. #include <linux/hwmon-vid.h>
  27. /*
  28. * Common code for decoding VID pins.
  29. *
  30. * References:
  31. *
  32. * For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines",
  33. * available at http://developer.intel.com/.
  34. *
  35. * For VRD 10.0 and up, "VRD x.y Design Guide",
  36. * available at http://developer.intel.com/.
  37. *
  38. * AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
  39. * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.PDF
  40. * Table 74. VID Code Voltages
  41. * This corresponds to an arbitrary VRM code of 24 in the functions below.
  42. * These CPU models (K8 revision <= E) have 5 VID pins. See also:
  43. * Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Publication 25759,
  44. * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf
  45. *
  46. * AMD NPT Family 0Fh Processors, AMD Publication 32559,
  47. * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
  48. * Table 71. VID Code Voltages
  49. * This corresponds to an arbitrary VRM code of 25 in the functions below.
  50. * These CPU models (K8 revision >= F) have 6 VID pins. See also:
  51. * Revision Guide for AMD NPT Family 0Fh Processors, AMD Publication 33610,
  52. * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
  53. *
  54. * The 17 specification is in fact Intel Mobile Voltage Positioning -
  55. * (IMVP-II). You can find more information in the datasheet of Max1718
  56. * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452
  57. *
  58. * The 13 specification corresponds to the Intel Pentium M series. There
  59. * doesn't seem to be any named specification for these. The conversion
  60. * tables are detailed directly in the various Pentium M datasheets:
  61. * http://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm
  62. *
  63. * The 14 specification corresponds to Intel Core series. There
  64. * doesn't seem to be any named specification for these. The conversion
  65. * tables are detailed directly in the various Pentium Core datasheets:
  66. * http://www.intel.com/design/mobile/datashts/309221.htm
  67. *
  68. * The 110 (VRM 11) specification corresponds to Intel Conroe based series.
  69. * http://www.intel.com/design/processor/applnots/313214.htm
  70. */
  71. /*
  72. * vrm is the VRM/VRD document version multiplied by 10.
  73. * val is the 4-bit or more VID code.
  74. * Returned value is in mV to avoid floating point in the kernel.
  75. * Some VID have some bits in uV scale, this is rounded to mV.
  76. */
  77. int vid_from_reg(int val, u8 vrm)
  78. {
  79. int vid;
  80. switch(vrm) {
  81. case 100: /* VRD 10.0 */
  82. /* compute in uV, round to mV */
  83. val &= 0x3f;
  84. if((val & 0x1f) == 0x1f)
  85. return 0;
  86. if((val & 0x1f) <= 0x09 || val == 0x0a)
  87. vid = 1087500 - (val & 0x1f) * 25000;
  88. else
  89. vid = 1862500 - (val & 0x1f) * 25000;
  90. if(val & 0x20)
  91. vid -= 12500;
  92. return((vid + 500) / 1000);
  93. case 110: /* Intel Conroe */
  94. /* compute in uV, round to mV */
  95. val &= 0xff;
  96. if (val < 0x02 || val > 0xb2)
  97. return 0;
  98. return((1600000 - (val - 2) * 6250 + 500) / 1000);
  99. case 24: /* Athlon64 & Opteron */
  100. val &= 0x1f;
  101. if (val == 0x1f)
  102. return 0;
  103. /* fall through */
  104. case 25: /* AMD NPT 0Fh */
  105. val &= 0x3f;
  106. return (val < 32) ? 1550 - 25 * val
  107. : 775 - (25 * (val - 31)) / 2;
  108. case 91: /* VRM 9.1 */
  109. case 90: /* VRM 9.0 */
  110. val &= 0x1f;
  111. return(val == 0x1f ? 0 :
  112. 1850 - val * 25);
  113. case 85: /* VRM 8.5 */
  114. val &= 0x1f;
  115. return((val & 0x10 ? 25 : 0) +
  116. ((val & 0x0f) > 0x04 ? 2050 : 1250) -
  117. ((val & 0x0f) * 50));
  118. case 84: /* VRM 8.4 */
  119. val &= 0x0f;
  120. /* fall through */
  121. case 82: /* VRM 8.2 */
  122. val &= 0x1f;
  123. return(val == 0x1f ? 0 :
  124. val & 0x10 ? 5100 - (val) * 100 :
  125. 2050 - (val) * 50);
  126. case 17: /* Intel IMVP-II */
  127. val &= 0x1f;
  128. return(val & 0x10 ? 975 - (val & 0xF) * 25 :
  129. 1750 - val * 50);
  130. case 13:
  131. val &= 0x3f;
  132. return(1708 - val * 16);
  133. case 14: /* Intel Core */
  134. /* compute in uV, round to mV */
  135. val &= 0x7f;
  136. return(val > 0x77 ? 0 : (1500000 - (val * 12500) + 500) / 1000);
  137. default: /* report 0 for unknown */
  138. if (vrm)
  139. printk(KERN_WARNING "hwmon-vid: Requested unsupported "
  140. "VRM version (%u)\n", (unsigned int)vrm);
  141. return 0;
  142. }
  143. }
  144. /*
  145. * After this point is the code to automatically determine which
  146. * VRM/VRD specification should be used depending on the CPU.
  147. */
  148. struct vrm_model {
  149. u8 vendor;
  150. u8 eff_family;
  151. u8 eff_model;
  152. u8 eff_stepping;
  153. u8 vrm_type;
  154. };
  155. #define ANY 0xFF
  156. #ifdef CONFIG_X86
  157. /*
  158. * The stepping parameter is highest acceptable stepping for current line.
  159. * The model match must be exact for 4-bit values. For model values 0x10
  160. * and above (extended model), all models below the parameter will match.
  161. */
  162. static struct vrm_model vrm_models[] = {
  163. {X86_VENDOR_AMD, 0x6, ANY, ANY, 90}, /* Athlon Duron etc */
  164. {X86_VENDOR_AMD, 0xF, 0x3F, ANY, 24}, /* Athlon 64, Opteron */
  165. {X86_VENDOR_AMD, 0xF, ANY, ANY, 25}, /* NPT family 0Fh */
  166. {X86_VENDOR_INTEL, 0x6, 0x9, ANY, 13}, /* Pentium M (130 nm) */
  167. {X86_VENDOR_INTEL, 0x6, 0xB, ANY, 85}, /* Tualatin */
  168. {X86_VENDOR_INTEL, 0x6, 0xD, ANY, 13}, /* Pentium M (90 nm) */
  169. {X86_VENDOR_INTEL, 0x6, 0xE, ANY, 14}, /* Intel Core (65 nm) */
  170. {X86_VENDOR_INTEL, 0x6, 0xF, ANY, 110}, /* Intel Conroe */
  171. {X86_VENDOR_INTEL, 0x6, ANY, ANY, 82}, /* any P6 */
  172. {X86_VENDOR_INTEL, 0xF, 0x0, ANY, 90}, /* P4 */
  173. {X86_VENDOR_INTEL, 0xF, 0x1, ANY, 90}, /* P4 Willamette */
  174. {X86_VENDOR_INTEL, 0xF, 0x2, ANY, 90}, /* P4 Northwood */
  175. {X86_VENDOR_INTEL, 0xF, ANY, ANY, 100}, /* Prescott and above assume VRD 10 */
  176. {X86_VENDOR_CENTAUR, 0x6, 0x7, ANY, 85}, /* Eden ESP/Ezra */
  177. {X86_VENDOR_CENTAUR, 0x6, 0x8, 0x7, 85}, /* Ezra T */
  178. {X86_VENDOR_CENTAUR, 0x6, 0x9, 0x7, 85}, /* Nemiah */
  179. {X86_VENDOR_CENTAUR, 0x6, 0x9, ANY, 17}, /* C3-M, Eden-N */
  180. {X86_VENDOR_CENTAUR, 0x6, 0xA, 0x7, 0}, /* No information */
  181. {X86_VENDOR_CENTAUR, 0x6, 0xA, ANY, 13}, /* C7, Esther */
  182. {X86_VENDOR_UNKNOWN, ANY, ANY, ANY, 0} /* stop here */
  183. };
  184. static u8 find_vrm(u8 eff_family, u8 eff_model, u8 eff_stepping, u8 vendor)
  185. {
  186. int i = 0;
  187. while (vrm_models[i].vendor!=X86_VENDOR_UNKNOWN) {
  188. if (vrm_models[i].vendor==vendor)
  189. if ((vrm_models[i].eff_family==eff_family)
  190. && ((vrm_models[i].eff_model==eff_model) ||
  191. (vrm_models[i].eff_model >= 0x10 &&
  192. eff_model <= vrm_models[i].eff_model) ||
  193. (vrm_models[i].eff_model==ANY)) &&
  194. (eff_stepping <= vrm_models[i].eff_stepping))
  195. return vrm_models[i].vrm_type;
  196. i++;
  197. }
  198. return 0;
  199. }
  200. u8 vid_which_vrm(void)
  201. {
  202. struct cpuinfo_x86 *c = &cpu_data(0);
  203. u32 eax;
  204. u8 eff_family, eff_model, eff_stepping, vrm_ret;
  205. if (c->x86 < 6) /* Any CPU with family lower than 6 */
  206. return 0; /* doesn't have VID and/or CPUID */
  207. eax = cpuid_eax(1);
  208. eff_family = ((eax & 0x00000F00)>>8);
  209. eff_model = ((eax & 0x000000F0)>>4);
  210. eff_stepping = eax & 0xF;
  211. if (eff_family == 0xF) { /* use extended model & family */
  212. eff_family += ((eax & 0x00F00000)>>20);
  213. eff_model += ((eax & 0x000F0000)>>16)<<4;
  214. }
  215. vrm_ret = find_vrm(eff_family, eff_model, eff_stepping, c->x86_vendor);
  216. if (vrm_ret == 0)
  217. printk(KERN_INFO "hwmon-vid: Unknown VRM version of your "
  218. "x86 CPU\n");
  219. return vrm_ret;
  220. }
  221. /* and now for something completely different for the non-x86 world */
  222. #else
  223. u8 vid_which_vrm(void)
  224. {
  225. printk(KERN_INFO "hwmon-vid: Unknown VRM version of your CPU\n");
  226. return 0;
  227. }
  228. #endif
  229. EXPORT_SYMBOL(vid_from_reg);
  230. EXPORT_SYMBOL(vid_which_vrm);
  231. MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
  232. MODULE_DESCRIPTION("hwmon-vid driver");
  233. MODULE_LICENSE("GPL");