via_irq.c 11 KB

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  1. /* via_irq.c
  2. *
  3. * Copyright 2004 BEAM Ltd.
  4. * Copyright 2002 Tungsten Graphics, Inc.
  5. * Copyright 2005 Thomas Hellstrom.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * BEAM LTD, TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  23. * DAMAGES OR
  24. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26. * DEALINGS IN THE SOFTWARE.
  27. *
  28. * Authors:
  29. * Terry Barnaby <terry1@beam.ltd.uk>
  30. * Keith Whitwell <keith@tungstengraphics.com>
  31. * Thomas Hellstrom <unichrome@shipmail.org>
  32. *
  33. * This code provides standard DRM access to the Via Unichrome / Pro Vertical blank
  34. * interrupt, as well as an infrastructure to handle other interrupts of the chip.
  35. * The refresh rate is also calculated for video playback sync purposes.
  36. */
  37. #include "drmP.h"
  38. #include "drm.h"
  39. #include "via_drm.h"
  40. #include "via_drv.h"
  41. #define VIA_REG_INTERRUPT 0x200
  42. /* VIA_REG_INTERRUPT */
  43. #define VIA_IRQ_GLOBAL (1 << 31)
  44. #define VIA_IRQ_VBLANK_ENABLE (1 << 19)
  45. #define VIA_IRQ_VBLANK_PENDING (1 << 3)
  46. #define VIA_IRQ_HQV0_ENABLE (1 << 11)
  47. #define VIA_IRQ_HQV1_ENABLE (1 << 25)
  48. #define VIA_IRQ_HQV0_PENDING (1 << 9)
  49. #define VIA_IRQ_HQV1_PENDING (1 << 10)
  50. #define VIA_IRQ_DMA0_DD_ENABLE (1 << 20)
  51. #define VIA_IRQ_DMA0_TD_ENABLE (1 << 21)
  52. #define VIA_IRQ_DMA1_DD_ENABLE (1 << 22)
  53. #define VIA_IRQ_DMA1_TD_ENABLE (1 << 23)
  54. #define VIA_IRQ_DMA0_DD_PENDING (1 << 4)
  55. #define VIA_IRQ_DMA0_TD_PENDING (1 << 5)
  56. #define VIA_IRQ_DMA1_DD_PENDING (1 << 6)
  57. #define VIA_IRQ_DMA1_TD_PENDING (1 << 7)
  58. /*
  59. * Device-specific IRQs go here. This type might need to be extended with
  60. * the register if there are multiple IRQ control registers.
  61. * Currently we activate the HQV interrupts of Unichrome Pro group A.
  62. */
  63. static maskarray_t via_pro_group_a_irqs[] = {
  64. {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010,
  65. 0x00000000},
  66. {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
  67. 0x00000000},
  68. {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
  69. VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
  70. {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
  71. VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
  72. };
  73. static int via_num_pro_group_a =
  74. sizeof(via_pro_group_a_irqs) / sizeof(maskarray_t);
  75. static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};
  76. static maskarray_t via_unichrome_irqs[] = {
  77. {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
  78. VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
  79. {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
  80. VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}
  81. };
  82. static int via_num_unichrome = sizeof(via_unichrome_irqs) / sizeof(maskarray_t);
  83. static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
  84. static unsigned time_diff(struct timeval *now, struct timeval *then)
  85. {
  86. return (now->tv_usec >= then->tv_usec) ?
  87. now->tv_usec - then->tv_usec :
  88. 1000000 - (then->tv_usec - now->tv_usec);
  89. }
  90. irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
  91. {
  92. struct drm_device *dev = (struct drm_device *) arg;
  93. drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
  94. u32 status;
  95. int handled = 0;
  96. struct timeval cur_vblank;
  97. drm_via_irq_t *cur_irq = dev_priv->via_irqs;
  98. int i;
  99. status = VIA_READ(VIA_REG_INTERRUPT);
  100. if (status & VIA_IRQ_VBLANK_PENDING) {
  101. atomic_inc(&dev->vbl_received);
  102. if (!(atomic_read(&dev->vbl_received) & 0x0F)) {
  103. do_gettimeofday(&cur_vblank);
  104. if (dev_priv->last_vblank_valid) {
  105. dev_priv->usec_per_vblank =
  106. time_diff(&cur_vblank,
  107. &dev_priv->last_vblank) >> 4;
  108. }
  109. dev_priv->last_vblank = cur_vblank;
  110. dev_priv->last_vblank_valid = 1;
  111. }
  112. if (!(atomic_read(&dev->vbl_received) & 0xFF)) {
  113. DRM_DEBUG("US per vblank is: %u\n",
  114. dev_priv->usec_per_vblank);
  115. }
  116. DRM_WAKEUP(&dev->vbl_queue);
  117. drm_vbl_send_signals(dev);
  118. handled = 1;
  119. }
  120. for (i = 0; i < dev_priv->num_irqs; ++i) {
  121. if (status & cur_irq->pending_mask) {
  122. atomic_inc(&cur_irq->irq_received);
  123. DRM_WAKEUP(&cur_irq->irq_queue);
  124. handled = 1;
  125. if (dev_priv->irq_map[drm_via_irq_dma0_td] == i) {
  126. via_dmablit_handler(dev, 0, 1);
  127. } else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i) {
  128. via_dmablit_handler(dev, 1, 1);
  129. }
  130. }
  131. cur_irq++;
  132. }
  133. /* Acknowlege interrupts */
  134. VIA_WRITE(VIA_REG_INTERRUPT, status);
  135. if (handled)
  136. return IRQ_HANDLED;
  137. else
  138. return IRQ_NONE;
  139. }
  140. static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv)
  141. {
  142. u32 status;
  143. if (dev_priv) {
  144. /* Acknowlege interrupts */
  145. status = VIA_READ(VIA_REG_INTERRUPT);
  146. VIA_WRITE(VIA_REG_INTERRUPT, status |
  147. dev_priv->irq_pending_mask);
  148. }
  149. }
  150. int via_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence)
  151. {
  152. drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
  153. unsigned int cur_vblank;
  154. int ret = 0;
  155. DRM_DEBUG("\n");
  156. if (!dev_priv) {
  157. DRM_ERROR("called with no initialization\n");
  158. return -EINVAL;
  159. }
  160. viadrv_acknowledge_irqs(dev_priv);
  161. /* Assume that the user has missed the current sequence number
  162. * by about a day rather than she wants to wait for years
  163. * using vertical blanks...
  164. */
  165. DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
  166. (((cur_vblank = atomic_read(&dev->vbl_received)) -
  167. *sequence) <= (1 << 23)));
  168. *sequence = cur_vblank;
  169. return ret;
  170. }
  171. static int
  172. via_driver_irq_wait(struct drm_device * dev, unsigned int irq, int force_sequence,
  173. unsigned int *sequence)
  174. {
  175. drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
  176. unsigned int cur_irq_sequence;
  177. drm_via_irq_t *cur_irq;
  178. int ret = 0;
  179. maskarray_t *masks;
  180. int real_irq;
  181. DRM_DEBUG("\n");
  182. if (!dev_priv) {
  183. DRM_ERROR("called with no initialization\n");
  184. return -EINVAL;
  185. }
  186. if (irq >= drm_via_irq_num) {
  187. DRM_ERROR("Trying to wait on unknown irq %d\n", irq);
  188. return -EINVAL;
  189. }
  190. real_irq = dev_priv->irq_map[irq];
  191. if (real_irq < 0) {
  192. DRM_ERROR("Video IRQ %d not available on this hardware.\n",
  193. irq);
  194. return -EINVAL;
  195. }
  196. masks = dev_priv->irq_masks;
  197. cur_irq = dev_priv->via_irqs + real_irq;
  198. if (masks[real_irq][2] && !force_sequence) {
  199. DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
  200. ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
  201. masks[irq][4]));
  202. cur_irq_sequence = atomic_read(&cur_irq->irq_received);
  203. } else {
  204. DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
  205. (((cur_irq_sequence =
  206. atomic_read(&cur_irq->irq_received)) -
  207. *sequence) <= (1 << 23)));
  208. }
  209. *sequence = cur_irq_sequence;
  210. return ret;
  211. }
  212. /*
  213. * drm_dma.h hooks
  214. */
  215. void via_driver_irq_preinstall(struct drm_device * dev)
  216. {
  217. drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
  218. u32 status;
  219. drm_via_irq_t *cur_irq;
  220. int i;
  221. DRM_DEBUG("dev_priv: %p\n", dev_priv);
  222. if (dev_priv) {
  223. cur_irq = dev_priv->via_irqs;
  224. dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
  225. dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
  226. if (dev_priv->chipset == VIA_PRO_GROUP_A ||
  227. dev_priv->chipset == VIA_DX9_0) {
  228. dev_priv->irq_masks = via_pro_group_a_irqs;
  229. dev_priv->num_irqs = via_num_pro_group_a;
  230. dev_priv->irq_map = via_irqmap_pro_group_a;
  231. } else {
  232. dev_priv->irq_masks = via_unichrome_irqs;
  233. dev_priv->num_irqs = via_num_unichrome;
  234. dev_priv->irq_map = via_irqmap_unichrome;
  235. }
  236. for (i = 0; i < dev_priv->num_irqs; ++i) {
  237. atomic_set(&cur_irq->irq_received, 0);
  238. cur_irq->enable_mask = dev_priv->irq_masks[i][0];
  239. cur_irq->pending_mask = dev_priv->irq_masks[i][1];
  240. DRM_INIT_WAITQUEUE(&cur_irq->irq_queue);
  241. dev_priv->irq_enable_mask |= cur_irq->enable_mask;
  242. dev_priv->irq_pending_mask |= cur_irq->pending_mask;
  243. cur_irq++;
  244. DRM_DEBUG("Initializing IRQ %d\n", i);
  245. }
  246. dev_priv->last_vblank_valid = 0;
  247. /* Clear VSync interrupt regs */
  248. status = VIA_READ(VIA_REG_INTERRUPT);
  249. VIA_WRITE(VIA_REG_INTERRUPT, status &
  250. ~(dev_priv->irq_enable_mask));
  251. /* Clear bits if they're already high */
  252. viadrv_acknowledge_irqs(dev_priv);
  253. }
  254. }
  255. void via_driver_irq_postinstall(struct drm_device * dev)
  256. {
  257. drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
  258. u32 status;
  259. DRM_DEBUG("\n");
  260. if (dev_priv) {
  261. status = VIA_READ(VIA_REG_INTERRUPT);
  262. VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
  263. | dev_priv->irq_enable_mask);
  264. /* Some magic, oh for some data sheets ! */
  265. VIA_WRITE8(0x83d4, 0x11);
  266. VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
  267. }
  268. }
  269. void via_driver_irq_uninstall(struct drm_device * dev)
  270. {
  271. drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
  272. u32 status;
  273. DRM_DEBUG("\n");
  274. if (dev_priv) {
  275. /* Some more magic, oh for some data sheets ! */
  276. VIA_WRITE8(0x83d4, 0x11);
  277. VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
  278. status = VIA_READ(VIA_REG_INTERRUPT);
  279. VIA_WRITE(VIA_REG_INTERRUPT, status &
  280. ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
  281. }
  282. }
  283. int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv)
  284. {
  285. drm_via_irqwait_t *irqwait = data;
  286. struct timeval now;
  287. int ret = 0;
  288. drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
  289. drm_via_irq_t *cur_irq = dev_priv->via_irqs;
  290. int force_sequence;
  291. if (!dev->irq)
  292. return -EINVAL;
  293. if (irqwait->request.irq >= dev_priv->num_irqs) {
  294. DRM_ERROR("Trying to wait on unknown irq %d\n",
  295. irqwait->request.irq);
  296. return -EINVAL;
  297. }
  298. cur_irq += irqwait->request.irq;
  299. switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) {
  300. case VIA_IRQ_RELATIVE:
  301. irqwait->request.sequence += atomic_read(&cur_irq->irq_received);
  302. irqwait->request.type &= ~_DRM_VBLANK_RELATIVE;
  303. case VIA_IRQ_ABSOLUTE:
  304. break;
  305. default:
  306. return -EINVAL;
  307. }
  308. if (irqwait->request.type & VIA_IRQ_SIGNAL) {
  309. DRM_ERROR("Signals on Via IRQs not implemented yet.\n");
  310. return -EINVAL;
  311. }
  312. force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE);
  313. ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence,
  314. &irqwait->request.sequence);
  315. do_gettimeofday(&now);
  316. irqwait->reply.tval_sec = now.tv_sec;
  317. irqwait->reply.tval_usec = now.tv_usec;
  318. return ret;
  319. }