i810_dma.c 33 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i810_drm.h"
  35. #include "i810_drv.h"
  36. #include <linux/interrupt.h> /* For task queue support */
  37. #include <linux/delay.h>
  38. #include <linux/pagemap.h>
  39. #define I810_BUF_FREE 2
  40. #define I810_BUF_CLIENT 1
  41. #define I810_BUF_HARDWARE 0
  42. #define I810_BUF_UNMAPPED 0
  43. #define I810_BUF_MAPPED 1
  44. static struct drm_buf *i810_freelist_get(struct drm_device * dev)
  45. {
  46. struct drm_device_dma *dma = dev->dma;
  47. int i;
  48. int used;
  49. /* Linear search might not be the best solution */
  50. for (i = 0; i < dma->buf_count; i++) {
  51. struct drm_buf *buf = dma->buflist[i];
  52. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  53. /* In use is already a pointer */
  54. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  55. I810_BUF_CLIENT);
  56. if (used == I810_BUF_FREE) {
  57. return buf;
  58. }
  59. }
  60. return NULL;
  61. }
  62. /* This should only be called if the buffer is not sent to the hardware
  63. * yet, the hardware updates in use for us once its on the ring buffer.
  64. */
  65. static int i810_freelist_put(struct drm_device * dev, struct drm_buf * buf)
  66. {
  67. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  68. int used;
  69. /* In use is already a pointer */
  70. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  71. if (used != I810_BUF_CLIENT) {
  72. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  73. return -EINVAL;
  74. }
  75. return 0;
  76. }
  77. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  78. {
  79. struct drm_file *priv = filp->private_data;
  80. struct drm_device *dev;
  81. drm_i810_private_t *dev_priv;
  82. struct drm_buf *buf;
  83. drm_i810_buf_priv_t *buf_priv;
  84. lock_kernel();
  85. dev = priv->minor->dev;
  86. dev_priv = dev->dev_private;
  87. buf = dev_priv->mmap_buffer;
  88. buf_priv = buf->dev_private;
  89. vma->vm_flags |= (VM_IO | VM_DONTCOPY);
  90. vma->vm_file = filp;
  91. buf_priv->currently_mapped = I810_BUF_MAPPED;
  92. unlock_kernel();
  93. if (io_remap_pfn_range(vma, vma->vm_start,
  94. vma->vm_pgoff,
  95. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  96. return -EAGAIN;
  97. return 0;
  98. }
  99. static const struct file_operations i810_buffer_fops = {
  100. .open = drm_open,
  101. .release = drm_release,
  102. .ioctl = drm_ioctl,
  103. .mmap = i810_mmap_buffers,
  104. .fasync = drm_fasync,
  105. };
  106. static int i810_map_buffer(struct drm_buf * buf, struct drm_file *file_priv)
  107. {
  108. struct drm_device *dev = file_priv->minor->dev;
  109. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  110. drm_i810_private_t *dev_priv = dev->dev_private;
  111. const struct file_operations *old_fops;
  112. int retcode = 0;
  113. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  114. return -EINVAL;
  115. down_write(&current->mm->mmap_sem);
  116. old_fops = file_priv->filp->f_op;
  117. file_priv->filp->f_op = &i810_buffer_fops;
  118. dev_priv->mmap_buffer = buf;
  119. buf_priv->virtual = (void *)do_mmap(file_priv->filp, 0, buf->total,
  120. PROT_READ | PROT_WRITE,
  121. MAP_SHARED, buf->bus_address);
  122. dev_priv->mmap_buffer = NULL;
  123. file_priv->filp->f_op = old_fops;
  124. if (IS_ERR(buf_priv->virtual)) {
  125. /* Real error */
  126. DRM_ERROR("mmap error\n");
  127. retcode = PTR_ERR(buf_priv->virtual);
  128. buf_priv->virtual = NULL;
  129. }
  130. up_write(&current->mm->mmap_sem);
  131. return retcode;
  132. }
  133. static int i810_unmap_buffer(struct drm_buf * buf)
  134. {
  135. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  136. int retcode = 0;
  137. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  138. return -EINVAL;
  139. down_write(&current->mm->mmap_sem);
  140. retcode = do_munmap(current->mm,
  141. (unsigned long)buf_priv->virtual,
  142. (size_t) buf->total);
  143. up_write(&current->mm->mmap_sem);
  144. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  145. buf_priv->virtual = NULL;
  146. return retcode;
  147. }
  148. static int i810_dma_get_buffer(struct drm_device * dev, drm_i810_dma_t * d,
  149. struct drm_file *file_priv)
  150. {
  151. struct drm_buf *buf;
  152. drm_i810_buf_priv_t *buf_priv;
  153. int retcode = 0;
  154. buf = i810_freelist_get(dev);
  155. if (!buf) {
  156. retcode = -ENOMEM;
  157. DRM_DEBUG("retcode=%d\n", retcode);
  158. return retcode;
  159. }
  160. retcode = i810_map_buffer(buf, file_priv);
  161. if (retcode) {
  162. i810_freelist_put(dev, buf);
  163. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  164. return retcode;
  165. }
  166. buf->file_priv = file_priv;
  167. buf_priv = buf->dev_private;
  168. d->granted = 1;
  169. d->request_idx = buf->idx;
  170. d->request_size = buf->total;
  171. d->virtual = buf_priv->virtual;
  172. return retcode;
  173. }
  174. static int i810_dma_cleanup(struct drm_device * dev)
  175. {
  176. struct drm_device_dma *dma = dev->dma;
  177. /* Make sure interrupts are disabled here because the uninstall ioctl
  178. * may not have been called from userspace and after dev_private
  179. * is freed, it's too late.
  180. */
  181. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  182. drm_irq_uninstall(dev);
  183. if (dev->dev_private) {
  184. int i;
  185. drm_i810_private_t *dev_priv =
  186. (drm_i810_private_t *) dev->dev_private;
  187. if (dev_priv->ring.virtual_start) {
  188. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  189. }
  190. if (dev_priv->hw_status_page) {
  191. pci_free_consistent(dev->pdev, PAGE_SIZE,
  192. dev_priv->hw_status_page,
  193. dev_priv->dma_status_page);
  194. /* Need to rewrite hardware status page */
  195. I810_WRITE(0x02080, 0x1ffff000);
  196. }
  197. drm_free(dev->dev_private, sizeof(drm_i810_private_t),
  198. DRM_MEM_DRIVER);
  199. dev->dev_private = NULL;
  200. for (i = 0; i < dma->buf_count; i++) {
  201. struct drm_buf *buf = dma->buflist[i];
  202. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  203. if (buf_priv->kernel_virtual && buf->total)
  204. drm_core_ioremapfree(&buf_priv->map, dev);
  205. }
  206. }
  207. return 0;
  208. }
  209. static int i810_wait_ring(struct drm_device * dev, int n)
  210. {
  211. drm_i810_private_t *dev_priv = dev->dev_private;
  212. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  213. int iters = 0;
  214. unsigned long end;
  215. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  216. end = jiffies + (HZ * 3);
  217. while (ring->space < n) {
  218. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  219. ring->space = ring->head - (ring->tail + 8);
  220. if (ring->space < 0)
  221. ring->space += ring->Size;
  222. if (ring->head != last_head) {
  223. end = jiffies + (HZ * 3);
  224. last_head = ring->head;
  225. }
  226. iters++;
  227. if (time_before(end, jiffies)) {
  228. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  229. DRM_ERROR("lockup\n");
  230. goto out_wait_ring;
  231. }
  232. udelay(1);
  233. }
  234. out_wait_ring:
  235. return iters;
  236. }
  237. static void i810_kernel_lost_context(struct drm_device * dev)
  238. {
  239. drm_i810_private_t *dev_priv = dev->dev_private;
  240. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  241. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  242. ring->tail = I810_READ(LP_RING + RING_TAIL);
  243. ring->space = ring->head - (ring->tail + 8);
  244. if (ring->space < 0)
  245. ring->space += ring->Size;
  246. }
  247. static int i810_freelist_init(struct drm_device * dev, drm_i810_private_t * dev_priv)
  248. {
  249. struct drm_device_dma *dma = dev->dma;
  250. int my_idx = 24;
  251. u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
  252. int i;
  253. if (dma->buf_count > 1019) {
  254. /* Not enough space in the status page for the freelist */
  255. return -EINVAL;
  256. }
  257. for (i = 0; i < dma->buf_count; i++) {
  258. struct drm_buf *buf = dma->buflist[i];
  259. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  260. buf_priv->in_use = hw_status++;
  261. buf_priv->my_use_idx = my_idx;
  262. my_idx += 4;
  263. *buf_priv->in_use = I810_BUF_FREE;
  264. buf_priv->map.offset = buf->bus_address;
  265. buf_priv->map.size = buf->total;
  266. buf_priv->map.type = _DRM_AGP;
  267. buf_priv->map.flags = 0;
  268. buf_priv->map.mtrr = 0;
  269. drm_core_ioremap(&buf_priv->map, dev);
  270. buf_priv->kernel_virtual = buf_priv->map.handle;
  271. }
  272. return 0;
  273. }
  274. static int i810_dma_initialize(struct drm_device * dev,
  275. drm_i810_private_t * dev_priv,
  276. drm_i810_init_t * init)
  277. {
  278. struct drm_map_list *r_list;
  279. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  280. list_for_each_entry(r_list, &dev->maplist, head) {
  281. if (r_list->map &&
  282. r_list->map->type == _DRM_SHM &&
  283. r_list->map->flags & _DRM_CONTAINS_LOCK) {
  284. dev_priv->sarea_map = r_list->map;
  285. break;
  286. }
  287. }
  288. if (!dev_priv->sarea_map) {
  289. dev->dev_private = (void *)dev_priv;
  290. i810_dma_cleanup(dev);
  291. DRM_ERROR("can not find sarea!\n");
  292. return -EINVAL;
  293. }
  294. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  295. if (!dev_priv->mmio_map) {
  296. dev->dev_private = (void *)dev_priv;
  297. i810_dma_cleanup(dev);
  298. DRM_ERROR("can not find mmio map!\n");
  299. return -EINVAL;
  300. }
  301. dev->agp_buffer_token = init->buffers_offset;
  302. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  303. if (!dev->agp_buffer_map) {
  304. dev->dev_private = (void *)dev_priv;
  305. i810_dma_cleanup(dev);
  306. DRM_ERROR("can not find dma buffer map!\n");
  307. return -EINVAL;
  308. }
  309. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  310. ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
  311. dev_priv->ring.Start = init->ring_start;
  312. dev_priv->ring.End = init->ring_end;
  313. dev_priv->ring.Size = init->ring_size;
  314. dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
  315. dev_priv->ring.map.size = init->ring_size;
  316. dev_priv->ring.map.type = _DRM_AGP;
  317. dev_priv->ring.map.flags = 0;
  318. dev_priv->ring.map.mtrr = 0;
  319. drm_core_ioremap(&dev_priv->ring.map, dev);
  320. if (dev_priv->ring.map.handle == NULL) {
  321. dev->dev_private = (void *)dev_priv;
  322. i810_dma_cleanup(dev);
  323. DRM_ERROR("can not ioremap virtual address for"
  324. " ring buffer\n");
  325. return -ENOMEM;
  326. }
  327. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  328. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  329. dev_priv->w = init->w;
  330. dev_priv->h = init->h;
  331. dev_priv->pitch = init->pitch;
  332. dev_priv->back_offset = init->back_offset;
  333. dev_priv->depth_offset = init->depth_offset;
  334. dev_priv->front_offset = init->front_offset;
  335. dev_priv->overlay_offset = init->overlay_offset;
  336. dev_priv->overlay_physical = init->overlay_physical;
  337. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  338. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  339. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  340. /* Program Hardware Status Page */
  341. dev_priv->hw_status_page =
  342. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  343. &dev_priv->dma_status_page);
  344. if (!dev_priv->hw_status_page) {
  345. dev->dev_private = (void *)dev_priv;
  346. i810_dma_cleanup(dev);
  347. DRM_ERROR("Can not allocate hardware status page\n");
  348. return -ENOMEM;
  349. }
  350. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  351. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  352. I810_WRITE(0x02080, dev_priv->dma_status_page);
  353. DRM_DEBUG("Enabled hardware status page\n");
  354. /* Now we need to init our freelist */
  355. if (i810_freelist_init(dev, dev_priv) != 0) {
  356. dev->dev_private = (void *)dev_priv;
  357. i810_dma_cleanup(dev);
  358. DRM_ERROR("Not enough space in the status page for"
  359. " the freelist\n");
  360. return -ENOMEM;
  361. }
  362. dev->dev_private = (void *)dev_priv;
  363. return 0;
  364. }
  365. static int i810_dma_init(struct drm_device *dev, void *data,
  366. struct drm_file *file_priv)
  367. {
  368. drm_i810_private_t *dev_priv;
  369. drm_i810_init_t *init = data;
  370. int retcode = 0;
  371. switch (init->func) {
  372. case I810_INIT_DMA_1_4:
  373. DRM_INFO("Using v1.4 init.\n");
  374. dev_priv = drm_alloc(sizeof(drm_i810_private_t),
  375. DRM_MEM_DRIVER);
  376. if (dev_priv == NULL)
  377. return -ENOMEM;
  378. retcode = i810_dma_initialize(dev, dev_priv, init);
  379. break;
  380. case I810_CLEANUP_DMA:
  381. DRM_INFO("DMA Cleanup\n");
  382. retcode = i810_dma_cleanup(dev);
  383. break;
  384. default:
  385. return -EINVAL;
  386. }
  387. return retcode;
  388. }
  389. /* Most efficient way to verify state for the i810 is as it is
  390. * emitted. Non-conformant state is silently dropped.
  391. *
  392. * Use 'volatile' & local var tmp to force the emitted values to be
  393. * identical to the verified ones.
  394. */
  395. static void i810EmitContextVerified(struct drm_device * dev,
  396. volatile unsigned int *code)
  397. {
  398. drm_i810_private_t *dev_priv = dev->dev_private;
  399. int i, j = 0;
  400. unsigned int tmp;
  401. RING_LOCALS;
  402. BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
  403. OUT_RING(GFX_OP_COLOR_FACTOR);
  404. OUT_RING(code[I810_CTXREG_CF1]);
  405. OUT_RING(GFX_OP_STIPPLE);
  406. OUT_RING(code[I810_CTXREG_ST1]);
  407. for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
  408. tmp = code[i];
  409. if ((tmp & (7 << 29)) == (3 << 29) &&
  410. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  411. OUT_RING(tmp);
  412. j++;
  413. } else
  414. printk("constext state dropped!!!\n");
  415. }
  416. if (j & 1)
  417. OUT_RING(0);
  418. ADVANCE_LP_RING();
  419. }
  420. static void i810EmitTexVerified(struct drm_device * dev, volatile unsigned int *code)
  421. {
  422. drm_i810_private_t *dev_priv = dev->dev_private;
  423. int i, j = 0;
  424. unsigned int tmp;
  425. RING_LOCALS;
  426. BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
  427. OUT_RING(GFX_OP_MAP_INFO);
  428. OUT_RING(code[I810_TEXREG_MI1]);
  429. OUT_RING(code[I810_TEXREG_MI2]);
  430. OUT_RING(code[I810_TEXREG_MI3]);
  431. for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
  432. tmp = code[i];
  433. if ((tmp & (7 << 29)) == (3 << 29) &&
  434. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  435. OUT_RING(tmp);
  436. j++;
  437. } else
  438. printk("texture state dropped!!!\n");
  439. }
  440. if (j & 1)
  441. OUT_RING(0);
  442. ADVANCE_LP_RING();
  443. }
  444. /* Need to do some additional checking when setting the dest buffer.
  445. */
  446. static void i810EmitDestVerified(struct drm_device * dev,
  447. volatile unsigned int *code)
  448. {
  449. drm_i810_private_t *dev_priv = dev->dev_private;
  450. unsigned int tmp;
  451. RING_LOCALS;
  452. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  453. tmp = code[I810_DESTREG_DI1];
  454. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  455. OUT_RING(CMD_OP_DESTBUFFER_INFO);
  456. OUT_RING(tmp);
  457. } else
  458. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  459. tmp, dev_priv->front_di1, dev_priv->back_di1);
  460. /* invarient:
  461. */
  462. OUT_RING(CMD_OP_Z_BUFFER_INFO);
  463. OUT_RING(dev_priv->zi1);
  464. OUT_RING(GFX_OP_DESTBUFFER_VARS);
  465. OUT_RING(code[I810_DESTREG_DV1]);
  466. OUT_RING(GFX_OP_DRAWRECT_INFO);
  467. OUT_RING(code[I810_DESTREG_DR1]);
  468. OUT_RING(code[I810_DESTREG_DR2]);
  469. OUT_RING(code[I810_DESTREG_DR3]);
  470. OUT_RING(code[I810_DESTREG_DR4]);
  471. OUT_RING(0);
  472. ADVANCE_LP_RING();
  473. }
  474. static void i810EmitState(struct drm_device * dev)
  475. {
  476. drm_i810_private_t *dev_priv = dev->dev_private;
  477. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  478. unsigned int dirty = sarea_priv->dirty;
  479. DRM_DEBUG("%x\n", dirty);
  480. if (dirty & I810_UPLOAD_BUFFERS) {
  481. i810EmitDestVerified(dev, sarea_priv->BufferState);
  482. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  483. }
  484. if (dirty & I810_UPLOAD_CTX) {
  485. i810EmitContextVerified(dev, sarea_priv->ContextState);
  486. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  487. }
  488. if (dirty & I810_UPLOAD_TEX0) {
  489. i810EmitTexVerified(dev, sarea_priv->TexState[0]);
  490. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  491. }
  492. if (dirty & I810_UPLOAD_TEX1) {
  493. i810EmitTexVerified(dev, sarea_priv->TexState[1]);
  494. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  495. }
  496. }
  497. /* need to verify
  498. */
  499. static void i810_dma_dispatch_clear(struct drm_device * dev, int flags,
  500. unsigned int clear_color,
  501. unsigned int clear_zval)
  502. {
  503. drm_i810_private_t *dev_priv = dev->dev_private;
  504. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  505. int nbox = sarea_priv->nbox;
  506. struct drm_clip_rect *pbox = sarea_priv->boxes;
  507. int pitch = dev_priv->pitch;
  508. int cpp = 2;
  509. int i;
  510. RING_LOCALS;
  511. if (dev_priv->current_page == 1) {
  512. unsigned int tmp = flags;
  513. flags &= ~(I810_FRONT | I810_BACK);
  514. if (tmp & I810_FRONT)
  515. flags |= I810_BACK;
  516. if (tmp & I810_BACK)
  517. flags |= I810_FRONT;
  518. }
  519. i810_kernel_lost_context(dev);
  520. if (nbox > I810_NR_SAREA_CLIPRECTS)
  521. nbox = I810_NR_SAREA_CLIPRECTS;
  522. for (i = 0; i < nbox; i++, pbox++) {
  523. unsigned int x = pbox->x1;
  524. unsigned int y = pbox->y1;
  525. unsigned int width = (pbox->x2 - x) * cpp;
  526. unsigned int height = pbox->y2 - y;
  527. unsigned int start = y * pitch + x * cpp;
  528. if (pbox->x1 > pbox->x2 ||
  529. pbox->y1 > pbox->y2 ||
  530. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  531. continue;
  532. if (flags & I810_FRONT) {
  533. BEGIN_LP_RING(6);
  534. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  535. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  536. OUT_RING((height << 16) | width);
  537. OUT_RING(start);
  538. OUT_RING(clear_color);
  539. OUT_RING(0);
  540. ADVANCE_LP_RING();
  541. }
  542. if (flags & I810_BACK) {
  543. BEGIN_LP_RING(6);
  544. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  545. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  546. OUT_RING((height << 16) | width);
  547. OUT_RING(dev_priv->back_offset + start);
  548. OUT_RING(clear_color);
  549. OUT_RING(0);
  550. ADVANCE_LP_RING();
  551. }
  552. if (flags & I810_DEPTH) {
  553. BEGIN_LP_RING(6);
  554. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  555. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  556. OUT_RING((height << 16) | width);
  557. OUT_RING(dev_priv->depth_offset + start);
  558. OUT_RING(clear_zval);
  559. OUT_RING(0);
  560. ADVANCE_LP_RING();
  561. }
  562. }
  563. }
  564. static void i810_dma_dispatch_swap(struct drm_device * dev)
  565. {
  566. drm_i810_private_t *dev_priv = dev->dev_private;
  567. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  568. int nbox = sarea_priv->nbox;
  569. struct drm_clip_rect *pbox = sarea_priv->boxes;
  570. int pitch = dev_priv->pitch;
  571. int cpp = 2;
  572. int i;
  573. RING_LOCALS;
  574. DRM_DEBUG("swapbuffers\n");
  575. i810_kernel_lost_context(dev);
  576. if (nbox > I810_NR_SAREA_CLIPRECTS)
  577. nbox = I810_NR_SAREA_CLIPRECTS;
  578. for (i = 0; i < nbox; i++, pbox++) {
  579. unsigned int w = pbox->x2 - pbox->x1;
  580. unsigned int h = pbox->y2 - pbox->y1;
  581. unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
  582. unsigned int start = dst;
  583. if (pbox->x1 > pbox->x2 ||
  584. pbox->y1 > pbox->y2 ||
  585. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  586. continue;
  587. BEGIN_LP_RING(6);
  588. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
  589. OUT_RING(pitch | (0xCC << 16));
  590. OUT_RING((h << 16) | (w * cpp));
  591. if (dev_priv->current_page == 0)
  592. OUT_RING(dev_priv->front_offset + start);
  593. else
  594. OUT_RING(dev_priv->back_offset + start);
  595. OUT_RING(pitch);
  596. if (dev_priv->current_page == 0)
  597. OUT_RING(dev_priv->back_offset + start);
  598. else
  599. OUT_RING(dev_priv->front_offset + start);
  600. ADVANCE_LP_RING();
  601. }
  602. }
  603. static void i810_dma_dispatch_vertex(struct drm_device * dev,
  604. struct drm_buf * buf, int discard, int used)
  605. {
  606. drm_i810_private_t *dev_priv = dev->dev_private;
  607. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  608. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  609. struct drm_clip_rect *box = sarea_priv->boxes;
  610. int nbox = sarea_priv->nbox;
  611. unsigned long address = (unsigned long)buf->bus_address;
  612. unsigned long start = address - dev->agp->base;
  613. int i = 0;
  614. RING_LOCALS;
  615. i810_kernel_lost_context(dev);
  616. if (nbox > I810_NR_SAREA_CLIPRECTS)
  617. nbox = I810_NR_SAREA_CLIPRECTS;
  618. if (used > 4 * 1024)
  619. used = 0;
  620. if (sarea_priv->dirty)
  621. i810EmitState(dev);
  622. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  623. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  624. *(u32 *) buf_priv->kernel_virtual =
  625. ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
  626. if (used & 4) {
  627. *(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
  628. used += 4;
  629. }
  630. i810_unmap_buffer(buf);
  631. }
  632. if (used) {
  633. do {
  634. if (i < nbox) {
  635. BEGIN_LP_RING(4);
  636. OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  637. SC_ENABLE);
  638. OUT_RING(GFX_OP_SCISSOR_INFO);
  639. OUT_RING(box[i].x1 | (box[i].y1 << 16));
  640. OUT_RING((box[i].x2 -
  641. 1) | ((box[i].y2 - 1) << 16));
  642. ADVANCE_LP_RING();
  643. }
  644. BEGIN_LP_RING(4);
  645. OUT_RING(CMD_OP_BATCH_BUFFER);
  646. OUT_RING(start | BB1_PROTECTED);
  647. OUT_RING(start + used - 4);
  648. OUT_RING(0);
  649. ADVANCE_LP_RING();
  650. } while (++i < nbox);
  651. }
  652. if (discard) {
  653. dev_priv->counter++;
  654. (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  655. I810_BUF_HARDWARE);
  656. BEGIN_LP_RING(8);
  657. OUT_RING(CMD_STORE_DWORD_IDX);
  658. OUT_RING(20);
  659. OUT_RING(dev_priv->counter);
  660. OUT_RING(CMD_STORE_DWORD_IDX);
  661. OUT_RING(buf_priv->my_use_idx);
  662. OUT_RING(I810_BUF_FREE);
  663. OUT_RING(CMD_REPORT_HEAD);
  664. OUT_RING(0);
  665. ADVANCE_LP_RING();
  666. }
  667. }
  668. static void i810_dma_dispatch_flip(struct drm_device * dev)
  669. {
  670. drm_i810_private_t *dev_priv = dev->dev_private;
  671. int pitch = dev_priv->pitch;
  672. RING_LOCALS;
  673. DRM_DEBUG("page=%d pfCurrentPage=%d\n",
  674. dev_priv->current_page,
  675. dev_priv->sarea_priv->pf_current_page);
  676. i810_kernel_lost_context(dev);
  677. BEGIN_LP_RING(2);
  678. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  679. OUT_RING(0);
  680. ADVANCE_LP_RING();
  681. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  682. /* On i815 at least ASYNC is buggy */
  683. /* pitch<<5 is from 11.2.8 p158,
  684. its the pitch / 8 then left shifted 8,
  685. so (pitch >> 3) << 8 */
  686. OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
  687. if (dev_priv->current_page == 0) {
  688. OUT_RING(dev_priv->back_offset);
  689. dev_priv->current_page = 1;
  690. } else {
  691. OUT_RING(dev_priv->front_offset);
  692. dev_priv->current_page = 0;
  693. }
  694. OUT_RING(0);
  695. ADVANCE_LP_RING();
  696. BEGIN_LP_RING(2);
  697. OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
  698. OUT_RING(0);
  699. ADVANCE_LP_RING();
  700. /* Increment the frame counter. The client-side 3D driver must
  701. * throttle the framerate by waiting for this value before
  702. * performing the swapbuffer ioctl.
  703. */
  704. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  705. }
  706. static void i810_dma_quiescent(struct drm_device * dev)
  707. {
  708. drm_i810_private_t *dev_priv = dev->dev_private;
  709. RING_LOCALS;
  710. i810_kernel_lost_context(dev);
  711. BEGIN_LP_RING(4);
  712. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  713. OUT_RING(CMD_REPORT_HEAD);
  714. OUT_RING(0);
  715. OUT_RING(0);
  716. ADVANCE_LP_RING();
  717. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  718. }
  719. static int i810_flush_queue(struct drm_device * dev)
  720. {
  721. drm_i810_private_t *dev_priv = dev->dev_private;
  722. struct drm_device_dma *dma = dev->dma;
  723. int i, ret = 0;
  724. RING_LOCALS;
  725. i810_kernel_lost_context(dev);
  726. BEGIN_LP_RING(2);
  727. OUT_RING(CMD_REPORT_HEAD);
  728. OUT_RING(0);
  729. ADVANCE_LP_RING();
  730. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  731. for (i = 0; i < dma->buf_count; i++) {
  732. struct drm_buf *buf = dma->buflist[i];
  733. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  734. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  735. I810_BUF_FREE);
  736. if (used == I810_BUF_HARDWARE)
  737. DRM_DEBUG("reclaimed from HARDWARE\n");
  738. if (used == I810_BUF_CLIENT)
  739. DRM_DEBUG("still on client\n");
  740. }
  741. return ret;
  742. }
  743. /* Must be called with the lock held */
  744. static void i810_reclaim_buffers(struct drm_device * dev,
  745. struct drm_file *file_priv)
  746. {
  747. struct drm_device_dma *dma = dev->dma;
  748. int i;
  749. if (!dma)
  750. return;
  751. if (!dev->dev_private)
  752. return;
  753. if (!dma->buflist)
  754. return;
  755. i810_flush_queue(dev);
  756. for (i = 0; i < dma->buf_count; i++) {
  757. struct drm_buf *buf = dma->buflist[i];
  758. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  759. if (buf->file_priv == file_priv && buf_priv) {
  760. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  761. I810_BUF_FREE);
  762. if (used == I810_BUF_CLIENT)
  763. DRM_DEBUG("reclaimed from client\n");
  764. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  765. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  766. }
  767. }
  768. }
  769. static int i810_flush_ioctl(struct drm_device *dev, void *data,
  770. struct drm_file *file_priv)
  771. {
  772. LOCK_TEST_WITH_RETURN(dev, file_priv);
  773. i810_flush_queue(dev);
  774. return 0;
  775. }
  776. static int i810_dma_vertex(struct drm_device *dev, void *data,
  777. struct drm_file *file_priv)
  778. {
  779. struct drm_device_dma *dma = dev->dma;
  780. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  781. u32 *hw_status = dev_priv->hw_status_page;
  782. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  783. dev_priv->sarea_priv;
  784. drm_i810_vertex_t *vertex = data;
  785. LOCK_TEST_WITH_RETURN(dev, file_priv);
  786. DRM_DEBUG("idx %d used %d discard %d\n",
  787. vertex->idx, vertex->used, vertex->discard);
  788. if (vertex->idx < 0 || vertex->idx > dma->buf_count)
  789. return -EINVAL;
  790. i810_dma_dispatch_vertex(dev,
  791. dma->buflist[vertex->idx],
  792. vertex->discard, vertex->used);
  793. atomic_add(vertex->used, &dev->counts[_DRM_STAT_SECONDARY]);
  794. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  795. sarea_priv->last_enqueue = dev_priv->counter - 1;
  796. sarea_priv->last_dispatch = (int)hw_status[5];
  797. return 0;
  798. }
  799. static int i810_clear_bufs(struct drm_device *dev, void *data,
  800. struct drm_file *file_priv)
  801. {
  802. drm_i810_clear_t *clear = data;
  803. LOCK_TEST_WITH_RETURN(dev, file_priv);
  804. /* GH: Someone's doing nasty things... */
  805. if (!dev->dev_private) {
  806. return -EINVAL;
  807. }
  808. i810_dma_dispatch_clear(dev, clear->flags,
  809. clear->clear_color, clear->clear_depth);
  810. return 0;
  811. }
  812. static int i810_swap_bufs(struct drm_device *dev, void *data,
  813. struct drm_file *file_priv)
  814. {
  815. DRM_DEBUG("\n");
  816. LOCK_TEST_WITH_RETURN(dev, file_priv);
  817. i810_dma_dispatch_swap(dev);
  818. return 0;
  819. }
  820. static int i810_getage(struct drm_device *dev, void *data,
  821. struct drm_file *file_priv)
  822. {
  823. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  824. u32 *hw_status = dev_priv->hw_status_page;
  825. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  826. dev_priv->sarea_priv;
  827. sarea_priv->last_dispatch = (int)hw_status[5];
  828. return 0;
  829. }
  830. static int i810_getbuf(struct drm_device *dev, void *data,
  831. struct drm_file *file_priv)
  832. {
  833. int retcode = 0;
  834. drm_i810_dma_t *d = data;
  835. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  836. u32 *hw_status = dev_priv->hw_status_page;
  837. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  838. dev_priv->sarea_priv;
  839. LOCK_TEST_WITH_RETURN(dev, file_priv);
  840. d->granted = 0;
  841. retcode = i810_dma_get_buffer(dev, d, file_priv);
  842. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  843. task_pid_nr(current), retcode, d->granted);
  844. sarea_priv->last_dispatch = (int)hw_status[5];
  845. return retcode;
  846. }
  847. static int i810_copybuf(struct drm_device *dev, void *data,
  848. struct drm_file *file_priv)
  849. {
  850. /* Never copy - 2.4.x doesn't need it */
  851. return 0;
  852. }
  853. static int i810_docopy(struct drm_device *dev, void *data,
  854. struct drm_file *file_priv)
  855. {
  856. /* Never copy - 2.4.x doesn't need it */
  857. return 0;
  858. }
  859. static void i810_dma_dispatch_mc(struct drm_device * dev, struct drm_buf * buf, int used,
  860. unsigned int last_render)
  861. {
  862. drm_i810_private_t *dev_priv = dev->dev_private;
  863. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  864. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  865. unsigned long address = (unsigned long)buf->bus_address;
  866. unsigned long start = address - dev->agp->base;
  867. int u;
  868. RING_LOCALS;
  869. i810_kernel_lost_context(dev);
  870. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
  871. if (u != I810_BUF_CLIENT) {
  872. DRM_DEBUG("MC found buffer that isn't mine!\n");
  873. }
  874. if (used > 4 * 1024)
  875. used = 0;
  876. sarea_priv->dirty = 0x7f;
  877. DRM_DEBUG("addr 0x%lx, used 0x%x\n", address, used);
  878. dev_priv->counter++;
  879. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  880. DRM_DEBUG("start : %lx\n", start);
  881. DRM_DEBUG("used : %d\n", used);
  882. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  883. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  884. if (used & 4) {
  885. *(u32 *) ((char *) buf_priv->virtual + used) = 0;
  886. used += 4;
  887. }
  888. i810_unmap_buffer(buf);
  889. }
  890. BEGIN_LP_RING(4);
  891. OUT_RING(CMD_OP_BATCH_BUFFER);
  892. OUT_RING(start | BB1_PROTECTED);
  893. OUT_RING(start + used - 4);
  894. OUT_RING(0);
  895. ADVANCE_LP_RING();
  896. BEGIN_LP_RING(8);
  897. OUT_RING(CMD_STORE_DWORD_IDX);
  898. OUT_RING(buf_priv->my_use_idx);
  899. OUT_RING(I810_BUF_FREE);
  900. OUT_RING(0);
  901. OUT_RING(CMD_STORE_DWORD_IDX);
  902. OUT_RING(16);
  903. OUT_RING(last_render);
  904. OUT_RING(0);
  905. ADVANCE_LP_RING();
  906. }
  907. static int i810_dma_mc(struct drm_device *dev, void *data,
  908. struct drm_file *file_priv)
  909. {
  910. struct drm_device_dma *dma = dev->dma;
  911. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  912. u32 *hw_status = dev_priv->hw_status_page;
  913. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  914. dev_priv->sarea_priv;
  915. drm_i810_mc_t *mc = data;
  916. LOCK_TEST_WITH_RETURN(dev, file_priv);
  917. if (mc->idx >= dma->buf_count || mc->idx < 0)
  918. return -EINVAL;
  919. i810_dma_dispatch_mc(dev, dma->buflist[mc->idx], mc->used,
  920. mc->last_render);
  921. atomic_add(mc->used, &dev->counts[_DRM_STAT_SECONDARY]);
  922. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  923. sarea_priv->last_enqueue = dev_priv->counter - 1;
  924. sarea_priv->last_dispatch = (int)hw_status[5];
  925. return 0;
  926. }
  927. static int i810_rstatus(struct drm_device *dev, void *data,
  928. struct drm_file *file_priv)
  929. {
  930. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  931. return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
  932. }
  933. static int i810_ov0_info(struct drm_device *dev, void *data,
  934. struct drm_file *file_priv)
  935. {
  936. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  937. drm_i810_overlay_t *ov = data;
  938. ov->offset = dev_priv->overlay_offset;
  939. ov->physical = dev_priv->overlay_physical;
  940. return 0;
  941. }
  942. static int i810_fstatus(struct drm_device *dev, void *data,
  943. struct drm_file *file_priv)
  944. {
  945. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  946. LOCK_TEST_WITH_RETURN(dev, file_priv);
  947. return I810_READ(0x30008);
  948. }
  949. static int i810_ov0_flip(struct drm_device *dev, void *data,
  950. struct drm_file *file_priv)
  951. {
  952. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  953. LOCK_TEST_WITH_RETURN(dev, file_priv);
  954. //Tell the overlay to update
  955. I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
  956. return 0;
  957. }
  958. /* Not sure why this isn't set all the time:
  959. */
  960. static void i810_do_init_pageflip(struct drm_device * dev)
  961. {
  962. drm_i810_private_t *dev_priv = dev->dev_private;
  963. DRM_DEBUG("\n");
  964. dev_priv->page_flipping = 1;
  965. dev_priv->current_page = 0;
  966. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  967. }
  968. static int i810_do_cleanup_pageflip(struct drm_device * dev)
  969. {
  970. drm_i810_private_t *dev_priv = dev->dev_private;
  971. DRM_DEBUG("\n");
  972. if (dev_priv->current_page != 0)
  973. i810_dma_dispatch_flip(dev);
  974. dev_priv->page_flipping = 0;
  975. return 0;
  976. }
  977. static int i810_flip_bufs(struct drm_device *dev, void *data,
  978. struct drm_file *file_priv)
  979. {
  980. drm_i810_private_t *dev_priv = dev->dev_private;
  981. DRM_DEBUG("\n");
  982. LOCK_TEST_WITH_RETURN(dev, file_priv);
  983. if (!dev_priv->page_flipping)
  984. i810_do_init_pageflip(dev);
  985. i810_dma_dispatch_flip(dev);
  986. return 0;
  987. }
  988. int i810_driver_load(struct drm_device *dev, unsigned long flags)
  989. {
  990. /* i810 has 4 more counters */
  991. dev->counters += 4;
  992. dev->types[6] = _DRM_STAT_IRQ;
  993. dev->types[7] = _DRM_STAT_PRIMARY;
  994. dev->types[8] = _DRM_STAT_SECONDARY;
  995. dev->types[9] = _DRM_STAT_DMA;
  996. return 0;
  997. }
  998. void i810_driver_lastclose(struct drm_device * dev)
  999. {
  1000. i810_dma_cleanup(dev);
  1001. }
  1002. void i810_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
  1003. {
  1004. if (dev->dev_private) {
  1005. drm_i810_private_t *dev_priv = dev->dev_private;
  1006. if (dev_priv->page_flipping) {
  1007. i810_do_cleanup_pageflip(dev);
  1008. }
  1009. }
  1010. }
  1011. void i810_driver_reclaim_buffers_locked(struct drm_device * dev,
  1012. struct drm_file *file_priv)
  1013. {
  1014. i810_reclaim_buffers(dev, file_priv);
  1015. }
  1016. int i810_driver_dma_quiescent(struct drm_device * dev)
  1017. {
  1018. i810_dma_quiescent(dev);
  1019. return 0;
  1020. }
  1021. struct drm_ioctl_desc i810_ioctls[] = {
  1022. DRM_IOCTL_DEF(DRM_I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1023. DRM_IOCTL_DEF(DRM_I810_VERTEX, i810_dma_vertex, DRM_AUTH),
  1024. DRM_IOCTL_DEF(DRM_I810_CLEAR, i810_clear_bufs, DRM_AUTH),
  1025. DRM_IOCTL_DEF(DRM_I810_FLUSH, i810_flush_ioctl, DRM_AUTH),
  1026. DRM_IOCTL_DEF(DRM_I810_GETAGE, i810_getage, DRM_AUTH),
  1027. DRM_IOCTL_DEF(DRM_I810_GETBUF, i810_getbuf, DRM_AUTH),
  1028. DRM_IOCTL_DEF(DRM_I810_SWAP, i810_swap_bufs, DRM_AUTH),
  1029. DRM_IOCTL_DEF(DRM_I810_COPY, i810_copybuf, DRM_AUTH),
  1030. DRM_IOCTL_DEF(DRM_I810_DOCOPY, i810_docopy, DRM_AUTH),
  1031. DRM_IOCTL_DEF(DRM_I810_OV0INFO, i810_ov0_info, DRM_AUTH),
  1032. DRM_IOCTL_DEF(DRM_I810_FSTATUS, i810_fstatus, DRM_AUTH),
  1033. DRM_IOCTL_DEF(DRM_I810_OV0FLIP, i810_ov0_flip, DRM_AUTH),
  1034. DRM_IOCTL_DEF(DRM_I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1035. DRM_IOCTL_DEF(DRM_I810_RSTATUS, i810_rstatus, DRM_AUTH),
  1036. DRM_IOCTL_DEF(DRM_I810_FLIP, i810_flip_bufs, DRM_AUTH)
  1037. };
  1038. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
  1039. /**
  1040. * Determine if the device really is AGP or not.
  1041. *
  1042. * All Intel graphics chipsets are treated as AGP, even if they are really
  1043. * PCI-e.
  1044. *
  1045. * \param dev The device to be tested.
  1046. *
  1047. * \returns
  1048. * A value of 1 is always retured to indictate every i810 is AGP.
  1049. */
  1050. int i810_driver_device_is_agp(struct drm_device * dev)
  1051. {
  1052. return 1;
  1053. }