pdc_adma.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695
  1. /*
  2. * pdc_adma.c - Pacific Digital Corporation ADMA
  3. *
  4. * Maintained by: Mark Lord <mlord@pobox.com>
  5. *
  6. * Copyright 2005 Mark Lord
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2, or (at your option)
  11. * any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; see the file COPYING. If not, write to
  20. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  21. *
  22. *
  23. * libata documentation is available via 'make {ps|pdf}docs',
  24. * as Documentation/DocBook/libata.*
  25. *
  26. *
  27. * Supports ATA disks in single-packet ADMA mode.
  28. * Uses PIO for everything else.
  29. *
  30. * TODO: Use ADMA transfers for ATAPI devices, when possible.
  31. * This requires careful attention to a number of quirks of the chip.
  32. *
  33. */
  34. #include <linux/kernel.h>
  35. #include <linux/module.h>
  36. #include <linux/pci.h>
  37. #include <linux/init.h>
  38. #include <linux/blkdev.h>
  39. #include <linux/delay.h>
  40. #include <linux/interrupt.h>
  41. #include <linux/device.h>
  42. #include <scsi/scsi_host.h>
  43. #include <linux/libata.h>
  44. #define DRV_NAME "pdc_adma"
  45. #define DRV_VERSION "1.0"
  46. /* macro to calculate base address for ATA regs */
  47. #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
  48. /* macro to calculate base address for ADMA regs */
  49. #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
  50. /* macro to obtain addresses from ata_port */
  51. #define ADMA_PORT_REGS(ap) \
  52. ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
  53. enum {
  54. ADMA_MMIO_BAR = 4,
  55. ADMA_PORTS = 2,
  56. ADMA_CPB_BYTES = 40,
  57. ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
  58. ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
  59. ADMA_DMA_BOUNDARY = 0xffffffff,
  60. /* global register offsets */
  61. ADMA_MODE_LOCK = 0x00c7,
  62. /* per-channel register offsets */
  63. ADMA_CONTROL = 0x0000, /* ADMA control */
  64. ADMA_STATUS = 0x0002, /* ADMA status */
  65. ADMA_CPB_COUNT = 0x0004, /* CPB count */
  66. ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
  67. ADMA_CPB_NEXT = 0x000c, /* next CPB address */
  68. ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
  69. ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
  70. ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
  71. /* ADMA_CONTROL register bits */
  72. aNIEN = (1 << 8), /* irq mask: 1==masked */
  73. aGO = (1 << 7), /* packet trigger ("Go!") */
  74. aRSTADM = (1 << 5), /* ADMA logic reset */
  75. aPIOMD4 = 0x0003, /* PIO mode 4 */
  76. /* ADMA_STATUS register bits */
  77. aPSD = (1 << 6),
  78. aUIRQ = (1 << 4),
  79. aPERR = (1 << 0),
  80. /* CPB bits */
  81. cDONE = (1 << 0),
  82. cATERR = (1 << 3),
  83. cVLD = (1 << 0),
  84. cDAT = (1 << 2),
  85. cIEN = (1 << 3),
  86. /* PRD bits */
  87. pORD = (1 << 4),
  88. pDIRO = (1 << 5),
  89. pEND = (1 << 7),
  90. /* ATA register flags */
  91. rIGN = (1 << 5),
  92. rEND = (1 << 7),
  93. /* ATA register addresses */
  94. ADMA_REGS_CONTROL = 0x0e,
  95. ADMA_REGS_SECTOR_COUNT = 0x12,
  96. ADMA_REGS_LBA_LOW = 0x13,
  97. ADMA_REGS_LBA_MID = 0x14,
  98. ADMA_REGS_LBA_HIGH = 0x15,
  99. ADMA_REGS_DEVICE = 0x16,
  100. ADMA_REGS_COMMAND = 0x17,
  101. /* PCI device IDs */
  102. board_1841_idx = 0, /* ADMA 2-port controller */
  103. };
  104. typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
  105. struct adma_port_priv {
  106. u8 *pkt;
  107. dma_addr_t pkt_dma;
  108. adma_state_t state;
  109. };
  110. static int adma_ata_init_one(struct pci_dev *pdev,
  111. const struct pci_device_id *ent);
  112. static int adma_port_start(struct ata_port *ap);
  113. static void adma_port_stop(struct ata_port *ap);
  114. static void adma_qc_prep(struct ata_queued_cmd *qc);
  115. static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
  116. static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
  117. static void adma_freeze(struct ata_port *ap);
  118. static void adma_thaw(struct ata_port *ap);
  119. static int adma_prereset(struct ata_link *link, unsigned long deadline);
  120. static struct scsi_host_template adma_ata_sht = {
  121. ATA_BASE_SHT(DRV_NAME),
  122. .sg_tablesize = LIBATA_MAX_PRD,
  123. .dma_boundary = ADMA_DMA_BOUNDARY,
  124. };
  125. static struct ata_port_operations adma_ata_ops = {
  126. .inherits = &ata_sff_port_ops,
  127. .check_atapi_dma = adma_check_atapi_dma,
  128. .qc_prep = adma_qc_prep,
  129. .qc_issue = adma_qc_issue,
  130. .freeze = adma_freeze,
  131. .thaw = adma_thaw,
  132. .prereset = adma_prereset,
  133. .port_start = adma_port_start,
  134. .port_stop = adma_port_stop,
  135. };
  136. static struct ata_port_info adma_port_info[] = {
  137. /* board_1841_idx */
  138. {
  139. .flags = ATA_FLAG_SLAVE_POSS |
  140. ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
  141. ATA_FLAG_PIO_POLLING,
  142. .pio_mask = 0x10, /* pio4 */
  143. .udma_mask = ATA_UDMA4,
  144. .port_ops = &adma_ata_ops,
  145. },
  146. };
  147. static const struct pci_device_id adma_ata_pci_tbl[] = {
  148. { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
  149. { } /* terminate list */
  150. };
  151. static struct pci_driver adma_ata_pci_driver = {
  152. .name = DRV_NAME,
  153. .id_table = adma_ata_pci_tbl,
  154. .probe = adma_ata_init_one,
  155. .remove = ata_pci_remove_one,
  156. };
  157. static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
  158. {
  159. return 1; /* ATAPI DMA not yet supported */
  160. }
  161. static void adma_reset_engine(struct ata_port *ap)
  162. {
  163. void __iomem *chan = ADMA_PORT_REGS(ap);
  164. /* reset ADMA to idle state */
  165. writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
  166. udelay(2);
  167. writew(aPIOMD4, chan + ADMA_CONTROL);
  168. udelay(2);
  169. }
  170. static void adma_reinit_engine(struct ata_port *ap)
  171. {
  172. struct adma_port_priv *pp = ap->private_data;
  173. void __iomem *chan = ADMA_PORT_REGS(ap);
  174. /* mask/clear ATA interrupts */
  175. writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
  176. ata_sff_check_status(ap);
  177. /* reset the ADMA engine */
  178. adma_reset_engine(ap);
  179. /* set in-FIFO threshold to 0x100 */
  180. writew(0x100, chan + ADMA_FIFO_IN);
  181. /* set CPB pointer */
  182. writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
  183. /* set out-FIFO threshold to 0x100 */
  184. writew(0x100, chan + ADMA_FIFO_OUT);
  185. /* set CPB count */
  186. writew(1, chan + ADMA_CPB_COUNT);
  187. /* read/discard ADMA status */
  188. readb(chan + ADMA_STATUS);
  189. }
  190. static inline void adma_enter_reg_mode(struct ata_port *ap)
  191. {
  192. void __iomem *chan = ADMA_PORT_REGS(ap);
  193. writew(aPIOMD4, chan + ADMA_CONTROL);
  194. readb(chan + ADMA_STATUS); /* flush */
  195. }
  196. static void adma_freeze(struct ata_port *ap)
  197. {
  198. void __iomem *chan = ADMA_PORT_REGS(ap);
  199. /* mask/clear ATA interrupts */
  200. writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
  201. ata_sff_check_status(ap);
  202. /* reset ADMA to idle state */
  203. writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
  204. udelay(2);
  205. writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
  206. udelay(2);
  207. }
  208. static void adma_thaw(struct ata_port *ap)
  209. {
  210. adma_reinit_engine(ap);
  211. }
  212. static int adma_prereset(struct ata_link *link, unsigned long deadline)
  213. {
  214. struct ata_port *ap = link->ap;
  215. struct adma_port_priv *pp = ap->private_data;
  216. if (pp->state != adma_state_idle) /* healthy paranoia */
  217. pp->state = adma_state_mmio;
  218. adma_reinit_engine(ap);
  219. return ata_sff_prereset(link, deadline);
  220. }
  221. static int adma_fill_sg(struct ata_queued_cmd *qc)
  222. {
  223. struct scatterlist *sg;
  224. struct ata_port *ap = qc->ap;
  225. struct adma_port_priv *pp = ap->private_data;
  226. u8 *buf = pp->pkt, *last_buf = NULL;
  227. int i = (2 + buf[3]) * 8;
  228. u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
  229. unsigned int si;
  230. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  231. u32 addr;
  232. u32 len;
  233. addr = (u32)sg_dma_address(sg);
  234. *(__le32 *)(buf + i) = cpu_to_le32(addr);
  235. i += 4;
  236. len = sg_dma_len(sg) >> 3;
  237. *(__le32 *)(buf + i) = cpu_to_le32(len);
  238. i += 4;
  239. last_buf = &buf[i];
  240. buf[i++] = pFLAGS;
  241. buf[i++] = qc->dev->dma_mode & 0xf;
  242. buf[i++] = 0; /* pPKLW */
  243. buf[i++] = 0; /* reserved */
  244. *(__le32 *)(buf + i) =
  245. (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
  246. i += 4;
  247. VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
  248. (unsigned long)addr, len);
  249. }
  250. if (likely(last_buf))
  251. *last_buf |= pEND;
  252. return i;
  253. }
  254. static void adma_qc_prep(struct ata_queued_cmd *qc)
  255. {
  256. struct adma_port_priv *pp = qc->ap->private_data;
  257. u8 *buf = pp->pkt;
  258. u32 pkt_dma = (u32)pp->pkt_dma;
  259. int i = 0;
  260. VPRINTK("ENTER\n");
  261. adma_enter_reg_mode(qc->ap);
  262. if (qc->tf.protocol != ATA_PROT_DMA) {
  263. ata_sff_qc_prep(qc);
  264. return;
  265. }
  266. buf[i++] = 0; /* Response flags */
  267. buf[i++] = 0; /* reserved */
  268. buf[i++] = cVLD | cDAT | cIEN;
  269. i++; /* cLEN, gets filled in below */
  270. *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
  271. i += 4; /* cNCPB */
  272. i += 4; /* cPRD, gets filled in below */
  273. buf[i++] = 0; /* reserved */
  274. buf[i++] = 0; /* reserved */
  275. buf[i++] = 0; /* reserved */
  276. buf[i++] = 0; /* reserved */
  277. /* ATA registers; must be a multiple of 4 */
  278. buf[i++] = qc->tf.device;
  279. buf[i++] = ADMA_REGS_DEVICE;
  280. if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
  281. buf[i++] = qc->tf.hob_nsect;
  282. buf[i++] = ADMA_REGS_SECTOR_COUNT;
  283. buf[i++] = qc->tf.hob_lbal;
  284. buf[i++] = ADMA_REGS_LBA_LOW;
  285. buf[i++] = qc->tf.hob_lbam;
  286. buf[i++] = ADMA_REGS_LBA_MID;
  287. buf[i++] = qc->tf.hob_lbah;
  288. buf[i++] = ADMA_REGS_LBA_HIGH;
  289. }
  290. buf[i++] = qc->tf.nsect;
  291. buf[i++] = ADMA_REGS_SECTOR_COUNT;
  292. buf[i++] = qc->tf.lbal;
  293. buf[i++] = ADMA_REGS_LBA_LOW;
  294. buf[i++] = qc->tf.lbam;
  295. buf[i++] = ADMA_REGS_LBA_MID;
  296. buf[i++] = qc->tf.lbah;
  297. buf[i++] = ADMA_REGS_LBA_HIGH;
  298. buf[i++] = 0;
  299. buf[i++] = ADMA_REGS_CONTROL;
  300. buf[i++] = rIGN;
  301. buf[i++] = 0;
  302. buf[i++] = qc->tf.command;
  303. buf[i++] = ADMA_REGS_COMMAND | rEND;
  304. buf[3] = (i >> 3) - 2; /* cLEN */
  305. *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
  306. i = adma_fill_sg(qc);
  307. wmb(); /* flush PRDs and pkt to memory */
  308. #if 0
  309. /* dump out CPB + PRDs for debug */
  310. {
  311. int j, len = 0;
  312. static char obuf[2048];
  313. for (j = 0; j < i; ++j) {
  314. len += sprintf(obuf+len, "%02x ", buf[j]);
  315. if ((j & 7) == 7) {
  316. printk("%s\n", obuf);
  317. len = 0;
  318. }
  319. }
  320. if (len)
  321. printk("%s\n", obuf);
  322. }
  323. #endif
  324. }
  325. static inline void adma_packet_start(struct ata_queued_cmd *qc)
  326. {
  327. struct ata_port *ap = qc->ap;
  328. void __iomem *chan = ADMA_PORT_REGS(ap);
  329. VPRINTK("ENTER, ap %p\n", ap);
  330. /* fire up the ADMA engine */
  331. writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
  332. }
  333. static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
  334. {
  335. struct adma_port_priv *pp = qc->ap->private_data;
  336. switch (qc->tf.protocol) {
  337. case ATA_PROT_DMA:
  338. pp->state = adma_state_pkt;
  339. adma_packet_start(qc);
  340. return 0;
  341. case ATAPI_PROT_DMA:
  342. BUG();
  343. break;
  344. default:
  345. break;
  346. }
  347. pp->state = adma_state_mmio;
  348. return ata_sff_qc_issue(qc);
  349. }
  350. static inline unsigned int adma_intr_pkt(struct ata_host *host)
  351. {
  352. unsigned int handled = 0, port_no;
  353. for (port_no = 0; port_no < host->n_ports; ++port_no) {
  354. struct ata_port *ap = host->ports[port_no];
  355. struct adma_port_priv *pp;
  356. struct ata_queued_cmd *qc;
  357. void __iomem *chan = ADMA_PORT_REGS(ap);
  358. u8 status = readb(chan + ADMA_STATUS);
  359. if (status == 0)
  360. continue;
  361. handled = 1;
  362. adma_enter_reg_mode(ap);
  363. if (ap->flags & ATA_FLAG_DISABLED)
  364. continue;
  365. pp = ap->private_data;
  366. if (!pp || pp->state != adma_state_pkt)
  367. continue;
  368. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  369. if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
  370. if (status & aPERR)
  371. qc->err_mask |= AC_ERR_HOST_BUS;
  372. else if ((status & (aPSD | aUIRQ)))
  373. qc->err_mask |= AC_ERR_OTHER;
  374. if (pp->pkt[0] & cATERR)
  375. qc->err_mask |= AC_ERR_DEV;
  376. else if (pp->pkt[0] != cDONE)
  377. qc->err_mask |= AC_ERR_OTHER;
  378. if (!qc->err_mask)
  379. ata_qc_complete(qc);
  380. else {
  381. struct ata_eh_info *ehi = &ap->link.eh_info;
  382. ata_ehi_clear_desc(ehi);
  383. ata_ehi_push_desc(ehi,
  384. "ADMA-status 0x%02X", status);
  385. ata_ehi_push_desc(ehi,
  386. "pkt[0] 0x%02X", pp->pkt[0]);
  387. if (qc->err_mask == AC_ERR_DEV)
  388. ata_port_abort(ap);
  389. else
  390. ata_port_freeze(ap);
  391. }
  392. }
  393. }
  394. return handled;
  395. }
  396. static inline unsigned int adma_intr_mmio(struct ata_host *host)
  397. {
  398. unsigned int handled = 0, port_no;
  399. for (port_no = 0; port_no < host->n_ports; ++port_no) {
  400. struct ata_port *ap;
  401. ap = host->ports[port_no];
  402. if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
  403. struct ata_queued_cmd *qc;
  404. struct adma_port_priv *pp = ap->private_data;
  405. if (!pp || pp->state != adma_state_mmio)
  406. continue;
  407. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  408. if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
  409. /* check main status, clearing INTRQ */
  410. u8 status = ata_sff_check_status(ap);
  411. if ((status & ATA_BUSY))
  412. continue;
  413. DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
  414. ap->print_id, qc->tf.protocol, status);
  415. /* complete taskfile transaction */
  416. pp->state = adma_state_idle;
  417. qc->err_mask |= ac_err_mask(status);
  418. if (!qc->err_mask)
  419. ata_qc_complete(qc);
  420. else {
  421. struct ata_eh_info *ehi =
  422. &ap->link.eh_info;
  423. ata_ehi_clear_desc(ehi);
  424. ata_ehi_push_desc(ehi,
  425. "status 0x%02X", status);
  426. if (qc->err_mask == AC_ERR_DEV)
  427. ata_port_abort(ap);
  428. else
  429. ata_port_freeze(ap);
  430. }
  431. handled = 1;
  432. }
  433. }
  434. }
  435. return handled;
  436. }
  437. static irqreturn_t adma_intr(int irq, void *dev_instance)
  438. {
  439. struct ata_host *host = dev_instance;
  440. unsigned int handled = 0;
  441. VPRINTK("ENTER\n");
  442. spin_lock(&host->lock);
  443. handled = adma_intr_pkt(host) | adma_intr_mmio(host);
  444. spin_unlock(&host->lock);
  445. VPRINTK("EXIT\n");
  446. return IRQ_RETVAL(handled);
  447. }
  448. static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
  449. {
  450. port->cmd_addr =
  451. port->data_addr = base + 0x000;
  452. port->error_addr =
  453. port->feature_addr = base + 0x004;
  454. port->nsect_addr = base + 0x008;
  455. port->lbal_addr = base + 0x00c;
  456. port->lbam_addr = base + 0x010;
  457. port->lbah_addr = base + 0x014;
  458. port->device_addr = base + 0x018;
  459. port->status_addr =
  460. port->command_addr = base + 0x01c;
  461. port->altstatus_addr =
  462. port->ctl_addr = base + 0x038;
  463. }
  464. static int adma_port_start(struct ata_port *ap)
  465. {
  466. struct device *dev = ap->host->dev;
  467. struct adma_port_priv *pp;
  468. int rc;
  469. rc = ata_port_start(ap);
  470. if (rc)
  471. return rc;
  472. adma_enter_reg_mode(ap);
  473. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  474. if (!pp)
  475. return -ENOMEM;
  476. pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
  477. GFP_KERNEL);
  478. if (!pp->pkt)
  479. return -ENOMEM;
  480. /* paranoia? */
  481. if ((pp->pkt_dma & 7) != 0) {
  482. printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
  483. (u32)pp->pkt_dma);
  484. return -ENOMEM;
  485. }
  486. memset(pp->pkt, 0, ADMA_PKT_BYTES);
  487. ap->private_data = pp;
  488. adma_reinit_engine(ap);
  489. return 0;
  490. }
  491. static void adma_port_stop(struct ata_port *ap)
  492. {
  493. adma_reset_engine(ap);
  494. }
  495. static void adma_host_init(struct ata_host *host, unsigned int chip_id)
  496. {
  497. unsigned int port_no;
  498. /* enable/lock aGO operation */
  499. writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
  500. /* reset the ADMA logic */
  501. for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
  502. adma_reset_engine(host->ports[port_no]);
  503. }
  504. static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
  505. {
  506. int rc;
  507. rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  508. if (rc) {
  509. dev_printk(KERN_ERR, &pdev->dev,
  510. "32-bit DMA enable failed\n");
  511. return rc;
  512. }
  513. rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  514. if (rc) {
  515. dev_printk(KERN_ERR, &pdev->dev,
  516. "32-bit consistent DMA enable failed\n");
  517. return rc;
  518. }
  519. return 0;
  520. }
  521. static int adma_ata_init_one(struct pci_dev *pdev,
  522. const struct pci_device_id *ent)
  523. {
  524. static int printed_version;
  525. unsigned int board_idx = (unsigned int) ent->driver_data;
  526. const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
  527. struct ata_host *host;
  528. void __iomem *mmio_base;
  529. int rc, port_no;
  530. if (!printed_version++)
  531. dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
  532. /* alloc host */
  533. host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
  534. if (!host)
  535. return -ENOMEM;
  536. /* acquire resources and fill host */
  537. rc = pcim_enable_device(pdev);
  538. if (rc)
  539. return rc;
  540. if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
  541. return -ENODEV;
  542. rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
  543. if (rc)
  544. return rc;
  545. host->iomap = pcim_iomap_table(pdev);
  546. mmio_base = host->iomap[ADMA_MMIO_BAR];
  547. rc = adma_set_dma_masks(pdev, mmio_base);
  548. if (rc)
  549. return rc;
  550. for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
  551. struct ata_port *ap = host->ports[port_no];
  552. void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
  553. unsigned int offset = port_base - mmio_base;
  554. adma_ata_setup_port(&ap->ioaddr, port_base);
  555. ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
  556. ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
  557. }
  558. /* initialize adapter */
  559. adma_host_init(host, board_idx);
  560. pci_set_master(pdev);
  561. return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
  562. &adma_ata_sht);
  563. }
  564. static int __init adma_ata_init(void)
  565. {
  566. return pci_register_driver(&adma_ata_pci_driver);
  567. }
  568. static void __exit adma_ata_exit(void)
  569. {
  570. pci_unregister_driver(&adma_ata_pci_driver);
  571. }
  572. MODULE_AUTHOR("Mark Lord");
  573. MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
  574. MODULE_LICENSE("GPL");
  575. MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
  576. MODULE_VERSION(DRV_VERSION);
  577. module_init(adma_ata_init);
  578. module_exit(adma_ata_exit);