tlb_uv.c 21 KB

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  1. /*
  2. * SGI UltraViolet TLB flush routines.
  3. *
  4. * (c) 2008 Cliff Wickman <cpw@sgi.com>, SGI.
  5. *
  6. * This code is released under the GNU General Public License version 2 or
  7. * later.
  8. */
  9. #include <linux/mc146818rtc.h>
  10. #include <linux/proc_fs.h>
  11. #include <linux/kernel.h>
  12. #include <asm/mmu_context.h>
  13. #include <asm/uv/uv_mmrs.h>
  14. #include <asm/uv/uv_hub.h>
  15. #include <asm/uv/uv_bau.h>
  16. #include <asm/genapic.h>
  17. #include <asm/idle.h>
  18. #include <asm/tsc.h>
  19. #include <asm/irq_vectors.h>
  20. #include <mach_apic.h>
  21. static struct bau_control **uv_bau_table_bases __read_mostly;
  22. static int uv_bau_retry_limit __read_mostly;
  23. /* position of pnode (which is nasid>>1): */
  24. static int uv_nshift __read_mostly;
  25. static unsigned long uv_mmask __read_mostly;
  26. static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
  27. static DEFINE_PER_CPU(struct bau_control, bau_control);
  28. /*
  29. * Free a software acknowledge hardware resource by clearing its Pending
  30. * bit. This will return a reply to the sender.
  31. * If the message has timed out, a reply has already been sent by the
  32. * hardware but the resource has not been released. In that case our
  33. * clear of the Timeout bit (as well) will free the resource. No reply will
  34. * be sent (the hardware will only do one reply per message).
  35. */
  36. static void uv_reply_to_message(int resource,
  37. struct bau_payload_queue_entry *msg,
  38. struct bau_msg_status *msp)
  39. {
  40. unsigned long dw;
  41. dw = (1 << (resource + UV_SW_ACK_NPENDING)) | (1 << resource);
  42. msg->replied_to = 1;
  43. msg->sw_ack_vector = 0;
  44. if (msp)
  45. msp->seen_by.bits = 0;
  46. uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw);
  47. }
  48. /*
  49. * Do all the things a cpu should do for a TLB shootdown message.
  50. * Other cpu's may come here at the same time for this message.
  51. */
  52. static void uv_bau_process_message(struct bau_payload_queue_entry *msg,
  53. int msg_slot, int sw_ack_slot)
  54. {
  55. unsigned long this_cpu_mask;
  56. struct bau_msg_status *msp;
  57. int cpu;
  58. msp = __get_cpu_var(bau_control).msg_statuses + msg_slot;
  59. cpu = uv_blade_processor_id();
  60. msg->number_of_cpus =
  61. uv_blade_nr_online_cpus(uv_node_to_blade_id(numa_node_id()));
  62. this_cpu_mask = 1UL << cpu;
  63. if (msp->seen_by.bits & this_cpu_mask)
  64. return;
  65. atomic_or_long(&msp->seen_by.bits, this_cpu_mask);
  66. if (msg->replied_to == 1)
  67. return;
  68. if (msg->address == TLB_FLUSH_ALL) {
  69. local_flush_tlb();
  70. __get_cpu_var(ptcstats).alltlb++;
  71. } else {
  72. __flush_tlb_one(msg->address);
  73. __get_cpu_var(ptcstats).onetlb++;
  74. }
  75. __get_cpu_var(ptcstats).requestee++;
  76. atomic_inc_short(&msg->acknowledge_count);
  77. if (msg->number_of_cpus == msg->acknowledge_count)
  78. uv_reply_to_message(sw_ack_slot, msg, msp);
  79. }
  80. /*
  81. * Examine the payload queue on one distribution node to see
  82. * which messages have not been seen, and which cpu(s) have not seen them.
  83. *
  84. * Returns the number of cpu's that have not responded.
  85. */
  86. static int uv_examine_destination(struct bau_control *bau_tablesp, int sender)
  87. {
  88. struct bau_payload_queue_entry *msg;
  89. struct bau_msg_status *msp;
  90. int count = 0;
  91. int i;
  92. int j;
  93. for (msg = bau_tablesp->va_queue_first, i = 0; i < DEST_Q_SIZE;
  94. msg++, i++) {
  95. if ((msg->sending_cpu == sender) && (!msg->replied_to)) {
  96. msp = bau_tablesp->msg_statuses + i;
  97. printk(KERN_DEBUG
  98. "blade %d: address:%#lx %d of %d, not cpu(s): ",
  99. i, msg->address, msg->acknowledge_count,
  100. msg->number_of_cpus);
  101. for (j = 0; j < msg->number_of_cpus; j++) {
  102. if (!((1L << j) & msp->seen_by.bits)) {
  103. count++;
  104. printk("%d ", j);
  105. }
  106. }
  107. printk("\n");
  108. }
  109. }
  110. return count;
  111. }
  112. /*
  113. * Examine the payload queue on all the distribution nodes to see
  114. * which messages have not been seen, and which cpu(s) have not seen them.
  115. *
  116. * Returns the number of cpu's that have not responded.
  117. */
  118. static int uv_examine_destinations(struct bau_target_nodemask *distribution)
  119. {
  120. int sender;
  121. int i;
  122. int count = 0;
  123. sender = smp_processor_id();
  124. for (i = 0; i < sizeof(struct bau_target_nodemask) * BITSPERBYTE; i++) {
  125. if (!bau_node_isset(i, distribution))
  126. continue;
  127. count += uv_examine_destination(uv_bau_table_bases[i], sender);
  128. }
  129. return count;
  130. }
  131. /*
  132. * wait for completion of a broadcast message
  133. *
  134. * return COMPLETE, RETRY or GIVEUP
  135. */
  136. static int uv_wait_completion(struct bau_desc *bau_desc,
  137. unsigned long mmr_offset, int right_shift)
  138. {
  139. int exams = 0;
  140. long destination_timeouts = 0;
  141. long source_timeouts = 0;
  142. unsigned long descriptor_status;
  143. while ((descriptor_status = (((unsigned long)
  144. uv_read_local_mmr(mmr_offset) >>
  145. right_shift) & UV_ACT_STATUS_MASK)) !=
  146. DESC_STATUS_IDLE) {
  147. if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) {
  148. source_timeouts++;
  149. if (source_timeouts > SOURCE_TIMEOUT_LIMIT)
  150. source_timeouts = 0;
  151. __get_cpu_var(ptcstats).s_retry++;
  152. return FLUSH_RETRY;
  153. }
  154. /*
  155. * spin here looking for progress at the destinations
  156. */
  157. if (descriptor_status == DESC_STATUS_DESTINATION_TIMEOUT) {
  158. destination_timeouts++;
  159. if (destination_timeouts > DESTINATION_TIMEOUT_LIMIT) {
  160. /*
  161. * returns number of cpus not responding
  162. */
  163. if (uv_examine_destinations
  164. (&bau_desc->distribution) == 0) {
  165. __get_cpu_var(ptcstats).d_retry++;
  166. return FLUSH_RETRY;
  167. }
  168. exams++;
  169. if (exams >= uv_bau_retry_limit) {
  170. printk(KERN_DEBUG
  171. "uv_flush_tlb_others");
  172. printk("giving up on cpu %d\n",
  173. smp_processor_id());
  174. return FLUSH_GIVEUP;
  175. }
  176. /*
  177. * delays can hang the simulator
  178. udelay(1000);
  179. */
  180. destination_timeouts = 0;
  181. }
  182. }
  183. }
  184. return FLUSH_COMPLETE;
  185. }
  186. /**
  187. * uv_flush_send_and_wait
  188. *
  189. * Send a broadcast and wait for a broadcast message to complete.
  190. *
  191. * The cpumaskp mask contains the cpus the broadcast was sent to.
  192. *
  193. * Returns 1 if all remote flushing was done. The mask is zeroed.
  194. * Returns 0 if some remote flushing remains to be done. The mask is left
  195. * unchanged.
  196. */
  197. int uv_flush_send_and_wait(int cpu, int this_blade, struct bau_desc *bau_desc,
  198. cpumask_t *cpumaskp)
  199. {
  200. int completion_status = 0;
  201. int right_shift;
  202. int tries = 0;
  203. int blade;
  204. int bit;
  205. unsigned long mmr_offset;
  206. unsigned long index;
  207. cycles_t time1;
  208. cycles_t time2;
  209. if (cpu < UV_CPUS_PER_ACT_STATUS) {
  210. mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
  211. right_shift = cpu * UV_ACT_STATUS_SIZE;
  212. } else {
  213. mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
  214. right_shift =
  215. ((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE);
  216. }
  217. time1 = get_cycles();
  218. do {
  219. tries++;
  220. index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) |
  221. cpu;
  222. uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
  223. completion_status = uv_wait_completion(bau_desc, mmr_offset,
  224. right_shift);
  225. } while (completion_status == FLUSH_RETRY);
  226. time2 = get_cycles();
  227. __get_cpu_var(ptcstats).sflush += (time2 - time1);
  228. if (tries > 1)
  229. __get_cpu_var(ptcstats).retriesok++;
  230. if (completion_status == FLUSH_GIVEUP) {
  231. /*
  232. * Cause the caller to do an IPI-style TLB shootdown on
  233. * the cpu's, all of which are still in the mask.
  234. */
  235. __get_cpu_var(ptcstats).ptc_i++;
  236. return 0;
  237. }
  238. /*
  239. * Success, so clear the remote cpu's from the mask so we don't
  240. * use the IPI method of shootdown on them.
  241. */
  242. for_each_cpu_mask(bit, *cpumaskp) {
  243. blade = uv_cpu_to_blade_id(bit);
  244. if (blade == this_blade)
  245. continue;
  246. cpu_clear(bit, *cpumaskp);
  247. }
  248. if (!cpus_empty(*cpumaskp))
  249. return 0;
  250. return 1;
  251. }
  252. /**
  253. * uv_flush_tlb_others - globally purge translation cache of a virtual
  254. * address or all TLB's
  255. * @cpumaskp: mask of all cpu's in which the address is to be removed
  256. * @mm: mm_struct containing virtual address range
  257. * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu)
  258. *
  259. * This is the entry point for initiating any UV global TLB shootdown.
  260. *
  261. * Purges the translation caches of all specified processors of the given
  262. * virtual address, or purges all TLB's on specified processors.
  263. *
  264. * The caller has derived the cpumaskp from the mm_struct and has subtracted
  265. * the local cpu from the mask. This function is called only if there
  266. * are bits set in the mask. (e.g. flush_tlb_page())
  267. *
  268. * The cpumaskp is converted into a nodemask of the nodes containing
  269. * the cpus.
  270. *
  271. * Returns 1 if all remote flushing was done.
  272. * Returns 0 if some remote flushing remains to be done.
  273. */
  274. int uv_flush_tlb_others(cpumask_t *cpumaskp, struct mm_struct *mm,
  275. unsigned long va)
  276. {
  277. int i;
  278. int bit;
  279. int blade;
  280. int cpu;
  281. int this_blade;
  282. int locals = 0;
  283. struct bau_desc *bau_desc;
  284. cpu = uv_blade_processor_id();
  285. this_blade = uv_numa_blade_id();
  286. bau_desc = __get_cpu_var(bau_control).descriptor_base;
  287. bau_desc += UV_ITEMS_PER_DESCRIPTOR * cpu;
  288. bau_nodes_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
  289. i = 0;
  290. for_each_cpu_mask(bit, *cpumaskp) {
  291. blade = uv_cpu_to_blade_id(bit);
  292. BUG_ON(blade > (UV_DISTRIBUTION_SIZE - 1));
  293. if (blade == this_blade) {
  294. locals++;
  295. continue;
  296. }
  297. bau_node_set(blade, &bau_desc->distribution);
  298. i++;
  299. }
  300. if (i == 0) {
  301. /*
  302. * no off_node flushing; return status for local node
  303. */
  304. if (locals)
  305. return 0;
  306. else
  307. return 1;
  308. }
  309. __get_cpu_var(ptcstats).requestor++;
  310. __get_cpu_var(ptcstats).ntargeted += i;
  311. bau_desc->payload.address = va;
  312. bau_desc->payload.sending_cpu = smp_processor_id();
  313. return uv_flush_send_and_wait(cpu, this_blade, bau_desc, cpumaskp);
  314. }
  315. /*
  316. * The BAU message interrupt comes here. (registered by set_intr_gate)
  317. * See entry_64.S
  318. *
  319. * We received a broadcast assist message.
  320. *
  321. * Interrupts may have been disabled; this interrupt could represent
  322. * the receipt of several messages.
  323. *
  324. * All cores/threads on this node get this interrupt.
  325. * The last one to see it does the s/w ack.
  326. * (the resource will not be freed until noninterruptable cpus see this
  327. * interrupt; hardware will timeout the s/w ack and reply ERROR)
  328. */
  329. void uv_bau_message_interrupt(struct pt_regs *regs)
  330. {
  331. struct bau_payload_queue_entry *va_queue_first;
  332. struct bau_payload_queue_entry *va_queue_last;
  333. struct bau_payload_queue_entry *msg;
  334. struct pt_regs *old_regs = set_irq_regs(regs);
  335. cycles_t time1;
  336. cycles_t time2;
  337. int msg_slot;
  338. int sw_ack_slot;
  339. int fw;
  340. int count = 0;
  341. unsigned long local_pnode;
  342. ack_APIC_irq();
  343. exit_idle();
  344. irq_enter();
  345. time1 = get_cycles();
  346. local_pnode = uv_blade_to_pnode(uv_numa_blade_id());
  347. va_queue_first = __get_cpu_var(bau_control).va_queue_first;
  348. va_queue_last = __get_cpu_var(bau_control).va_queue_last;
  349. msg = __get_cpu_var(bau_control).bau_msg_head;
  350. while (msg->sw_ack_vector) {
  351. count++;
  352. fw = msg->sw_ack_vector;
  353. msg_slot = msg - va_queue_first;
  354. sw_ack_slot = ffs(fw) - 1;
  355. uv_bau_process_message(msg, msg_slot, sw_ack_slot);
  356. msg++;
  357. if (msg > va_queue_last)
  358. msg = va_queue_first;
  359. __get_cpu_var(bau_control).bau_msg_head = msg;
  360. }
  361. if (!count)
  362. __get_cpu_var(ptcstats).nomsg++;
  363. else if (count > 1)
  364. __get_cpu_var(ptcstats).multmsg++;
  365. time2 = get_cycles();
  366. __get_cpu_var(ptcstats).dflush += (time2 - time1);
  367. irq_exit();
  368. set_irq_regs(old_regs);
  369. }
  370. static void uv_enable_timeouts(void)
  371. {
  372. int i;
  373. int blade;
  374. int last_blade;
  375. int pnode;
  376. int cur_cpu = 0;
  377. unsigned long apicid;
  378. last_blade = -1;
  379. for_each_online_node(i) {
  380. blade = uv_node_to_blade_id(i);
  381. if (blade == last_blade)
  382. continue;
  383. last_blade = blade;
  384. apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
  385. pnode = uv_blade_to_pnode(blade);
  386. cur_cpu += uv_blade_nr_possible_cpus(i);
  387. }
  388. }
  389. static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset)
  390. {
  391. if (*offset < num_possible_cpus())
  392. return offset;
  393. return NULL;
  394. }
  395. static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
  396. {
  397. (*offset)++;
  398. if (*offset < num_possible_cpus())
  399. return offset;
  400. return NULL;
  401. }
  402. static void uv_ptc_seq_stop(struct seq_file *file, void *data)
  403. {
  404. }
  405. /*
  406. * Display the statistics thru /proc
  407. * data points to the cpu number
  408. */
  409. static int uv_ptc_seq_show(struct seq_file *file, void *data)
  410. {
  411. struct ptc_stats *stat;
  412. int cpu;
  413. cpu = *(loff_t *)data;
  414. if (!cpu) {
  415. seq_printf(file,
  416. "# cpu requestor requestee one all sretry dretry ptc_i ");
  417. seq_printf(file,
  418. "sw_ack sflush dflush sok dnomsg dmult starget\n");
  419. }
  420. if (cpu < num_possible_cpus() && cpu_online(cpu)) {
  421. stat = &per_cpu(ptcstats, cpu);
  422. seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld ",
  423. cpu, stat->requestor,
  424. stat->requestee, stat->onetlb, stat->alltlb,
  425. stat->s_retry, stat->d_retry, stat->ptc_i);
  426. seq_printf(file, "%lx %ld %ld %ld %ld %ld %ld\n",
  427. uv_read_global_mmr64(uv_blade_to_pnode
  428. (uv_cpu_to_blade_id(cpu)),
  429. UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE),
  430. stat->sflush, stat->dflush,
  431. stat->retriesok, stat->nomsg,
  432. stat->multmsg, stat->ntargeted);
  433. }
  434. return 0;
  435. }
  436. /*
  437. * 0: display meaning of the statistics
  438. * >0: retry limit
  439. */
  440. static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user,
  441. size_t count, loff_t *data)
  442. {
  443. long newmode;
  444. char optstr[64];
  445. if (count == 0 || count > sizeof(optstr))
  446. return -EINVAL;
  447. if (copy_from_user(optstr, user, count))
  448. return -EFAULT;
  449. optstr[count - 1] = '\0';
  450. if (strict_strtoul(optstr, 10, &newmode) < 0) {
  451. printk(KERN_DEBUG "%s is invalid\n", optstr);
  452. return -EINVAL;
  453. }
  454. if (newmode == 0) {
  455. printk(KERN_DEBUG "# cpu: cpu number\n");
  456. printk(KERN_DEBUG
  457. "requestor: times this cpu was the flush requestor\n");
  458. printk(KERN_DEBUG
  459. "requestee: times this cpu was requested to flush its TLBs\n");
  460. printk(KERN_DEBUG
  461. "one: times requested to flush a single address\n");
  462. printk(KERN_DEBUG
  463. "all: times requested to flush all TLB's\n");
  464. printk(KERN_DEBUG
  465. "sretry: number of retries of source-side timeouts\n");
  466. printk(KERN_DEBUG
  467. "dretry: number of retries of destination-side timeouts\n");
  468. printk(KERN_DEBUG
  469. "ptc_i: times UV fell through to IPI-style flushes\n");
  470. printk(KERN_DEBUG
  471. "sw_ack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n");
  472. printk(KERN_DEBUG
  473. "sflush_us: cycles spent in uv_flush_tlb_others()\n");
  474. printk(KERN_DEBUG
  475. "dflush_us: cycles spent in handling flush requests\n");
  476. printk(KERN_DEBUG "sok: successes on retry\n");
  477. printk(KERN_DEBUG "dnomsg: interrupts with no message\n");
  478. printk(KERN_DEBUG
  479. "dmult: interrupts with multiple messages\n");
  480. printk(KERN_DEBUG "starget: nodes targeted\n");
  481. } else {
  482. uv_bau_retry_limit = newmode;
  483. printk(KERN_DEBUG "timeout retry limit:%d\n",
  484. uv_bau_retry_limit);
  485. }
  486. return count;
  487. }
  488. static const struct seq_operations uv_ptc_seq_ops = {
  489. .start = uv_ptc_seq_start,
  490. .next = uv_ptc_seq_next,
  491. .stop = uv_ptc_seq_stop,
  492. .show = uv_ptc_seq_show
  493. };
  494. static int uv_ptc_proc_open(struct inode *inode, struct file *file)
  495. {
  496. return seq_open(file, &uv_ptc_seq_ops);
  497. }
  498. static const struct file_operations proc_uv_ptc_operations = {
  499. .open = uv_ptc_proc_open,
  500. .read = seq_read,
  501. .write = uv_ptc_proc_write,
  502. .llseek = seq_lseek,
  503. .release = seq_release,
  504. };
  505. static int __init uv_ptc_init(void)
  506. {
  507. struct proc_dir_entry *proc_uv_ptc;
  508. if (!is_uv_system())
  509. return 0;
  510. if (!proc_mkdir("sgi_uv", NULL))
  511. return -EINVAL;
  512. proc_uv_ptc = create_proc_entry(UV_PTC_BASENAME, 0444, NULL);
  513. if (!proc_uv_ptc) {
  514. printk(KERN_ERR "unable to create %s proc entry\n",
  515. UV_PTC_BASENAME);
  516. remove_proc_entry("sgi_uv", NULL);
  517. return -EINVAL;
  518. }
  519. proc_uv_ptc->proc_fops = &proc_uv_ptc_operations;
  520. return 0;
  521. }
  522. /*
  523. * begin the initialization of the per-blade control structures
  524. */
  525. static struct bau_control * __init uv_table_bases_init(int blade, int node)
  526. {
  527. int i;
  528. int *ip;
  529. struct bau_msg_status *msp;
  530. struct bau_control *bau_tabp;
  531. bau_tabp =
  532. kmalloc_node(sizeof(struct bau_control), GFP_KERNEL, node);
  533. BUG_ON(!bau_tabp);
  534. bau_tabp->msg_statuses =
  535. kmalloc_node(sizeof(struct bau_msg_status) *
  536. DEST_Q_SIZE, GFP_KERNEL, node);
  537. BUG_ON(!bau_tabp->msg_statuses);
  538. for (i = 0, msp = bau_tabp->msg_statuses; i < DEST_Q_SIZE; i++, msp++)
  539. bau_cpubits_clear(&msp->seen_by, (int)
  540. uv_blade_nr_possible_cpus(blade));
  541. bau_tabp->watching =
  542. kmalloc_node(sizeof(int) * DEST_NUM_RESOURCES, GFP_KERNEL, node);
  543. BUG_ON(!bau_tabp->watching);
  544. for (i = 0, ip = bau_tabp->watching; i < DEST_Q_SIZE; i++, ip++)
  545. *ip = 0;
  546. uv_bau_table_bases[blade] = bau_tabp;
  547. return bau_tabp;
  548. }
  549. /*
  550. * finish the initialization of the per-blade control structures
  551. */
  552. static void __init
  553. uv_table_bases_finish(int blade, int node, int cur_cpu,
  554. struct bau_control *bau_tablesp,
  555. struct bau_desc *adp)
  556. {
  557. struct bau_control *bcp;
  558. int i;
  559. for (i = cur_cpu; i < cur_cpu + uv_blade_nr_possible_cpus(blade); i++) {
  560. bcp = (struct bau_control *)&per_cpu(bau_control, i);
  561. bcp->bau_msg_head = bau_tablesp->va_queue_first;
  562. bcp->va_queue_first = bau_tablesp->va_queue_first;
  563. bcp->va_queue_last = bau_tablesp->va_queue_last;
  564. bcp->watching = bau_tablesp->watching;
  565. bcp->msg_statuses = bau_tablesp->msg_statuses;
  566. bcp->descriptor_base = adp;
  567. }
  568. }
  569. /*
  570. * initialize the sending side's sending buffers
  571. */
  572. static struct bau_desc * __init
  573. uv_activation_descriptor_init(int node, int pnode)
  574. {
  575. int i;
  576. unsigned long pa;
  577. unsigned long m;
  578. unsigned long n;
  579. unsigned long mmr_image;
  580. struct bau_desc *adp;
  581. struct bau_desc *ad2;
  582. adp = (struct bau_desc *)
  583. kmalloc_node(16384, GFP_KERNEL, node);
  584. BUG_ON(!adp);
  585. pa = __pa((unsigned long)adp);
  586. n = pa >> uv_nshift;
  587. m = pa & uv_mmask;
  588. mmr_image = uv_read_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE);
  589. if (mmr_image) {
  590. uv_write_global_mmr64(pnode, (unsigned long)
  591. UVH_LB_BAU_SB_DESCRIPTOR_BASE,
  592. (n << UV_DESC_BASE_PNODE_SHIFT | m));
  593. }
  594. for (i = 0, ad2 = adp; i < UV_ACTIVATION_DESCRIPTOR_SIZE; i++, ad2++) {
  595. memset(ad2, 0, sizeof(struct bau_desc));
  596. ad2->header.sw_ack_flag = 1;
  597. ad2->header.base_dest_nodeid =
  598. uv_blade_to_pnode(uv_cpu_to_blade_id(0));
  599. ad2->header.command = UV_NET_ENDPOINT_INTD;
  600. ad2->header.int_both = 1;
  601. /*
  602. * all others need to be set to zero:
  603. * fairness chaining multilevel count replied_to
  604. */
  605. }
  606. return adp;
  607. }
  608. /*
  609. * initialize the destination side's receiving buffers
  610. */
  611. static struct bau_payload_queue_entry * __init
  612. uv_payload_queue_init(int node, int pnode, struct bau_control *bau_tablesp)
  613. {
  614. struct bau_payload_queue_entry *pqp;
  615. char *cp;
  616. pqp = (struct bau_payload_queue_entry *) kmalloc_node(
  617. (DEST_Q_SIZE + 1) * sizeof(struct bau_payload_queue_entry),
  618. GFP_KERNEL, node);
  619. BUG_ON(!pqp);
  620. cp = (char *)pqp + 31;
  621. pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5);
  622. bau_tablesp->va_queue_first = pqp;
  623. uv_write_global_mmr64(pnode,
  624. UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST,
  625. ((unsigned long)pnode <<
  626. UV_PAYLOADQ_PNODE_SHIFT) |
  627. uv_physnodeaddr(pqp));
  628. uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL,
  629. uv_physnodeaddr(pqp));
  630. bau_tablesp->va_queue_last = pqp + (DEST_Q_SIZE - 1);
  631. uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST,
  632. (unsigned long)
  633. uv_physnodeaddr(bau_tablesp->va_queue_last));
  634. memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE);
  635. return pqp;
  636. }
  637. /*
  638. * Initialization of each UV blade's structures
  639. */
  640. static int __init uv_init_blade(int blade, int node, int cur_cpu)
  641. {
  642. int pnode;
  643. unsigned long pa;
  644. unsigned long apicid;
  645. struct bau_desc *adp;
  646. struct bau_payload_queue_entry *pqp;
  647. struct bau_control *bau_tablesp;
  648. bau_tablesp = uv_table_bases_init(blade, node);
  649. pnode = uv_blade_to_pnode(blade);
  650. adp = uv_activation_descriptor_init(node, pnode);
  651. pqp = uv_payload_queue_init(node, pnode, bau_tablesp);
  652. uv_table_bases_finish(blade, node, cur_cpu, bau_tablesp, adp);
  653. /*
  654. * the below initialization can't be in firmware because the
  655. * messaging IRQ will be determined by the OS
  656. */
  657. apicid = per_cpu(x86_cpu_to_apicid, cur_cpu);
  658. pa = uv_read_global_mmr64(pnode, UVH_BAU_DATA_CONFIG);
  659. if ((pa & 0xff) != UV_BAU_MESSAGE) {
  660. uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG,
  661. ((apicid << 32) | UV_BAU_MESSAGE));
  662. }
  663. return 0;
  664. }
  665. /*
  666. * Initialization of BAU-related structures
  667. */
  668. static int __init uv_bau_init(void)
  669. {
  670. int blade;
  671. int node;
  672. int nblades;
  673. int last_blade;
  674. int cur_cpu = 0;
  675. if (!is_uv_system())
  676. return 0;
  677. uv_bau_retry_limit = 1;
  678. uv_nshift = uv_hub_info->n_val;
  679. uv_mmask = (1UL << uv_hub_info->n_val) - 1;
  680. nblades = 0;
  681. last_blade = -1;
  682. for_each_online_node(node) {
  683. blade = uv_node_to_blade_id(node);
  684. if (blade == last_blade)
  685. continue;
  686. last_blade = blade;
  687. nblades++;
  688. }
  689. uv_bau_table_bases = (struct bau_control **)
  690. kmalloc(nblades * sizeof(struct bau_control *), GFP_KERNEL);
  691. BUG_ON(!uv_bau_table_bases);
  692. last_blade = -1;
  693. for_each_online_node(node) {
  694. blade = uv_node_to_blade_id(node);
  695. if (blade == last_blade)
  696. continue;
  697. last_blade = blade;
  698. uv_init_blade(blade, node, cur_cpu);
  699. cur_cpu += uv_blade_nr_possible_cpus(blade);
  700. }
  701. alloc_intr_gate(UV_BAU_MESSAGE, uv_bau_message_intr1);
  702. uv_enable_timeouts();
  703. return 0;
  704. }
  705. __initcall(uv_bau_init);
  706. __initcall(uv_ptc_init);