mce_intel_64.c 2.1 KB

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  1. /*
  2. * Intel specific MCE features.
  3. * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
  4. */
  5. #include <linux/init.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/percpu.h>
  8. #include <asm/processor.h>
  9. #include <asm/msr.h>
  10. #include <asm/mce.h>
  11. #include <asm/hw_irq.h>
  12. #include <asm/idle.h>
  13. #include <asm/therm_throt.h>
  14. asmlinkage void smp_thermal_interrupt(void)
  15. {
  16. __u64 msr_val;
  17. ack_APIC_irq();
  18. exit_idle();
  19. irq_enter();
  20. rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
  21. if (therm_throt_process(msr_val & 1))
  22. mce_log_therm_throt_event(smp_processor_id(), msr_val);
  23. add_pda(irq_thermal_count, 1);
  24. irq_exit();
  25. }
  26. static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
  27. {
  28. u32 l, h;
  29. int tm2 = 0;
  30. unsigned int cpu = smp_processor_id();
  31. if (!cpu_has(c, X86_FEATURE_ACPI))
  32. return;
  33. if (!cpu_has(c, X86_FEATURE_ACC))
  34. return;
  35. /* first check if TM1 is already enabled by the BIOS, in which
  36. * case there might be some SMM goo which handles it, so we can't even
  37. * put a handler since it might be delivered via SMI already.
  38. */
  39. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  40. h = apic_read(APIC_LVTTHMR);
  41. if ((l & (1 << 3)) && (h & APIC_DM_SMI)) {
  42. printk(KERN_DEBUG
  43. "CPU%d: Thermal monitoring handled by SMI\n", cpu);
  44. return;
  45. }
  46. if (cpu_has(c, X86_FEATURE_TM2) && (l & (1 << 13)))
  47. tm2 = 1;
  48. if (h & APIC_VECTOR_MASK) {
  49. printk(KERN_DEBUG
  50. "CPU%d: Thermal LVT vector (%#x) already "
  51. "installed\n", cpu, (h & APIC_VECTOR_MASK));
  52. return;
  53. }
  54. h = THERMAL_APIC_VECTOR;
  55. h |= (APIC_DM_FIXED | APIC_LVT_MASKED);
  56. apic_write(APIC_LVTTHMR, h);
  57. rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
  58. wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
  59. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  60. wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h);
  61. l = apic_read(APIC_LVTTHMR);
  62. apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
  63. printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",
  64. cpu, tm2 ? "TM2" : "TM1");
  65. /* enable thermal throttle processing */
  66. atomic_set(&therm_throt_en, 1);
  67. return;
  68. }
  69. void __cpuinit mce_intel_feature_init(struct cpuinfo_x86 *c)
  70. {
  71. intel_init_thermal(c);
  72. }