dma-sh7780.h 880 B

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  1. #ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
  2. #define __ASM_SH_CPU_SH4_DMA_SH7780_H
  3. #define REQ_HE 0x000000C0
  4. #define REQ_H 0x00000080
  5. #define REQ_LE 0x00000040
  6. #define TM_BURST 0x0000020
  7. #define TS_8 0x00000000
  8. #define TS_16 0x00000008
  9. #define TS_32 0x00000010
  10. #define TS_16BLK 0x00000018
  11. #define TS_32BLK 0x00100000
  12. /*
  13. * The SuperH DMAC supports a number of transmit sizes, we list them here,
  14. * with their respective values as they appear in the CHCR registers.
  15. *
  16. * Defaults to a 64-bit transfer size.
  17. */
  18. enum {
  19. XMIT_SZ_8BIT,
  20. XMIT_SZ_16BIT,
  21. XMIT_SZ_32BIT,
  22. XMIT_SZ_128BIT,
  23. XMIT_SZ_256BIT,
  24. };
  25. /*
  26. * The DMA count is defined as the number of bytes to transfer.
  27. */
  28. static unsigned int ts_shift[] __maybe_unused = {
  29. [XMIT_SZ_8BIT] = 0,
  30. [XMIT_SZ_16BIT] = 1,
  31. [XMIT_SZ_32BIT] = 2,
  32. [XMIT_SZ_128BIT] = 4,
  33. [XMIT_SZ_256BIT] = 5,
  34. };
  35. #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */