time.c 43 KB

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  1. /*
  2. * arch/s390/kernel/time.c
  3. * Time of day based timer functions.
  4. *
  5. * S390 version
  6. * Copyright IBM Corp. 1999, 2008
  7. * Author(s): Hartmut Penner (hp@de.ibm.com),
  8. * Martin Schwidefsky (schwidefsky@de.ibm.com),
  9. * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
  10. *
  11. * Derived from "arch/i386/kernel/time.c"
  12. * Copyright (C) 1991, 1992, 1995 Linus Torvalds
  13. */
  14. #include <linux/errno.h>
  15. #include <linux/module.h>
  16. #include <linux/sched.h>
  17. #include <linux/kernel.h>
  18. #include <linux/param.h>
  19. #include <linux/string.h>
  20. #include <linux/mm.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/time.h>
  23. #include <linux/sysdev.h>
  24. #include <linux/delay.h>
  25. #include <linux/init.h>
  26. #include <linux/smp.h>
  27. #include <linux/types.h>
  28. #include <linux/profile.h>
  29. #include <linux/timex.h>
  30. #include <linux/notifier.h>
  31. #include <linux/clocksource.h>
  32. #include <linux/clockchips.h>
  33. #include <linux/bootmem.h>
  34. #include <asm/uaccess.h>
  35. #include <asm/delay.h>
  36. #include <asm/s390_ext.h>
  37. #include <asm/div64.h>
  38. #include <asm/irq.h>
  39. #include <asm/irq_regs.h>
  40. #include <asm/timer.h>
  41. #include <asm/etr.h>
  42. #include <asm/cio.h>
  43. /* change this if you have some constant time drift */
  44. #define USECS_PER_JIFFY ((unsigned long) 1000000/HZ)
  45. #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12)
  46. /* The value of the TOD clock for 1.1.1970. */
  47. #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
  48. /*
  49. * Create a small time difference between the timer interrupts
  50. * on the different cpus to avoid lock contention.
  51. */
  52. #define CPU_DEVIATION (smp_processor_id() << 12)
  53. #define TICK_SIZE tick
  54. static ext_int_info_t ext_int_info_cc;
  55. static ext_int_info_t ext_int_etr_cc;
  56. static u64 jiffies_timer_cc;
  57. static DEFINE_PER_CPU(struct clock_event_device, comparators);
  58. /*
  59. * Scheduler clock - returns current time in nanosec units.
  60. */
  61. unsigned long long sched_clock(void)
  62. {
  63. return ((get_clock_xt() - jiffies_timer_cc) * 125) >> 9;
  64. }
  65. /*
  66. * Monotonic_clock - returns # of nanoseconds passed since time_init()
  67. */
  68. unsigned long long monotonic_clock(void)
  69. {
  70. return sched_clock();
  71. }
  72. EXPORT_SYMBOL(monotonic_clock);
  73. void tod_to_timeval(__u64 todval, struct timespec *xtime)
  74. {
  75. unsigned long long sec;
  76. sec = todval >> 12;
  77. do_div(sec, 1000000);
  78. xtime->tv_sec = sec;
  79. todval -= (sec * 1000000) << 12;
  80. xtime->tv_nsec = ((todval * 1000) >> 12);
  81. }
  82. #ifdef CONFIG_PROFILING
  83. #define s390_do_profile() profile_tick(CPU_PROFILING)
  84. #else
  85. #define s390_do_profile() do { ; } while(0)
  86. #endif /* CONFIG_PROFILING */
  87. void clock_comparator_work(void)
  88. {
  89. struct clock_event_device *cd;
  90. S390_lowcore.clock_comparator = -1ULL;
  91. set_clock_comparator(S390_lowcore.clock_comparator);
  92. cd = &__get_cpu_var(comparators);
  93. cd->event_handler(cd);
  94. s390_do_profile();
  95. }
  96. /*
  97. * Fixup the clock comparator.
  98. */
  99. static void fixup_clock_comparator(unsigned long long delta)
  100. {
  101. /* If nobody is waiting there's nothing to fix. */
  102. if (S390_lowcore.clock_comparator == -1ULL)
  103. return;
  104. S390_lowcore.clock_comparator += delta;
  105. set_clock_comparator(S390_lowcore.clock_comparator);
  106. }
  107. static int s390_next_event(unsigned long delta,
  108. struct clock_event_device *evt)
  109. {
  110. S390_lowcore.clock_comparator = get_clock() + delta;
  111. set_clock_comparator(S390_lowcore.clock_comparator);
  112. return 0;
  113. }
  114. static void s390_set_mode(enum clock_event_mode mode,
  115. struct clock_event_device *evt)
  116. {
  117. }
  118. /*
  119. * Set up lowcore and control register of the current cpu to
  120. * enable TOD clock and clock comparator interrupts.
  121. */
  122. void init_cpu_timer(void)
  123. {
  124. struct clock_event_device *cd;
  125. int cpu;
  126. S390_lowcore.clock_comparator = -1ULL;
  127. set_clock_comparator(S390_lowcore.clock_comparator);
  128. cpu = smp_processor_id();
  129. cd = &per_cpu(comparators, cpu);
  130. cd->name = "comparator";
  131. cd->features = CLOCK_EVT_FEAT_ONESHOT;
  132. cd->mult = 16777;
  133. cd->shift = 12;
  134. cd->min_delta_ns = 1;
  135. cd->max_delta_ns = LONG_MAX;
  136. cd->rating = 400;
  137. cd->cpumask = cpumask_of_cpu(cpu);
  138. cd->set_next_event = s390_next_event;
  139. cd->set_mode = s390_set_mode;
  140. clockevents_register_device(cd);
  141. /* Enable clock comparator timer interrupt. */
  142. __ctl_set_bit(0,11);
  143. /* Always allow the timing alert external interrupt. */
  144. __ctl_set_bit(0, 4);
  145. }
  146. static void clock_comparator_interrupt(__u16 code)
  147. {
  148. if (S390_lowcore.clock_comparator == -1ULL)
  149. set_clock_comparator(S390_lowcore.clock_comparator);
  150. }
  151. static void etr_timing_alert(struct etr_irq_parm *);
  152. static void stp_timing_alert(struct stp_irq_parm *);
  153. static void timing_alert_interrupt(__u16 code)
  154. {
  155. if (S390_lowcore.ext_params & 0x00c40000)
  156. etr_timing_alert((struct etr_irq_parm *)
  157. &S390_lowcore.ext_params);
  158. if (S390_lowcore.ext_params & 0x00038000)
  159. stp_timing_alert((struct stp_irq_parm *)
  160. &S390_lowcore.ext_params);
  161. }
  162. static void etr_reset(void);
  163. static void stp_reset(void);
  164. /*
  165. * Get the TOD clock running.
  166. */
  167. static u64 __init reset_tod_clock(void)
  168. {
  169. u64 time;
  170. etr_reset();
  171. stp_reset();
  172. if (store_clock(&time) == 0)
  173. return time;
  174. /* TOD clock not running. Set the clock to Unix Epoch. */
  175. if (set_clock(TOD_UNIX_EPOCH) != 0 || store_clock(&time) != 0)
  176. panic("TOD clock not operational.");
  177. return TOD_UNIX_EPOCH;
  178. }
  179. static cycle_t read_tod_clock(void)
  180. {
  181. return get_clock();
  182. }
  183. static struct clocksource clocksource_tod = {
  184. .name = "tod",
  185. .rating = 400,
  186. .read = read_tod_clock,
  187. .mask = -1ULL,
  188. .mult = 1000,
  189. .shift = 12,
  190. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  191. };
  192. /*
  193. * Initialize the TOD clock and the CPU timer of
  194. * the boot cpu.
  195. */
  196. void __init time_init(void)
  197. {
  198. u64 init_timer_cc;
  199. init_timer_cc = reset_tod_clock();
  200. jiffies_timer_cc = init_timer_cc - jiffies_64 * CLK_TICKS_PER_JIFFY;
  201. /* set xtime */
  202. tod_to_timeval(init_timer_cc - TOD_UNIX_EPOCH, &xtime);
  203. set_normalized_timespec(&wall_to_monotonic,
  204. -xtime.tv_sec, -xtime.tv_nsec);
  205. /* request the clock comparator external interrupt */
  206. if (register_early_external_interrupt(0x1004,
  207. clock_comparator_interrupt,
  208. &ext_int_info_cc) != 0)
  209. panic("Couldn't request external interrupt 0x1004");
  210. if (clocksource_register(&clocksource_tod) != 0)
  211. panic("Could not register TOD clock source");
  212. /* request the timing alert external interrupt */
  213. if (register_early_external_interrupt(0x1406,
  214. timing_alert_interrupt,
  215. &ext_int_etr_cc) != 0)
  216. panic("Couldn't request external interrupt 0x1406");
  217. /* Enable TOD clock interrupts on the boot cpu. */
  218. init_cpu_timer();
  219. #ifdef CONFIG_VIRT_TIMER
  220. vtime_init();
  221. #endif
  222. }
  223. /*
  224. * The time is "clock". old is what we think the time is.
  225. * Adjust the value by a multiple of jiffies and add the delta to ntp.
  226. * "delay" is an approximation how long the synchronization took. If
  227. * the time correction is positive, then "delay" is subtracted from
  228. * the time difference and only the remaining part is passed to ntp.
  229. */
  230. static unsigned long long adjust_time(unsigned long long old,
  231. unsigned long long clock,
  232. unsigned long long delay)
  233. {
  234. unsigned long long delta, ticks;
  235. struct timex adjust;
  236. if (clock > old) {
  237. /* It is later than we thought. */
  238. delta = ticks = clock - old;
  239. delta = ticks = (delta < delay) ? 0 : delta - delay;
  240. delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
  241. adjust.offset = ticks * (1000000 / HZ);
  242. } else {
  243. /* It is earlier than we thought. */
  244. delta = ticks = old - clock;
  245. delta -= do_div(ticks, CLK_TICKS_PER_JIFFY);
  246. delta = -delta;
  247. adjust.offset = -ticks * (1000000 / HZ);
  248. }
  249. jiffies_timer_cc += delta;
  250. if (adjust.offset != 0) {
  251. printk(KERN_NOTICE "etr: time adjusted by %li micro-seconds\n",
  252. adjust.offset);
  253. adjust.modes = ADJ_OFFSET_SINGLESHOT;
  254. do_adjtimex(&adjust);
  255. }
  256. return delta;
  257. }
  258. static DEFINE_PER_CPU(atomic_t, clock_sync_word);
  259. static unsigned long clock_sync_flags;
  260. #define CLOCK_SYNC_HAS_ETR 0
  261. #define CLOCK_SYNC_HAS_STP 1
  262. #define CLOCK_SYNC_ETR 2
  263. #define CLOCK_SYNC_STP 3
  264. /*
  265. * The synchronous get_clock function. It will write the current clock
  266. * value to the clock pointer and return 0 if the clock is in sync with
  267. * the external time source. If the clock mode is local it will return
  268. * -ENOSYS and -EAGAIN if the clock is not in sync with the external
  269. * reference.
  270. */
  271. int get_sync_clock(unsigned long long *clock)
  272. {
  273. atomic_t *sw_ptr;
  274. unsigned int sw0, sw1;
  275. sw_ptr = &get_cpu_var(clock_sync_word);
  276. sw0 = atomic_read(sw_ptr);
  277. *clock = get_clock();
  278. sw1 = atomic_read(sw_ptr);
  279. put_cpu_var(clock_sync_sync);
  280. if (sw0 == sw1 && (sw0 & 0x80000000U))
  281. /* Success: time is in sync. */
  282. return 0;
  283. if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) &&
  284. !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
  285. return -ENOSYS;
  286. if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) &&
  287. !test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
  288. return -EACCES;
  289. return -EAGAIN;
  290. }
  291. EXPORT_SYMBOL(get_sync_clock);
  292. /*
  293. * Make get_sync_clock return -EAGAIN.
  294. */
  295. static void disable_sync_clock(void *dummy)
  296. {
  297. atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
  298. /*
  299. * Clear the in-sync bit 2^31. All get_sync_clock calls will
  300. * fail until the sync bit is turned back on. In addition
  301. * increase the "sequence" counter to avoid the race of an
  302. * etr event and the complete recovery against get_sync_clock.
  303. */
  304. atomic_clear_mask(0x80000000, sw_ptr);
  305. atomic_inc(sw_ptr);
  306. }
  307. /*
  308. * Make get_sync_clock return 0 again.
  309. * Needs to be called from a context disabled for preemption.
  310. */
  311. static void enable_sync_clock(void)
  312. {
  313. atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word);
  314. atomic_set_mask(0x80000000, sw_ptr);
  315. }
  316. /*
  317. * External Time Reference (ETR) code.
  318. */
  319. static int etr_port0_online;
  320. static int etr_port1_online;
  321. static int etr_steai_available;
  322. static int __init early_parse_etr(char *p)
  323. {
  324. if (strncmp(p, "off", 3) == 0)
  325. etr_port0_online = etr_port1_online = 0;
  326. else if (strncmp(p, "port0", 5) == 0)
  327. etr_port0_online = 1;
  328. else if (strncmp(p, "port1", 5) == 0)
  329. etr_port1_online = 1;
  330. else if (strncmp(p, "on", 2) == 0)
  331. etr_port0_online = etr_port1_online = 1;
  332. return 0;
  333. }
  334. early_param("etr", early_parse_etr);
  335. enum etr_event {
  336. ETR_EVENT_PORT0_CHANGE,
  337. ETR_EVENT_PORT1_CHANGE,
  338. ETR_EVENT_PORT_ALERT,
  339. ETR_EVENT_SYNC_CHECK,
  340. ETR_EVENT_SWITCH_LOCAL,
  341. ETR_EVENT_UPDATE,
  342. };
  343. /*
  344. * Valid bit combinations of the eacr register are (x = don't care):
  345. * e0 e1 dp p0 p1 ea es sl
  346. * 0 0 x 0 0 0 0 0 initial, disabled state
  347. * 0 0 x 0 1 1 0 0 port 1 online
  348. * 0 0 x 1 0 1 0 0 port 0 online
  349. * 0 0 x 1 1 1 0 0 both ports online
  350. * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode
  351. * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode
  352. * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync
  353. * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync
  354. * 0 1 x 1 1 1 0 0 both ports online, port 1 usable
  355. * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync
  356. * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync
  357. * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode
  358. * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode
  359. * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync
  360. * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync
  361. * 1 0 x 1 1 1 0 0 both ports online, port 0 usable
  362. * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync
  363. * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync
  364. * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync
  365. * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync
  366. */
  367. static struct etr_eacr etr_eacr;
  368. static u64 etr_tolec; /* time of last eacr update */
  369. static struct etr_aib etr_port0;
  370. static int etr_port0_uptodate;
  371. static struct etr_aib etr_port1;
  372. static int etr_port1_uptodate;
  373. static unsigned long etr_events;
  374. static struct timer_list etr_timer;
  375. static void etr_timeout(unsigned long dummy);
  376. static void etr_work_fn(struct work_struct *work);
  377. static DECLARE_WORK(etr_work, etr_work_fn);
  378. /*
  379. * Reset ETR attachment.
  380. */
  381. static void etr_reset(void)
  382. {
  383. etr_eacr = (struct etr_eacr) {
  384. .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0,
  385. .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0,
  386. .es = 0, .sl = 0 };
  387. if (etr_setr(&etr_eacr) == 0) {
  388. etr_tolec = get_clock();
  389. set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags);
  390. } else if (etr_port0_online || etr_port1_online) {
  391. printk(KERN_WARNING "Running on non ETR capable "
  392. "machine, only local mode available.\n");
  393. etr_port0_online = etr_port1_online = 0;
  394. }
  395. }
  396. static int __init etr_init(void)
  397. {
  398. struct etr_aib aib;
  399. if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
  400. return 0;
  401. /* Check if this machine has the steai instruction. */
  402. if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0)
  403. etr_steai_available = 1;
  404. setup_timer(&etr_timer, etr_timeout, 0UL);
  405. if (etr_port0_online) {
  406. set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
  407. schedule_work(&etr_work);
  408. }
  409. if (etr_port1_online) {
  410. set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
  411. schedule_work(&etr_work);
  412. }
  413. return 0;
  414. }
  415. arch_initcall(etr_init);
  416. /*
  417. * Two sorts of ETR machine checks. The architecture reads:
  418. * "When a machine-check niterruption occurs and if a switch-to-local or
  419. * ETR-sync-check interrupt request is pending but disabled, this pending
  420. * disabled interruption request is indicated and is cleared".
  421. * Which means that we can get etr_switch_to_local events from the machine
  422. * check handler although the interruption condition is disabled. Lovely..
  423. */
  424. /*
  425. * Switch to local machine check. This is called when the last usable
  426. * ETR port goes inactive. After switch to local the clock is not in sync.
  427. */
  428. void etr_switch_to_local(void)
  429. {
  430. if (!etr_eacr.sl)
  431. return;
  432. if (test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
  433. disable_sync_clock(NULL);
  434. set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events);
  435. schedule_work(&etr_work);
  436. }
  437. /*
  438. * ETR sync check machine check. This is called when the ETR OTE and the
  439. * local clock OTE are farther apart than the ETR sync check tolerance.
  440. * After a ETR sync check the clock is not in sync. The machine check
  441. * is broadcasted to all cpus at the same time.
  442. */
  443. void etr_sync_check(void)
  444. {
  445. if (!etr_eacr.es)
  446. return;
  447. if (test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
  448. disable_sync_clock(NULL);
  449. set_bit(ETR_EVENT_SYNC_CHECK, &etr_events);
  450. schedule_work(&etr_work);
  451. }
  452. /*
  453. * ETR timing alert. There are two causes:
  454. * 1) port state change, check the usability of the port
  455. * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the
  456. * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3)
  457. * or ETR-data word 4 (edf4) has changed.
  458. */
  459. static void etr_timing_alert(struct etr_irq_parm *intparm)
  460. {
  461. if (intparm->pc0)
  462. /* ETR port 0 state change. */
  463. set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
  464. if (intparm->pc1)
  465. /* ETR port 1 state change. */
  466. set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
  467. if (intparm->eai)
  468. /*
  469. * ETR port alert on either port 0, 1 or both.
  470. * Both ports are not up-to-date now.
  471. */
  472. set_bit(ETR_EVENT_PORT_ALERT, &etr_events);
  473. schedule_work(&etr_work);
  474. }
  475. static void etr_timeout(unsigned long dummy)
  476. {
  477. set_bit(ETR_EVENT_UPDATE, &etr_events);
  478. schedule_work(&etr_work);
  479. }
  480. /*
  481. * Check if the etr mode is pss.
  482. */
  483. static inline int etr_mode_is_pps(struct etr_eacr eacr)
  484. {
  485. return eacr.es && !eacr.sl;
  486. }
  487. /*
  488. * Check if the etr mode is etr.
  489. */
  490. static inline int etr_mode_is_etr(struct etr_eacr eacr)
  491. {
  492. return eacr.es && eacr.sl;
  493. }
  494. /*
  495. * Check if the port can be used for TOD synchronization.
  496. * For PPS mode the port has to receive OTEs. For ETR mode
  497. * the port has to receive OTEs, the ETR stepping bit has to
  498. * be zero and the validity bits for data frame 1, 2, and 3
  499. * have to be 1.
  500. */
  501. static int etr_port_valid(struct etr_aib *aib, int port)
  502. {
  503. unsigned int psc;
  504. /* Check that this port is receiving OTEs. */
  505. if (aib->tsp == 0)
  506. return 0;
  507. psc = port ? aib->esw.psc1 : aib->esw.psc0;
  508. if (psc == etr_lpsc_pps_mode)
  509. return 1;
  510. if (psc == etr_lpsc_operational_step)
  511. return !aib->esw.y && aib->slsw.v1 &&
  512. aib->slsw.v2 && aib->slsw.v3;
  513. return 0;
  514. }
  515. /*
  516. * Check if two ports are on the same network.
  517. */
  518. static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2)
  519. {
  520. // FIXME: any other fields we have to compare?
  521. return aib1->edf1.net_id == aib2->edf1.net_id;
  522. }
  523. /*
  524. * Wrapper for etr_stei that converts physical port states
  525. * to logical port states to be consistent with the output
  526. * of stetr (see etr_psc vs. etr_lpsc).
  527. */
  528. static void etr_steai_cv(struct etr_aib *aib, unsigned int func)
  529. {
  530. BUG_ON(etr_steai(aib, func) != 0);
  531. /* Convert port state to logical port state. */
  532. if (aib->esw.psc0 == 1)
  533. aib->esw.psc0 = 2;
  534. else if (aib->esw.psc0 == 0 && aib->esw.p == 0)
  535. aib->esw.psc0 = 1;
  536. if (aib->esw.psc1 == 1)
  537. aib->esw.psc1 = 2;
  538. else if (aib->esw.psc1 == 0 && aib->esw.p == 1)
  539. aib->esw.psc1 = 1;
  540. }
  541. /*
  542. * Check if the aib a2 is still connected to the same attachment as
  543. * aib a1, the etv values differ by one and a2 is valid.
  544. */
  545. static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p)
  546. {
  547. int state_a1, state_a2;
  548. /* Paranoia check: e0/e1 should better be the same. */
  549. if (a1->esw.eacr.e0 != a2->esw.eacr.e0 ||
  550. a1->esw.eacr.e1 != a2->esw.eacr.e1)
  551. return 0;
  552. /* Still connected to the same etr ? */
  553. state_a1 = p ? a1->esw.psc1 : a1->esw.psc0;
  554. state_a2 = p ? a2->esw.psc1 : a2->esw.psc0;
  555. if (state_a1 == etr_lpsc_operational_step) {
  556. if (state_a2 != etr_lpsc_operational_step ||
  557. a1->edf1.net_id != a2->edf1.net_id ||
  558. a1->edf1.etr_id != a2->edf1.etr_id ||
  559. a1->edf1.etr_pn != a2->edf1.etr_pn)
  560. return 0;
  561. } else if (state_a2 != etr_lpsc_pps_mode)
  562. return 0;
  563. /* The ETV value of a2 needs to be ETV of a1 + 1. */
  564. if (a1->edf2.etv + 1 != a2->edf2.etv)
  565. return 0;
  566. if (!etr_port_valid(a2, p))
  567. return 0;
  568. return 1;
  569. }
  570. struct clock_sync_data {
  571. int in_sync;
  572. unsigned long long fixup_cc;
  573. };
  574. static void clock_sync_cpu_start(void *dummy)
  575. {
  576. struct clock_sync_data *sync = dummy;
  577. enable_sync_clock();
  578. /*
  579. * This looks like a busy wait loop but it isn't. etr_sync_cpus
  580. * is called on all other cpus while the TOD clocks is stopped.
  581. * __udelay will stop the cpu on an enabled wait psw until the
  582. * TOD is running again.
  583. */
  584. while (sync->in_sync == 0) {
  585. __udelay(1);
  586. /*
  587. * A different cpu changes *in_sync. Therefore use
  588. * barrier() to force memory access.
  589. */
  590. barrier();
  591. }
  592. if (sync->in_sync != 1)
  593. /* Didn't work. Clear per-cpu in sync bit again. */
  594. disable_sync_clock(NULL);
  595. /*
  596. * This round of TOD syncing is done. Set the clock comparator
  597. * to the next tick and let the processor continue.
  598. */
  599. fixup_clock_comparator(sync->fixup_cc);
  600. }
  601. static void clock_sync_cpu_end(void *dummy)
  602. {
  603. }
  604. /*
  605. * Sync the TOD clock using the port refered to by aibp. This port
  606. * has to be enabled and the other port has to be disabled. The
  607. * last eacr update has to be more than 1.6 seconds in the past.
  608. */
  609. static int etr_sync_clock(struct etr_aib *aib, int port)
  610. {
  611. struct etr_aib *sync_port;
  612. struct clock_sync_data etr_sync;
  613. unsigned long long clock, old_clock, delay, delta;
  614. int follows;
  615. int rc;
  616. /* Check if the current aib is adjacent to the sync port aib. */
  617. sync_port = (port == 0) ? &etr_port0 : &etr_port1;
  618. follows = etr_aib_follows(sync_port, aib, port);
  619. memcpy(sync_port, aib, sizeof(*aib));
  620. if (!follows)
  621. return -EAGAIN;
  622. /*
  623. * Catch all other cpus and make them wait until we have
  624. * successfully synced the clock. smp_call_function will
  625. * return after all other cpus are in etr_sync_cpu_start.
  626. */
  627. memset(&etr_sync, 0, sizeof(etr_sync));
  628. preempt_disable();
  629. smp_call_function(clock_sync_cpu_start, &etr_sync, 0);
  630. local_irq_disable();
  631. enable_sync_clock();
  632. /* Set clock to next OTE. */
  633. __ctl_set_bit(14, 21);
  634. __ctl_set_bit(0, 29);
  635. clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32;
  636. old_clock = get_clock();
  637. if (set_clock(clock) == 0) {
  638. __udelay(1); /* Wait for the clock to start. */
  639. __ctl_clear_bit(0, 29);
  640. __ctl_clear_bit(14, 21);
  641. etr_stetr(aib);
  642. /* Adjust Linux timing variables. */
  643. delay = (unsigned long long)
  644. (aib->edf2.etv - sync_port->edf2.etv) << 32;
  645. delta = adjust_time(old_clock, clock, delay);
  646. etr_sync.fixup_cc = delta;
  647. fixup_clock_comparator(delta);
  648. /* Verify that the clock is properly set. */
  649. if (!etr_aib_follows(sync_port, aib, port)) {
  650. /* Didn't work. */
  651. disable_sync_clock(NULL);
  652. etr_sync.in_sync = -EAGAIN;
  653. rc = -EAGAIN;
  654. } else {
  655. etr_sync.in_sync = 1;
  656. rc = 0;
  657. }
  658. } else {
  659. /* Could not set the clock ?!? */
  660. __ctl_clear_bit(0, 29);
  661. __ctl_clear_bit(14, 21);
  662. disable_sync_clock(NULL);
  663. etr_sync.in_sync = -EAGAIN;
  664. rc = -EAGAIN;
  665. }
  666. local_irq_enable();
  667. smp_call_function(clock_sync_cpu_end, NULL, 0);
  668. preempt_enable();
  669. return rc;
  670. }
  671. /*
  672. * Handle the immediate effects of the different events.
  673. * The port change event is used for online/offline changes.
  674. */
  675. static struct etr_eacr etr_handle_events(struct etr_eacr eacr)
  676. {
  677. if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events))
  678. eacr.es = 0;
  679. if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events))
  680. eacr.es = eacr.sl = 0;
  681. if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events))
  682. etr_port0_uptodate = etr_port1_uptodate = 0;
  683. if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) {
  684. if (eacr.e0)
  685. /*
  686. * Port change of an enabled port. We have to
  687. * assume that this can have caused an stepping
  688. * port switch.
  689. */
  690. etr_tolec = get_clock();
  691. eacr.p0 = etr_port0_online;
  692. if (!eacr.p0)
  693. eacr.e0 = 0;
  694. etr_port0_uptodate = 0;
  695. }
  696. if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) {
  697. if (eacr.e1)
  698. /*
  699. * Port change of an enabled port. We have to
  700. * assume that this can have caused an stepping
  701. * port switch.
  702. */
  703. etr_tolec = get_clock();
  704. eacr.p1 = etr_port1_online;
  705. if (!eacr.p1)
  706. eacr.e1 = 0;
  707. etr_port1_uptodate = 0;
  708. }
  709. clear_bit(ETR_EVENT_UPDATE, &etr_events);
  710. return eacr;
  711. }
  712. /*
  713. * Set up a timer that expires after the etr_tolec + 1.6 seconds if
  714. * one of the ports needs an update.
  715. */
  716. static void etr_set_tolec_timeout(unsigned long long now)
  717. {
  718. unsigned long micros;
  719. if ((!etr_eacr.p0 || etr_port0_uptodate) &&
  720. (!etr_eacr.p1 || etr_port1_uptodate))
  721. return;
  722. micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0;
  723. micros = (micros > 1600000) ? 0 : 1600000 - micros;
  724. mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1);
  725. }
  726. /*
  727. * Set up a time that expires after 1/2 second.
  728. */
  729. static void etr_set_sync_timeout(void)
  730. {
  731. mod_timer(&etr_timer, jiffies + HZ/2);
  732. }
  733. /*
  734. * Update the aib information for one or both ports.
  735. */
  736. static struct etr_eacr etr_handle_update(struct etr_aib *aib,
  737. struct etr_eacr eacr)
  738. {
  739. /* With both ports disabled the aib information is useless. */
  740. if (!eacr.e0 && !eacr.e1)
  741. return eacr;
  742. /* Update port0 or port1 with aib stored in etr_work_fn. */
  743. if (aib->esw.q == 0) {
  744. /* Information for port 0 stored. */
  745. if (eacr.p0 && !etr_port0_uptodate) {
  746. etr_port0 = *aib;
  747. if (etr_port0_online)
  748. etr_port0_uptodate = 1;
  749. }
  750. } else {
  751. /* Information for port 1 stored. */
  752. if (eacr.p1 && !etr_port1_uptodate) {
  753. etr_port1 = *aib;
  754. if (etr_port0_online)
  755. etr_port1_uptodate = 1;
  756. }
  757. }
  758. /*
  759. * Do not try to get the alternate port aib if the clock
  760. * is not in sync yet.
  761. */
  762. if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags) && !eacr.es)
  763. return eacr;
  764. /*
  765. * If steai is available we can get the information about
  766. * the other port immediately. If only stetr is available the
  767. * data-port bit toggle has to be used.
  768. */
  769. if (etr_steai_available) {
  770. if (eacr.p0 && !etr_port0_uptodate) {
  771. etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0);
  772. etr_port0_uptodate = 1;
  773. }
  774. if (eacr.p1 && !etr_port1_uptodate) {
  775. etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1);
  776. etr_port1_uptodate = 1;
  777. }
  778. } else {
  779. /*
  780. * One port was updated above, if the other
  781. * port is not uptodate toggle dp bit.
  782. */
  783. if ((eacr.p0 && !etr_port0_uptodate) ||
  784. (eacr.p1 && !etr_port1_uptodate))
  785. eacr.dp ^= 1;
  786. else
  787. eacr.dp = 0;
  788. }
  789. return eacr;
  790. }
  791. /*
  792. * Write new etr control register if it differs from the current one.
  793. * Return 1 if etr_tolec has been updated as well.
  794. */
  795. static void etr_update_eacr(struct etr_eacr eacr)
  796. {
  797. int dp_changed;
  798. if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0)
  799. /* No change, return. */
  800. return;
  801. /*
  802. * The disable of an active port of the change of the data port
  803. * bit can/will cause a change in the data port.
  804. */
  805. dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 ||
  806. (etr_eacr.dp ^ eacr.dp) != 0;
  807. etr_eacr = eacr;
  808. etr_setr(&etr_eacr);
  809. if (dp_changed)
  810. etr_tolec = get_clock();
  811. }
  812. /*
  813. * ETR tasklet. In this function you'll find the main logic. In
  814. * particular this is the only function that calls etr_update_eacr(),
  815. * it "controls" the etr control register.
  816. */
  817. static void etr_work_fn(struct work_struct *work)
  818. {
  819. unsigned long long now;
  820. struct etr_eacr eacr;
  821. struct etr_aib aib;
  822. int sync_port;
  823. /* Create working copy of etr_eacr. */
  824. eacr = etr_eacr;
  825. /* Check for the different events and their immediate effects. */
  826. eacr = etr_handle_events(eacr);
  827. /* Check if ETR is supposed to be active. */
  828. eacr.ea = eacr.p0 || eacr.p1;
  829. if (!eacr.ea) {
  830. /* Both ports offline. Reset everything. */
  831. eacr.dp = eacr.es = eacr.sl = 0;
  832. on_each_cpu(disable_sync_clock, NULL, 1);
  833. del_timer_sync(&etr_timer);
  834. etr_update_eacr(eacr);
  835. clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
  836. return;
  837. }
  838. /* Store aib to get the current ETR status word. */
  839. BUG_ON(etr_stetr(&aib) != 0);
  840. etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */
  841. now = get_clock();
  842. /*
  843. * Update the port information if the last stepping port change
  844. * or data port change is older than 1.6 seconds.
  845. */
  846. if (now >= etr_tolec + (1600000 << 12))
  847. eacr = etr_handle_update(&aib, eacr);
  848. /*
  849. * Select ports to enable. The prefered synchronization mode is PPS.
  850. * If a port can be enabled depends on a number of things:
  851. * 1) The port needs to be online and uptodate. A port is not
  852. * disabled just because it is not uptodate, but it is only
  853. * enabled if it is uptodate.
  854. * 2) The port needs to have the same mode (pps / etr).
  855. * 3) The port needs to be usable -> etr_port_valid() == 1
  856. * 4) To enable the second port the clock needs to be in sync.
  857. * 5) If both ports are useable and are ETR ports, the network id
  858. * has to be the same.
  859. * The eacr.sl bit is used to indicate etr mode vs. pps mode.
  860. */
  861. if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) {
  862. eacr.sl = 0;
  863. eacr.e0 = 1;
  864. if (!etr_mode_is_pps(etr_eacr))
  865. eacr.es = 0;
  866. if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode)
  867. eacr.e1 = 0;
  868. // FIXME: uptodate checks ?
  869. else if (etr_port0_uptodate && etr_port1_uptodate)
  870. eacr.e1 = 1;
  871. sync_port = (etr_port0_uptodate &&
  872. etr_port_valid(&etr_port0, 0)) ? 0 : -1;
  873. } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) {
  874. eacr.sl = 0;
  875. eacr.e0 = 0;
  876. eacr.e1 = 1;
  877. if (!etr_mode_is_pps(etr_eacr))
  878. eacr.es = 0;
  879. sync_port = (etr_port1_uptodate &&
  880. etr_port_valid(&etr_port1, 1)) ? 1 : -1;
  881. } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) {
  882. eacr.sl = 1;
  883. eacr.e0 = 1;
  884. if (!etr_mode_is_etr(etr_eacr))
  885. eacr.es = 0;
  886. if (!eacr.es || !eacr.p1 ||
  887. aib.esw.psc1 != etr_lpsc_operational_alt)
  888. eacr.e1 = 0;
  889. else if (etr_port0_uptodate && etr_port1_uptodate &&
  890. etr_compare_network(&etr_port0, &etr_port1))
  891. eacr.e1 = 1;
  892. sync_port = (etr_port0_uptodate &&
  893. etr_port_valid(&etr_port0, 0)) ? 0 : -1;
  894. } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) {
  895. eacr.sl = 1;
  896. eacr.e0 = 0;
  897. eacr.e1 = 1;
  898. if (!etr_mode_is_etr(etr_eacr))
  899. eacr.es = 0;
  900. sync_port = (etr_port1_uptodate &&
  901. etr_port_valid(&etr_port1, 1)) ? 1 : -1;
  902. } else {
  903. /* Both ports not usable. */
  904. eacr.es = eacr.sl = 0;
  905. sync_port = -1;
  906. clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
  907. }
  908. if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
  909. eacr.es = 0;
  910. /*
  911. * If the clock is in sync just update the eacr and return.
  912. * If there is no valid sync port wait for a port update.
  913. */
  914. if (test_bit(CLOCK_SYNC_STP, &clock_sync_flags) ||
  915. eacr.es || sync_port < 0) {
  916. etr_update_eacr(eacr);
  917. etr_set_tolec_timeout(now);
  918. return;
  919. }
  920. /*
  921. * Prepare control register for clock syncing
  922. * (reset data port bit, set sync check control.
  923. */
  924. eacr.dp = 0;
  925. eacr.es = 1;
  926. /*
  927. * Update eacr and try to synchronize the clock. If the update
  928. * of eacr caused a stepping port switch (or if we have to
  929. * assume that a stepping port switch has occured) or the
  930. * clock syncing failed, reset the sync check control bit
  931. * and set up a timer to try again after 0.5 seconds
  932. */
  933. etr_update_eacr(eacr);
  934. set_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
  935. if (now < etr_tolec + (1600000 << 12) ||
  936. etr_sync_clock(&aib, sync_port) != 0) {
  937. /* Sync failed. Try again in 1/2 second. */
  938. eacr.es = 0;
  939. etr_update_eacr(eacr);
  940. clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags);
  941. etr_set_sync_timeout();
  942. } else
  943. etr_set_tolec_timeout(now);
  944. }
  945. /*
  946. * Sysfs interface functions
  947. */
  948. static struct sysdev_class etr_sysclass = {
  949. .name = "etr",
  950. };
  951. static struct sys_device etr_port0_dev = {
  952. .id = 0,
  953. .cls = &etr_sysclass,
  954. };
  955. static struct sys_device etr_port1_dev = {
  956. .id = 1,
  957. .cls = &etr_sysclass,
  958. };
  959. /*
  960. * ETR class attributes
  961. */
  962. static ssize_t etr_stepping_port_show(struct sysdev_class *class, char *buf)
  963. {
  964. return sprintf(buf, "%i\n", etr_port0.esw.p);
  965. }
  966. static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL);
  967. static ssize_t etr_stepping_mode_show(struct sysdev_class *class, char *buf)
  968. {
  969. char *mode_str;
  970. if (etr_mode_is_pps(etr_eacr))
  971. mode_str = "pps";
  972. else if (etr_mode_is_etr(etr_eacr))
  973. mode_str = "etr";
  974. else
  975. mode_str = "local";
  976. return sprintf(buf, "%s\n", mode_str);
  977. }
  978. static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL);
  979. /*
  980. * ETR port attributes
  981. */
  982. static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev)
  983. {
  984. if (dev == &etr_port0_dev)
  985. return etr_port0_online ? &etr_port0 : NULL;
  986. else
  987. return etr_port1_online ? &etr_port1 : NULL;
  988. }
  989. static ssize_t etr_online_show(struct sys_device *dev,
  990. struct sysdev_attribute *attr,
  991. char *buf)
  992. {
  993. unsigned int online;
  994. online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online;
  995. return sprintf(buf, "%i\n", online);
  996. }
  997. static ssize_t etr_online_store(struct sys_device *dev,
  998. struct sysdev_attribute *attr,
  999. const char *buf, size_t count)
  1000. {
  1001. unsigned int value;
  1002. value = simple_strtoul(buf, NULL, 0);
  1003. if (value != 0 && value != 1)
  1004. return -EINVAL;
  1005. if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags))
  1006. return -EOPNOTSUPP;
  1007. if (dev == &etr_port0_dev) {
  1008. if (etr_port0_online == value)
  1009. return count; /* Nothing to do. */
  1010. etr_port0_online = value;
  1011. set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events);
  1012. schedule_work(&etr_work);
  1013. } else {
  1014. if (etr_port1_online == value)
  1015. return count; /* Nothing to do. */
  1016. etr_port1_online = value;
  1017. set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events);
  1018. schedule_work(&etr_work);
  1019. }
  1020. return count;
  1021. }
  1022. static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store);
  1023. static ssize_t etr_stepping_control_show(struct sys_device *dev,
  1024. struct sysdev_attribute *attr,
  1025. char *buf)
  1026. {
  1027. return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
  1028. etr_eacr.e0 : etr_eacr.e1);
  1029. }
  1030. static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL);
  1031. static ssize_t etr_mode_code_show(struct sys_device *dev,
  1032. struct sysdev_attribute *attr, char *buf)
  1033. {
  1034. if (!etr_port0_online && !etr_port1_online)
  1035. /* Status word is not uptodate if both ports are offline. */
  1036. return -ENODATA;
  1037. return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ?
  1038. etr_port0.esw.psc0 : etr_port0.esw.psc1);
  1039. }
  1040. static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL);
  1041. static ssize_t etr_untuned_show(struct sys_device *dev,
  1042. struct sysdev_attribute *attr, char *buf)
  1043. {
  1044. struct etr_aib *aib = etr_aib_from_dev(dev);
  1045. if (!aib || !aib->slsw.v1)
  1046. return -ENODATA;
  1047. return sprintf(buf, "%i\n", aib->edf1.u);
  1048. }
  1049. static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL);
  1050. static ssize_t etr_network_id_show(struct sys_device *dev,
  1051. struct sysdev_attribute *attr, char *buf)
  1052. {
  1053. struct etr_aib *aib = etr_aib_from_dev(dev);
  1054. if (!aib || !aib->slsw.v1)
  1055. return -ENODATA;
  1056. return sprintf(buf, "%i\n", aib->edf1.net_id);
  1057. }
  1058. static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL);
  1059. static ssize_t etr_id_show(struct sys_device *dev,
  1060. struct sysdev_attribute *attr, char *buf)
  1061. {
  1062. struct etr_aib *aib = etr_aib_from_dev(dev);
  1063. if (!aib || !aib->slsw.v1)
  1064. return -ENODATA;
  1065. return sprintf(buf, "%i\n", aib->edf1.etr_id);
  1066. }
  1067. static SYSDEV_ATTR(id, 0400, etr_id_show, NULL);
  1068. static ssize_t etr_port_number_show(struct sys_device *dev,
  1069. struct sysdev_attribute *attr, char *buf)
  1070. {
  1071. struct etr_aib *aib = etr_aib_from_dev(dev);
  1072. if (!aib || !aib->slsw.v1)
  1073. return -ENODATA;
  1074. return sprintf(buf, "%i\n", aib->edf1.etr_pn);
  1075. }
  1076. static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL);
  1077. static ssize_t etr_coupled_show(struct sys_device *dev,
  1078. struct sysdev_attribute *attr, char *buf)
  1079. {
  1080. struct etr_aib *aib = etr_aib_from_dev(dev);
  1081. if (!aib || !aib->slsw.v3)
  1082. return -ENODATA;
  1083. return sprintf(buf, "%i\n", aib->edf3.c);
  1084. }
  1085. static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL);
  1086. static ssize_t etr_local_time_show(struct sys_device *dev,
  1087. struct sysdev_attribute *attr, char *buf)
  1088. {
  1089. struct etr_aib *aib = etr_aib_from_dev(dev);
  1090. if (!aib || !aib->slsw.v3)
  1091. return -ENODATA;
  1092. return sprintf(buf, "%i\n", aib->edf3.blto);
  1093. }
  1094. static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL);
  1095. static ssize_t etr_utc_offset_show(struct sys_device *dev,
  1096. struct sysdev_attribute *attr, char *buf)
  1097. {
  1098. struct etr_aib *aib = etr_aib_from_dev(dev);
  1099. if (!aib || !aib->slsw.v3)
  1100. return -ENODATA;
  1101. return sprintf(buf, "%i\n", aib->edf3.buo);
  1102. }
  1103. static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL);
  1104. static struct sysdev_attribute *etr_port_attributes[] = {
  1105. &attr_online,
  1106. &attr_stepping_control,
  1107. &attr_state_code,
  1108. &attr_untuned,
  1109. &attr_network,
  1110. &attr_id,
  1111. &attr_port,
  1112. &attr_coupled,
  1113. &attr_local_time,
  1114. &attr_utc_offset,
  1115. NULL
  1116. };
  1117. static int __init etr_register_port(struct sys_device *dev)
  1118. {
  1119. struct sysdev_attribute **attr;
  1120. int rc;
  1121. rc = sysdev_register(dev);
  1122. if (rc)
  1123. goto out;
  1124. for (attr = etr_port_attributes; *attr; attr++) {
  1125. rc = sysdev_create_file(dev, *attr);
  1126. if (rc)
  1127. goto out_unreg;
  1128. }
  1129. return 0;
  1130. out_unreg:
  1131. for (; attr >= etr_port_attributes; attr--)
  1132. sysdev_remove_file(dev, *attr);
  1133. sysdev_unregister(dev);
  1134. out:
  1135. return rc;
  1136. }
  1137. static void __init etr_unregister_port(struct sys_device *dev)
  1138. {
  1139. struct sysdev_attribute **attr;
  1140. for (attr = etr_port_attributes; *attr; attr++)
  1141. sysdev_remove_file(dev, *attr);
  1142. sysdev_unregister(dev);
  1143. }
  1144. static int __init etr_init_sysfs(void)
  1145. {
  1146. int rc;
  1147. rc = sysdev_class_register(&etr_sysclass);
  1148. if (rc)
  1149. goto out;
  1150. rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port);
  1151. if (rc)
  1152. goto out_unreg_class;
  1153. rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode);
  1154. if (rc)
  1155. goto out_remove_stepping_port;
  1156. rc = etr_register_port(&etr_port0_dev);
  1157. if (rc)
  1158. goto out_remove_stepping_mode;
  1159. rc = etr_register_port(&etr_port1_dev);
  1160. if (rc)
  1161. goto out_remove_port0;
  1162. return 0;
  1163. out_remove_port0:
  1164. etr_unregister_port(&etr_port0_dev);
  1165. out_remove_stepping_mode:
  1166. sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode);
  1167. out_remove_stepping_port:
  1168. sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port);
  1169. out_unreg_class:
  1170. sysdev_class_unregister(&etr_sysclass);
  1171. out:
  1172. return rc;
  1173. }
  1174. device_initcall(etr_init_sysfs);
  1175. /*
  1176. * Server Time Protocol (STP) code.
  1177. */
  1178. static int stp_online;
  1179. static struct stp_sstpi stp_info;
  1180. static void *stp_page;
  1181. static void stp_work_fn(struct work_struct *work);
  1182. static DECLARE_WORK(stp_work, stp_work_fn);
  1183. static int __init early_parse_stp(char *p)
  1184. {
  1185. if (strncmp(p, "off", 3) == 0)
  1186. stp_online = 0;
  1187. else if (strncmp(p, "on", 2) == 0)
  1188. stp_online = 1;
  1189. return 0;
  1190. }
  1191. early_param("stp", early_parse_stp);
  1192. /*
  1193. * Reset STP attachment.
  1194. */
  1195. static void __init stp_reset(void)
  1196. {
  1197. int rc;
  1198. stp_page = alloc_bootmem_pages(PAGE_SIZE);
  1199. rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
  1200. if (rc == 0)
  1201. set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags);
  1202. else if (stp_online) {
  1203. printk(KERN_WARNING "Running on non STP capable machine.\n");
  1204. free_bootmem((unsigned long) stp_page, PAGE_SIZE);
  1205. stp_page = NULL;
  1206. stp_online = 0;
  1207. }
  1208. }
  1209. static int __init stp_init(void)
  1210. {
  1211. if (test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags) && stp_online)
  1212. schedule_work(&stp_work);
  1213. return 0;
  1214. }
  1215. arch_initcall(stp_init);
  1216. /*
  1217. * STP timing alert. There are three causes:
  1218. * 1) timing status change
  1219. * 2) link availability change
  1220. * 3) time control parameter change
  1221. * In all three cases we are only interested in the clock source state.
  1222. * If a STP clock source is now available use it.
  1223. */
  1224. static void stp_timing_alert(struct stp_irq_parm *intparm)
  1225. {
  1226. if (intparm->tsc || intparm->lac || intparm->tcpc)
  1227. schedule_work(&stp_work);
  1228. }
  1229. /*
  1230. * STP sync check machine check. This is called when the timing state
  1231. * changes from the synchronized state to the unsynchronized state.
  1232. * After a STP sync check the clock is not in sync. The machine check
  1233. * is broadcasted to all cpus at the same time.
  1234. */
  1235. void stp_sync_check(void)
  1236. {
  1237. if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
  1238. return;
  1239. disable_sync_clock(NULL);
  1240. schedule_work(&stp_work);
  1241. }
  1242. /*
  1243. * STP island condition machine check. This is called when an attached
  1244. * server attempts to communicate over an STP link and the servers
  1245. * have matching CTN ids and have a valid stratum-1 configuration
  1246. * but the configurations do not match.
  1247. */
  1248. void stp_island_check(void)
  1249. {
  1250. if (!test_bit(CLOCK_SYNC_STP, &clock_sync_flags))
  1251. return;
  1252. disable_sync_clock(NULL);
  1253. schedule_work(&stp_work);
  1254. }
  1255. /*
  1256. * STP tasklet. Check for the STP state and take over the clock
  1257. * synchronization if the STP clock source is usable.
  1258. */
  1259. static void stp_work_fn(struct work_struct *work)
  1260. {
  1261. struct clock_sync_data stp_sync;
  1262. unsigned long long old_clock, delta;
  1263. int rc;
  1264. if (!stp_online) {
  1265. chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000);
  1266. return;
  1267. }
  1268. rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0);
  1269. if (rc)
  1270. return;
  1271. rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi));
  1272. if (rc || stp_info.c == 0)
  1273. return;
  1274. /*
  1275. * Catch all other cpus and make them wait until we have
  1276. * successfully synced the clock. smp_call_function will
  1277. * return after all other cpus are in clock_sync_cpu_start.
  1278. */
  1279. memset(&stp_sync, 0, sizeof(stp_sync));
  1280. preempt_disable();
  1281. smp_call_function(clock_sync_cpu_start, &stp_sync, 0);
  1282. local_irq_disable();
  1283. enable_sync_clock();
  1284. set_bit(CLOCK_SYNC_STP, &clock_sync_flags);
  1285. if (test_and_clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags))
  1286. schedule_work(&etr_work);
  1287. rc = 0;
  1288. if (stp_info.todoff[0] || stp_info.todoff[1] ||
  1289. stp_info.todoff[2] || stp_info.todoff[3] ||
  1290. stp_info.tmd != 2) {
  1291. old_clock = get_clock();
  1292. rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0);
  1293. if (rc == 0) {
  1294. delta = adjust_time(old_clock, get_clock(), 0);
  1295. fixup_clock_comparator(delta);
  1296. rc = chsc_sstpi(stp_page, &stp_info,
  1297. sizeof(struct stp_sstpi));
  1298. if (rc == 0 && stp_info.tmd != 2)
  1299. rc = -EAGAIN;
  1300. }
  1301. }
  1302. if (rc) {
  1303. disable_sync_clock(NULL);
  1304. stp_sync.in_sync = -EAGAIN;
  1305. clear_bit(CLOCK_SYNC_STP, &clock_sync_flags);
  1306. if (etr_port0_online || etr_port1_online)
  1307. schedule_work(&etr_work);
  1308. } else
  1309. stp_sync.in_sync = 1;
  1310. local_irq_enable();
  1311. smp_call_function(clock_sync_cpu_end, NULL, 0);
  1312. preempt_enable();
  1313. }
  1314. /*
  1315. * STP class sysfs interface functions
  1316. */
  1317. static struct sysdev_class stp_sysclass = {
  1318. .name = "stp",
  1319. };
  1320. static ssize_t stp_ctn_id_show(struct sysdev_class *class, char *buf)
  1321. {
  1322. if (!stp_online)
  1323. return -ENODATA;
  1324. return sprintf(buf, "%016llx\n",
  1325. *(unsigned long long *) stp_info.ctnid);
  1326. }
  1327. static SYSDEV_CLASS_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL);
  1328. static ssize_t stp_ctn_type_show(struct sysdev_class *class, char *buf)
  1329. {
  1330. if (!stp_online)
  1331. return -ENODATA;
  1332. return sprintf(buf, "%i\n", stp_info.ctn);
  1333. }
  1334. static SYSDEV_CLASS_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL);
  1335. static ssize_t stp_dst_offset_show(struct sysdev_class *class, char *buf)
  1336. {
  1337. if (!stp_online || !(stp_info.vbits & 0x2000))
  1338. return -ENODATA;
  1339. return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto);
  1340. }
  1341. static SYSDEV_CLASS_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL);
  1342. static ssize_t stp_leap_seconds_show(struct sysdev_class *class, char *buf)
  1343. {
  1344. if (!stp_online || !(stp_info.vbits & 0x8000))
  1345. return -ENODATA;
  1346. return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps);
  1347. }
  1348. static SYSDEV_CLASS_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL);
  1349. static ssize_t stp_stratum_show(struct sysdev_class *class, char *buf)
  1350. {
  1351. if (!stp_online)
  1352. return -ENODATA;
  1353. return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum);
  1354. }
  1355. static SYSDEV_CLASS_ATTR(stratum, 0400, stp_stratum_show, NULL);
  1356. static ssize_t stp_time_offset_show(struct sysdev_class *class, char *buf)
  1357. {
  1358. if (!stp_online || !(stp_info.vbits & 0x0800))
  1359. return -ENODATA;
  1360. return sprintf(buf, "%i\n", (int) stp_info.tto);
  1361. }
  1362. static SYSDEV_CLASS_ATTR(time_offset, 0400, stp_time_offset_show, NULL);
  1363. static ssize_t stp_time_zone_offset_show(struct sysdev_class *class, char *buf)
  1364. {
  1365. if (!stp_online || !(stp_info.vbits & 0x4000))
  1366. return -ENODATA;
  1367. return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo);
  1368. }
  1369. static SYSDEV_CLASS_ATTR(time_zone_offset, 0400,
  1370. stp_time_zone_offset_show, NULL);
  1371. static ssize_t stp_timing_mode_show(struct sysdev_class *class, char *buf)
  1372. {
  1373. if (!stp_online)
  1374. return -ENODATA;
  1375. return sprintf(buf, "%i\n", stp_info.tmd);
  1376. }
  1377. static SYSDEV_CLASS_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL);
  1378. static ssize_t stp_timing_state_show(struct sysdev_class *class, char *buf)
  1379. {
  1380. if (!stp_online)
  1381. return -ENODATA;
  1382. return sprintf(buf, "%i\n", stp_info.tst);
  1383. }
  1384. static SYSDEV_CLASS_ATTR(timing_state, 0400, stp_timing_state_show, NULL);
  1385. static ssize_t stp_online_show(struct sysdev_class *class, char *buf)
  1386. {
  1387. return sprintf(buf, "%i\n", stp_online);
  1388. }
  1389. static ssize_t stp_online_store(struct sysdev_class *class,
  1390. const char *buf, size_t count)
  1391. {
  1392. unsigned int value;
  1393. value = simple_strtoul(buf, NULL, 0);
  1394. if (value != 0 && value != 1)
  1395. return -EINVAL;
  1396. if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags))
  1397. return -EOPNOTSUPP;
  1398. stp_online = value;
  1399. schedule_work(&stp_work);
  1400. return count;
  1401. }
  1402. /*
  1403. * Can't use SYSDEV_CLASS_ATTR because the attribute should be named
  1404. * stp/online but attr_online already exists in this file ..
  1405. */
  1406. static struct sysdev_class_attribute attr_stp_online = {
  1407. .attr = { .name = "online", .mode = 0600 },
  1408. .show = stp_online_show,
  1409. .store = stp_online_store,
  1410. };
  1411. static struct sysdev_class_attribute *stp_attributes[] = {
  1412. &attr_ctn_id,
  1413. &attr_ctn_type,
  1414. &attr_dst_offset,
  1415. &attr_leap_seconds,
  1416. &attr_stp_online,
  1417. &attr_stratum,
  1418. &attr_time_offset,
  1419. &attr_time_zone_offset,
  1420. &attr_timing_mode,
  1421. &attr_timing_state,
  1422. NULL
  1423. };
  1424. static int __init stp_init_sysfs(void)
  1425. {
  1426. struct sysdev_class_attribute **attr;
  1427. int rc;
  1428. rc = sysdev_class_register(&stp_sysclass);
  1429. if (rc)
  1430. goto out;
  1431. for (attr = stp_attributes; *attr; attr++) {
  1432. rc = sysdev_class_create_file(&stp_sysclass, *attr);
  1433. if (rc)
  1434. goto out_unreg;
  1435. }
  1436. return 0;
  1437. out_unreg:
  1438. for (; attr >= stp_attributes; attr--)
  1439. sysdev_class_remove_file(&stp_sysclass, *attr);
  1440. sysdev_class_unregister(&stp_sysclass);
  1441. out:
  1442. return rc;
  1443. }
  1444. device_initcall(stp_init_sysfs);