mpc836x_mds.c 4.5 KB

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  1. /*
  2. * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
  3. *
  4. * Author: Li Yang <LeoLi@freescale.com>
  5. * Yin Olivia <Hong-hua.Yin@freescale.com>
  6. *
  7. * Description:
  8. * MPC8360E MDS board specific routines.
  9. *
  10. * Changelog:
  11. * Jun 21, 2006 Initial version
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. */
  18. #include <linux/stddef.h>
  19. #include <linux/kernel.h>
  20. #include <linux/init.h>
  21. #include <linux/errno.h>
  22. #include <linux/reboot.h>
  23. #include <linux/pci.h>
  24. #include <linux/kdev_t.h>
  25. #include <linux/major.h>
  26. #include <linux/console.h>
  27. #include <linux/delay.h>
  28. #include <linux/seq_file.h>
  29. #include <linux/root_dev.h>
  30. #include <linux/initrd.h>
  31. #include <linux/of_platform.h>
  32. #include <linux/of_device.h>
  33. #include <asm/system.h>
  34. #include <asm/atomic.h>
  35. #include <asm/time.h>
  36. #include <asm/io.h>
  37. #include <asm/machdep.h>
  38. #include <asm/ipic.h>
  39. #include <asm/irq.h>
  40. #include <asm/prom.h>
  41. #include <asm/udbg.h>
  42. #include <sysdev/fsl_soc.h>
  43. #include <sysdev/fsl_pci.h>
  44. #include <asm/qe.h>
  45. #include <asm/qe_ic.h>
  46. #include "mpc83xx.h"
  47. #undef DEBUG
  48. #ifdef DEBUG
  49. #define DBG(fmt...) udbg_printf(fmt)
  50. #else
  51. #define DBG(fmt...)
  52. #endif
  53. static u8 *bcsr_regs = NULL;
  54. /* ************************************************************************
  55. *
  56. * Setup the architecture
  57. *
  58. */
  59. static void __init mpc836x_mds_setup_arch(void)
  60. {
  61. struct device_node *np;
  62. if (ppc_md.progress)
  63. ppc_md.progress("mpc836x_mds_setup_arch()", 0);
  64. /* Map BCSR area */
  65. np = of_find_node_by_name(NULL, "bcsr");
  66. if (np != 0) {
  67. struct resource res;
  68. of_address_to_resource(np, 0, &res);
  69. bcsr_regs = ioremap(res.start, res.end - res.start +1);
  70. of_node_put(np);
  71. }
  72. #ifdef CONFIG_PCI
  73. for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
  74. mpc83xx_add_bridge(np);
  75. #endif
  76. #ifdef CONFIG_QUICC_ENGINE
  77. qe_reset();
  78. if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
  79. par_io_init(np);
  80. of_node_put(np);
  81. for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
  82. par_io_of_config(np);
  83. }
  84. if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
  85. != NULL){
  86. uint svid;
  87. /* Reset the Ethernet PHY */
  88. #define BCSR9_GETHRST 0x20
  89. clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
  90. udelay(1000);
  91. setbits8(&bcsr_regs[9], BCSR9_GETHRST);
  92. /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
  93. svid = mfspr(SPRN_SVR);
  94. if (svid == 0x80480021) {
  95. void __iomem *immap;
  96. immap = ioremap(get_immrbase() + 0x14a8, 8);
  97. /*
  98. * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
  99. * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
  100. */
  101. setbits32(immap, 0x0c003000);
  102. /*
  103. * IMMR + 0x14AC[20:27] = 10101010
  104. * (data delay for both UCC's)
  105. */
  106. clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
  107. iounmap(immap);
  108. }
  109. iounmap(bcsr_regs);
  110. of_node_put(np);
  111. }
  112. #endif /* CONFIG_QUICC_ENGINE */
  113. }
  114. static struct of_device_id mpc836x_ids[] = {
  115. { .type = "soc", },
  116. { .compatible = "soc", },
  117. { .compatible = "simple-bus", },
  118. { .type = "qe", },
  119. { .compatible = "fsl,qe", },
  120. {},
  121. };
  122. static int __init mpc836x_declare_of_platform_devices(void)
  123. {
  124. /* Publish the QE devices */
  125. of_platform_bus_probe(NULL, mpc836x_ids, NULL);
  126. return 0;
  127. }
  128. machine_device_initcall(mpc836x_mds, mpc836x_declare_of_platform_devices);
  129. static void __init mpc836x_mds_init_IRQ(void)
  130. {
  131. struct device_node *np;
  132. np = of_find_node_by_type(NULL, "ipic");
  133. if (!np)
  134. return;
  135. ipic_init(np, 0);
  136. /* Initialize the default interrupt mapping priorities,
  137. * in case the boot rom changed something on us.
  138. */
  139. ipic_set_default_priority();
  140. of_node_put(np);
  141. #ifdef CONFIG_QUICC_ENGINE
  142. np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
  143. if (!np) {
  144. np = of_find_node_by_type(NULL, "qeic");
  145. if (!np)
  146. return;
  147. }
  148. qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
  149. of_node_put(np);
  150. #endif /* CONFIG_QUICC_ENGINE */
  151. }
  152. /*
  153. * Called very early, MMU is off, device-tree isn't unflattened
  154. */
  155. static int __init mpc836x_mds_probe(void)
  156. {
  157. unsigned long root = of_get_flat_dt_root();
  158. return of_flat_dt_is_compatible(root, "MPC836xMDS");
  159. }
  160. define_machine(mpc836x_mds) {
  161. .name = "MPC836x MDS",
  162. .probe = mpc836x_mds_probe,
  163. .setup_arch = mpc836x_mds_setup_arch,
  164. .init_IRQ = mpc836x_mds_init_IRQ,
  165. .get_irq = ipic_get_irq,
  166. .restart = mpc83xx_restart,
  167. .time_init = mpc83xx_time_init,
  168. .calibrate_decr = generic_calibrate_decr,
  169. .progress = udbg_progress,
  170. };