mpc832x_rdb.c 4.4 KB

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  1. /*
  2. * arch/powerpc/platforms/83xx/mpc832x_rdb.c
  3. *
  4. * Copyright (C) Freescale Semiconductor, Inc. 2007. All rights reserved.
  5. *
  6. * Description:
  7. * MPC832x RDB board specific routines.
  8. * This file is based on mpc832x_mds.c and mpc8313_rdb.c
  9. * Author: Michael Barkowski <michael.barkowski@freescale.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify it
  12. * under the terms of the GNU General Public License as published by the
  13. * Free Software Foundation; either version 2 of the License, or (at your
  14. * option) any later version.
  15. */
  16. #include <linux/pci.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/spi/mmc_spi.h>
  20. #include <linux/mmc/host.h>
  21. #include <linux/of_platform.h>
  22. #include <asm/time.h>
  23. #include <asm/ipic.h>
  24. #include <asm/udbg.h>
  25. #include <asm/qe.h>
  26. #include <asm/qe_ic.h>
  27. #include <sysdev/fsl_soc.h>
  28. #include <sysdev/fsl_pci.h>
  29. #include "mpc83xx.h"
  30. #undef DEBUG
  31. #ifdef DEBUG
  32. #define DBG(fmt...) udbg_printf(fmt)
  33. #else
  34. #define DBG(fmt...)
  35. #endif
  36. static void mpc83xx_spi_activate_cs(u8 cs, u8 polarity)
  37. {
  38. pr_debug("%s %d %d\n", __func__, cs, polarity);
  39. par_io_data_set(3, 13, polarity);
  40. }
  41. static void mpc83xx_spi_deactivate_cs(u8 cs, u8 polarity)
  42. {
  43. pr_debug("%s %d %d\n", __func__, cs, polarity);
  44. par_io_data_set(3, 13, !polarity);
  45. }
  46. static struct mmc_spi_platform_data mpc832x_mmc_pdata = {
  47. .ocr_mask = MMC_VDD_33_34,
  48. };
  49. static struct spi_board_info mpc832x_spi_boardinfo = {
  50. .bus_num = 0x4c0,
  51. .chip_select = 0,
  52. .max_speed_hz = 50000000,
  53. .modalias = "mmc_spi",
  54. .platform_data = &mpc832x_mmc_pdata,
  55. };
  56. static int __init mpc832x_spi_init(void)
  57. {
  58. par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */
  59. par_io_config_pin(3, 1, 3, 0, 1, 0); /* SPI1 MISO, I/O */
  60. par_io_config_pin(3, 2, 3, 0, 1, 0); /* SPI1 CLK, I/O */
  61. par_io_config_pin(3, 3, 2, 0, 1, 0); /* SPI1 SEL, I */
  62. par_io_config_pin(3, 13, 1, 0, 0, 0); /* !SD_CS, O */
  63. par_io_config_pin(3, 14, 2, 0, 0, 0); /* SD_INSERT, I */
  64. par_io_config_pin(3, 15, 2, 0, 0, 0); /* SD_PROTECT,I */
  65. return fsl_spi_init(&mpc832x_spi_boardinfo, 1,
  66. mpc83xx_spi_activate_cs,
  67. mpc83xx_spi_deactivate_cs);
  68. }
  69. machine_device_initcall(mpc832x_rdb, mpc832x_spi_init);
  70. /* ************************************************************************
  71. *
  72. * Setup the architecture
  73. *
  74. */
  75. static void __init mpc832x_rdb_setup_arch(void)
  76. {
  77. #if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
  78. struct device_node *np;
  79. #endif
  80. if (ppc_md.progress)
  81. ppc_md.progress("mpc832x_rdb_setup_arch()", 0);
  82. #ifdef CONFIG_PCI
  83. for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
  84. mpc83xx_add_bridge(np);
  85. #endif
  86. #ifdef CONFIG_QUICC_ENGINE
  87. qe_reset();
  88. if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
  89. par_io_init(np);
  90. of_node_put(np);
  91. for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
  92. par_io_of_config(np);
  93. }
  94. #endif /* CONFIG_QUICC_ENGINE */
  95. }
  96. static struct of_device_id mpc832x_ids[] = {
  97. { .type = "soc", },
  98. { .compatible = "soc", },
  99. { .compatible = "simple-bus", },
  100. { .type = "qe", },
  101. { .compatible = "fsl,qe", },
  102. {},
  103. };
  104. static int __init mpc832x_declare_of_platform_devices(void)
  105. {
  106. /* Publish the QE devices */
  107. of_platform_bus_probe(NULL, mpc832x_ids, NULL);
  108. return 0;
  109. }
  110. machine_device_initcall(mpc832x_rdb, mpc832x_declare_of_platform_devices);
  111. void __init mpc832x_rdb_init_IRQ(void)
  112. {
  113. struct device_node *np;
  114. np = of_find_node_by_type(NULL, "ipic");
  115. if (!np)
  116. return;
  117. ipic_init(np, 0);
  118. /* Initialize the default interrupt mapping priorities,
  119. * in case the boot rom changed something on us.
  120. */
  121. ipic_set_default_priority();
  122. of_node_put(np);
  123. #ifdef CONFIG_QUICC_ENGINE
  124. np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
  125. if (!np) {
  126. np = of_find_node_by_type(NULL, "qeic");
  127. if (!np)
  128. return;
  129. }
  130. qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
  131. of_node_put(np);
  132. #endif /* CONFIG_QUICC_ENGINE */
  133. }
  134. /*
  135. * Called very early, MMU is off, device-tree isn't unflattened
  136. */
  137. static int __init mpc832x_rdb_probe(void)
  138. {
  139. unsigned long root = of_get_flat_dt_root();
  140. return of_flat_dt_is_compatible(root, "MPC832xRDB");
  141. }
  142. define_machine(mpc832x_rdb) {
  143. .name = "MPC832x RDB",
  144. .probe = mpc832x_rdb_probe,
  145. .setup_arch = mpc832x_rdb_setup_arch,
  146. .init_IRQ = mpc832x_rdb_init_IRQ,
  147. .get_irq = ipic_get_irq,
  148. .restart = mpc83xx_restart,
  149. .time_init = mpc83xx_time_init,
  150. .calibrate_decr = generic_calibrate_decr,
  151. .progress = udbg_progress,
  152. };