pq2ads-pci-pic.c 4.2 KB

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  1. /*
  2. * PQ2 ADS-style PCI interrupt controller
  3. *
  4. * Copyright 2007 Freescale Semiconductor, Inc.
  5. * Author: Scott Wood <scottwood@freescale.com>
  6. *
  7. * Loosely based on mpc82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
  8. * Copyright (c) 2006 MontaVista Software, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License version 2 as published
  12. * by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/irq.h>
  17. #include <linux/types.h>
  18. #include <linux/bootmem.h>
  19. #include <asm/io.h>
  20. #include <asm/prom.h>
  21. #include <asm/cpm2.h>
  22. #include "pq2.h"
  23. static DEFINE_SPINLOCK(pci_pic_lock);
  24. struct pq2ads_pci_pic {
  25. struct device_node *node;
  26. struct irq_host *host;
  27. struct {
  28. u32 stat;
  29. u32 mask;
  30. } __iomem *regs;
  31. };
  32. #define NUM_IRQS 32
  33. static void pq2ads_pci_mask_irq(unsigned int virq)
  34. {
  35. struct pq2ads_pci_pic *priv = get_irq_chip_data(virq);
  36. int irq = NUM_IRQS - virq_to_hw(virq) - 1;
  37. if (irq != -1) {
  38. unsigned long flags;
  39. spin_lock_irqsave(&pci_pic_lock, flags);
  40. setbits32(&priv->regs->mask, 1 << irq);
  41. mb();
  42. spin_unlock_irqrestore(&pci_pic_lock, flags);
  43. }
  44. }
  45. static void pq2ads_pci_unmask_irq(unsigned int virq)
  46. {
  47. struct pq2ads_pci_pic *priv = get_irq_chip_data(virq);
  48. int irq = NUM_IRQS - virq_to_hw(virq) - 1;
  49. if (irq != -1) {
  50. unsigned long flags;
  51. spin_lock_irqsave(&pci_pic_lock, flags);
  52. clrbits32(&priv->regs->mask, 1 << irq);
  53. spin_unlock_irqrestore(&pci_pic_lock, flags);
  54. }
  55. }
  56. static struct irq_chip pq2ads_pci_ic = {
  57. .typename = "PQ2 ADS PCI",
  58. .name = "PQ2 ADS PCI",
  59. .end = pq2ads_pci_unmask_irq,
  60. .mask = pq2ads_pci_mask_irq,
  61. .mask_ack = pq2ads_pci_mask_irq,
  62. .ack = pq2ads_pci_mask_irq,
  63. .unmask = pq2ads_pci_unmask_irq,
  64. .enable = pq2ads_pci_unmask_irq,
  65. .disable = pq2ads_pci_mask_irq
  66. };
  67. static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
  68. {
  69. struct pq2ads_pci_pic *priv = desc->handler_data;
  70. u32 stat, mask, pend;
  71. int bit;
  72. for (;;) {
  73. stat = in_be32(&priv->regs->stat);
  74. mask = in_be32(&priv->regs->mask);
  75. pend = stat & ~mask;
  76. if (!pend)
  77. break;
  78. for (bit = 0; pend != 0; ++bit, pend <<= 1) {
  79. if (pend & 0x80000000) {
  80. int virq = irq_linear_revmap(priv->host, bit);
  81. generic_handle_irq(virq);
  82. }
  83. }
  84. }
  85. }
  86. static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
  87. irq_hw_number_t hw)
  88. {
  89. get_irq_desc(virq)->status |= IRQ_LEVEL;
  90. set_irq_chip_data(virq, h->host_data);
  91. set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
  92. return 0;
  93. }
  94. static void pci_host_unmap(struct irq_host *h, unsigned int virq)
  95. {
  96. /* remove chip and handler */
  97. set_irq_chip_data(virq, NULL);
  98. set_irq_chip(virq, NULL);
  99. }
  100. static struct irq_host_ops pci_pic_host_ops = {
  101. .map = pci_pic_host_map,
  102. .unmap = pci_host_unmap,
  103. };
  104. int __init pq2ads_pci_init_irq(void)
  105. {
  106. struct pq2ads_pci_pic *priv;
  107. struct irq_host *host;
  108. struct device_node *np;
  109. int ret = -ENODEV;
  110. int irq;
  111. np = of_find_compatible_node(NULL, NULL, "fsl,pq2ads-pci-pic");
  112. if (!np) {
  113. printk(KERN_ERR "No pci pic node in device tree.\n");
  114. of_node_put(np);
  115. goto out;
  116. }
  117. irq = irq_of_parse_and_map(np, 0);
  118. if (irq == NO_IRQ) {
  119. printk(KERN_ERR "No interrupt in pci pic node.\n");
  120. of_node_put(np);
  121. goto out;
  122. }
  123. priv = alloc_bootmem(sizeof(struct pq2ads_pci_pic));
  124. if (!priv) {
  125. of_node_put(np);
  126. ret = -ENOMEM;
  127. goto out_unmap_irq;
  128. }
  129. /* PCI interrupt controller registers: status and mask */
  130. priv->regs = of_iomap(np, 0);
  131. if (!priv->regs) {
  132. printk(KERN_ERR "Cannot map PCI PIC registers.\n");
  133. goto out_free_bootmem;
  134. }
  135. /* mask all PCI interrupts */
  136. out_be32(&priv->regs->mask, ~0);
  137. mb();
  138. host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, NUM_IRQS,
  139. &pci_pic_host_ops, NUM_IRQS);
  140. if (!host) {
  141. ret = -ENOMEM;
  142. goto out_unmap_regs;
  143. }
  144. host->host_data = priv;
  145. priv->host = host;
  146. host->host_data = priv;
  147. set_irq_data(irq, priv);
  148. set_irq_chained_handler(irq, pq2ads_pci_irq_demux);
  149. of_node_put(np);
  150. return 0;
  151. out_unmap_regs:
  152. iounmap(priv->regs);
  153. out_free_bootmem:
  154. free_bootmem((unsigned long)priv,
  155. sizeof(sizeof(struct pq2ads_pci_pic)));
  156. of_node_put(np);
  157. out_unmap_irq:
  158. irq_dispose_mapping(irq);
  159. out:
  160. return ret;
  161. }