dcr-native.h 3.3 KB

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  1. /*
  2. * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
  3. * <benh@kernel.crashing.org>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
  13. * the GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #ifndef _ASM_POWERPC_DCR_NATIVE_H
  20. #define _ASM_POWERPC_DCR_NATIVE_H
  21. #ifdef __KERNEL__
  22. #ifndef __ASSEMBLY__
  23. #include <linux/spinlock.h>
  24. typedef struct {
  25. unsigned int base;
  26. } dcr_host_native_t;
  27. static inline bool dcr_map_ok_native(dcr_host_native_t host)
  28. {
  29. return 1;
  30. }
  31. #define dcr_map_native(dev, dcr_n, dcr_c) \
  32. ((dcr_host_native_t){ .base = (dcr_n) })
  33. #define dcr_unmap_native(host, dcr_c) do {} while (0)
  34. #define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)
  35. #define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
  36. /* Device Control Registers */
  37. void __mtdcr(int reg, unsigned int val);
  38. unsigned int __mfdcr(int reg);
  39. #define mfdcr(rn) \
  40. ({unsigned int rval; \
  41. if (__builtin_constant_p(rn)) \
  42. asm volatile("mfdcr %0," __stringify(rn) \
  43. : "=r" (rval)); \
  44. else \
  45. rval = __mfdcr(rn); \
  46. rval;})
  47. #define mtdcr(rn, v) \
  48. do { \
  49. if (__builtin_constant_p(rn)) \
  50. asm volatile("mtdcr " __stringify(rn) ",%0" \
  51. : : "r" (v)); \
  52. else \
  53. __mtdcr(rn, v); \
  54. } while (0)
  55. /* R/W of indirect DCRs make use of standard naming conventions for DCRs */
  56. extern spinlock_t dcr_ind_lock;
  57. static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
  58. {
  59. unsigned long flags;
  60. unsigned int val;
  61. spin_lock_irqsave(&dcr_ind_lock, flags);
  62. __mtdcr(base_addr, reg);
  63. val = __mfdcr(base_data);
  64. spin_unlock_irqrestore(&dcr_ind_lock, flags);
  65. return val;
  66. }
  67. static inline void __mtdcri(int base_addr, int base_data, int reg,
  68. unsigned val)
  69. {
  70. unsigned long flags;
  71. spin_lock_irqsave(&dcr_ind_lock, flags);
  72. __mtdcr(base_addr, reg);
  73. __mtdcr(base_data, val);
  74. spin_unlock_irqrestore(&dcr_ind_lock, flags);
  75. }
  76. static inline void __dcri_clrset(int base_addr, int base_data, int reg,
  77. unsigned clr, unsigned set)
  78. {
  79. unsigned long flags;
  80. unsigned int val;
  81. spin_lock_irqsave(&dcr_ind_lock, flags);
  82. __mtdcr(base_addr, reg);
  83. val = (__mfdcr(base_data) & ~clr) | set;
  84. __mtdcr(base_data, val);
  85. spin_unlock_irqrestore(&dcr_ind_lock, flags);
  86. }
  87. #define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
  88. DCRN_ ## base ## _CONFIG_DATA, \
  89. reg)
  90. #define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \
  91. DCRN_ ## base ## _CONFIG_DATA, \
  92. reg, data)
  93. #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \
  94. DCRN_ ## base ## _CONFIG_DATA, \
  95. reg, clr, set)
  96. #endif /* __ASSEMBLY__ */
  97. #endif /* __KERNEL__ */
  98. #endif /* _ASM_POWERPC_DCR_NATIVE_H */