stx_gp3_8560.dts 6.0 KB

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  1. /*
  2. * STX GP3 - 8560 ADS Device Tree Source
  3. *
  4. * Copyright 2008 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "stx,gp3";
  14. compatible = "stx,gp3-8560", "stx,gp3";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. pci0 = &pci0;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8560@0 {
  27. device_type = "cpu";
  28. reg = <0>;
  29. d-cache-line-size = <32>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <32768>;
  32. i-cache-size = <32768>;
  33. timebase-frequency = <0>;
  34. bus-frequency = <0>;
  35. clock-frequency = <0>;
  36. next-level-cache = <&L2>;
  37. };
  38. };
  39. memory {
  40. device_type = "memory";
  41. reg = <0x00000000 0x10000000>;
  42. };
  43. soc@fdf00000 {
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. device_type = "soc";
  47. ranges = <0 0xfdf00000 0x100000>;
  48. reg = <0xfdf00000 0x1000>;
  49. bus-frequency = <0>;
  50. compatible = "fsl,mpc8560-immr", "simple-bus";
  51. memory-controller@2000 {
  52. compatible = "fsl,8540-memory-controller";
  53. reg = <0x2000 0x1000>;
  54. interrupt-parent = <&mpic>;
  55. interrupts = <18 2>;
  56. };
  57. L2: l2-cache-controller@20000 {
  58. compatible = "fsl,8540-l2-cache-controller";
  59. reg = <0x20000 0x1000>;
  60. cache-line-size = <32>;
  61. cache-size = <0x40000>; // L2, 256K
  62. interrupt-parent = <&mpic>;
  63. interrupts = <16 2>;
  64. };
  65. i2c@3000 {
  66. #address-cells = <1>;
  67. #size-cells = <0>;
  68. cell-index = <0>;
  69. compatible = "fsl-i2c";
  70. reg = <0x3000 0x100>;
  71. interrupts = <43 2>;
  72. interrupt-parent = <&mpic>;
  73. dfsrr;
  74. };
  75. dma@21300 {
  76. #address-cells = <1>;
  77. #size-cells = <1>;
  78. compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
  79. reg = <0x21300 0x4>;
  80. ranges = <0x0 0x21100 0x200>;
  81. cell-index = <0>;
  82. dma-channel@0 {
  83. compatible = "fsl,mpc8560-dma-channel",
  84. "fsl,eloplus-dma-channel";
  85. reg = <0x0 0x80>;
  86. cell-index = <0>;
  87. interrupt-parent = <&mpic>;
  88. interrupts = <20 2>;
  89. };
  90. dma-channel@80 {
  91. compatible = "fsl,mpc8560-dma-channel",
  92. "fsl,eloplus-dma-channel";
  93. reg = <0x80 0x80>;
  94. cell-index = <1>;
  95. interrupt-parent = <&mpic>;
  96. interrupts = <21 2>;
  97. };
  98. dma-channel@100 {
  99. compatible = "fsl,mpc8560-dma-channel",
  100. "fsl,eloplus-dma-channel";
  101. reg = <0x100 0x80>;
  102. cell-index = <2>;
  103. interrupt-parent = <&mpic>;
  104. interrupts = <22 2>;
  105. };
  106. dma-channel@180 {
  107. compatible = "fsl,mpc8560-dma-channel",
  108. "fsl,eloplus-dma-channel";
  109. reg = <0x180 0x80>;
  110. cell-index = <3>;
  111. interrupt-parent = <&mpic>;
  112. interrupts = <23 2>;
  113. };
  114. };
  115. mdio@24520 {
  116. #address-cells = <1>;
  117. #size-cells = <0>;
  118. compatible = "fsl,gianfar-mdio";
  119. reg = <0x24520 0x20>;
  120. phy2: ethernet-phy@2 {
  121. interrupt-parent = <&mpic>;
  122. interrupts = <5 4>;
  123. reg = <2>;
  124. device_type = "ethernet-phy";
  125. };
  126. phy4: ethernet-phy@4 {
  127. interrupt-parent = <&mpic>;
  128. interrupts = <5 4>;
  129. reg = <4>;
  130. device_type = "ethernet-phy";
  131. };
  132. };
  133. enet0: ethernet@24000 {
  134. cell-index = <0>;
  135. device_type = "network";
  136. model = "TSEC";
  137. compatible = "gianfar";
  138. reg = <0x24000 0x1000>;
  139. local-mac-address = [ 00 00 00 00 00 00 ];
  140. interrupts = <29 2 30 2 34 2>;
  141. interrupt-parent = <&mpic>;
  142. phy-handle = <&phy2>;
  143. };
  144. enet1: ethernet@25000 {
  145. cell-index = <1>;
  146. device_type = "network";
  147. model = "TSEC";
  148. compatible = "gianfar";
  149. reg = <0x25000 0x1000>;
  150. local-mac-address = [ 00 00 00 00 00 00 ];
  151. interrupts = <35 2 36 2 40 2>;
  152. interrupt-parent = <&mpic>;
  153. phy-handle = <&phy4>;
  154. };
  155. mpic: pic@40000 {
  156. interrupt-controller;
  157. #address-cells = <0>;
  158. #interrupt-cells = <2>;
  159. reg = <0x40000 0x40000>;
  160. compatible = "chrp,open-pic";
  161. device_type = "open-pic";
  162. };
  163. cpm@919c0 {
  164. #address-cells = <1>;
  165. #size-cells = <1>;
  166. compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
  167. reg = <0x919c0 0x30>;
  168. ranges;
  169. muram@80000 {
  170. #address-cells = <1>;
  171. #size-cells = <1>;
  172. ranges = <0 0x80000 0x10000>;
  173. data@0 {
  174. compatible = "fsl,cpm-muram-data";
  175. reg = <0 0x4000 0x9000 0x2000>;
  176. };
  177. };
  178. brg@919f0 {
  179. compatible = "fsl,mpc8560-brg",
  180. "fsl,cpm2-brg",
  181. "fsl,cpm-brg";
  182. reg = <0x919f0 0x10 0x915f0 0x10>;
  183. clock-frequency = <0>;
  184. };
  185. cpmpic: pic@90c00 {
  186. interrupt-controller;
  187. #address-cells = <0>;
  188. #interrupt-cells = <2>;
  189. interrupts = <46 2>;
  190. interrupt-parent = <&mpic>;
  191. reg = <0x90c00 0x80>;
  192. compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
  193. };
  194. serial0: serial@91a20 {
  195. device_type = "serial";
  196. compatible = "fsl,mpc8560-scc-uart",
  197. "fsl,cpm2-scc-uart";
  198. reg = <0x91a20 0x20 0x88100 0x100>;
  199. fsl,cpm-brg = <2>;
  200. fsl,cpm-command = <0x4a00000>;
  201. interrupts = <41 8>;
  202. interrupt-parent = <&cpmpic>;
  203. };
  204. };
  205. };
  206. pci0: pci@fdf08000 {
  207. cell-index = <0>;
  208. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  209. interrupt-map = <
  210. /* IDSEL 0x0c */
  211. 0x6000 0 0 1 &mpic 1 1
  212. 0x6000 0 0 2 &mpic 2 1
  213. 0x6000 0 0 3 &mpic 3 1
  214. 0x6000 0 0 4 &mpic 4 1
  215. /* IDSEL 0x0d */
  216. 0x6800 0 0 1 &mpic 4 1
  217. 0x6800 0 0 2 &mpic 1 1
  218. 0x6800 0 0 3 &mpic 2 1
  219. 0x6800 0 0 4 &mpic 3 1
  220. /* IDSEL 0x0e */
  221. 0x7000 0 0 1 &mpic 3 1
  222. 0x7000 0 0 2 &mpic 4 1
  223. 0x7000 0 0 3 &mpic 1 1
  224. 0x7000 0 0 4 &mpic 2 1
  225. /* IDSEL 0x0f */
  226. 0x7800 0 0 1 &mpic 2 1
  227. 0x7800 0 0 2 &mpic 3 1
  228. 0x7800 0 0 3 &mpic 4 1
  229. 0x7800 0 0 4 &mpic 1 1>;
  230. interrupt-parent = <&mpic>;
  231. interrupts = <24 2>;
  232. bus-range = <0 0>;
  233. ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
  234. 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
  235. clock-frequency = <66666666>;
  236. #interrupt-cells = <1>;
  237. #size-cells = <2>;
  238. #address-cells = <3>;
  239. reg = <0xfdf08000 0x1000>;
  240. compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
  241. device_type = "pci";
  242. };
  243. };