sbc8349.dts 6.2 KB

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  1. /*
  2. * SBC8349E Device Tree Source
  3. *
  4. * Copyright 2007 Wind River Inc.
  5. *
  6. * Paul Gortmaker (see MAINTAINERS for contact information)
  7. *
  8. * -based largely on the Freescale MPC834x_MDS dts.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. /dts-v1/;
  16. / {
  17. model = "SBC8349E";
  18. compatible = "SBC834xE";
  19. #address-cells = <1>;
  20. #size-cells = <1>;
  21. aliases {
  22. ethernet0 = &enet0;
  23. ethernet1 = &enet1;
  24. serial0 = &serial0;
  25. serial1 = &serial1;
  26. pci0 = &pci0;
  27. };
  28. cpus {
  29. #address-cells = <1>;
  30. #size-cells = <0>;
  31. PowerPC,8349@0 {
  32. device_type = "cpu";
  33. reg = <0x0>;
  34. d-cache-line-size = <32>;
  35. i-cache-line-size = <32>;
  36. d-cache-size = <32768>;
  37. i-cache-size = <32768>;
  38. timebase-frequency = <0>; // from bootloader
  39. bus-frequency = <0>; // from bootloader
  40. clock-frequency = <0>; // from bootloader
  41. };
  42. };
  43. memory {
  44. device_type = "memory";
  45. reg = <0x00000000 0x10000000>; // 256MB at 0
  46. };
  47. soc8349@e0000000 {
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. device_type = "soc";
  51. ranges = <0x0 0xe0000000 0x00100000>;
  52. reg = <0xe0000000 0x00000200>;
  53. bus-frequency = <0>;
  54. wdt@200 {
  55. compatible = "mpc83xx_wdt";
  56. reg = <0x200 0x100>;
  57. };
  58. i2c@3000 {
  59. #address-cells = <1>;
  60. #size-cells = <0>;
  61. cell-index = <0>;
  62. compatible = "fsl-i2c";
  63. reg = <0x3000 0x100>;
  64. interrupts = <14 0x8>;
  65. interrupt-parent = <&ipic>;
  66. dfsrr;
  67. };
  68. i2c@3100 {
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. cell-index = <1>;
  72. compatible = "fsl-i2c";
  73. reg = <0x3100 0x100>;
  74. interrupts = <15 0x8>;
  75. interrupt-parent = <&ipic>;
  76. dfsrr;
  77. };
  78. spi@7000 {
  79. cell-index = <0>;
  80. compatible = "fsl,spi";
  81. reg = <0x7000 0x1000>;
  82. interrupts = <16 0x8>;
  83. interrupt-parent = <&ipic>;
  84. mode = "cpu";
  85. };
  86. dma@82a8 {
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  90. reg = <0x82a8 4>;
  91. ranges = <0 0x8100 0x1a8>;
  92. interrupt-parent = <&ipic>;
  93. interrupts = <71 8>;
  94. cell-index = <0>;
  95. dma-channel@0 {
  96. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  97. reg = <0 0x80>;
  98. interrupt-parent = <&ipic>;
  99. interrupts = <71 8>;
  100. };
  101. dma-channel@80 {
  102. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  103. reg = <0x80 0x80>;
  104. interrupt-parent = <&ipic>;
  105. interrupts = <71 8>;
  106. };
  107. dma-channel@100 {
  108. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  109. reg = <0x100 0x80>;
  110. interrupt-parent = <&ipic>;
  111. interrupts = <71 8>;
  112. };
  113. dma-channel@180 {
  114. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  115. reg = <0x180 0x28>;
  116. interrupt-parent = <&ipic>;
  117. interrupts = <71 8>;
  118. };
  119. };
  120. /* phy type (ULPI or SERIAL) are only types supported for MPH */
  121. /* port = 0 or 1 */
  122. usb@22000 {
  123. compatible = "fsl-usb2-mph";
  124. reg = <0x22000 0x1000>;
  125. #address-cells = <1>;
  126. #size-cells = <0>;
  127. interrupt-parent = <&ipic>;
  128. interrupts = <39 0x8>;
  129. phy_type = "ulpi";
  130. port1;
  131. };
  132. /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
  133. usb@23000 {
  134. device_type = "usb";
  135. compatible = "fsl-usb2-dr";
  136. reg = <0x23000 0x1000>;
  137. #address-cells = <1>;
  138. #size-cells = <0>;
  139. interrupt-parent = <&ipic>;
  140. interrupts = <38 0x8>;
  141. dr_mode = "otg";
  142. phy_type = "ulpi";
  143. };
  144. mdio@24520 {
  145. #address-cells = <1>;
  146. #size-cells = <0>;
  147. compatible = "fsl,gianfar-mdio";
  148. reg = <0x24520 0x20>;
  149. phy0: ethernet-phy@19 {
  150. interrupt-parent = <&ipic>;
  151. interrupts = <20 0x8>;
  152. reg = <0x19>;
  153. device_type = "ethernet-phy";
  154. };
  155. phy1: ethernet-phy@1a {
  156. interrupt-parent = <&ipic>;
  157. interrupts = <21 0x8>;
  158. reg = <0x1a>;
  159. device_type = "ethernet-phy";
  160. };
  161. };
  162. enet0: ethernet@24000 {
  163. cell-index = <0>;
  164. device_type = "network";
  165. model = "TSEC";
  166. compatible = "gianfar";
  167. reg = <0x24000 0x1000>;
  168. local-mac-address = [ 00 00 00 00 00 00 ];
  169. interrupts = <32 0x8 33 0x8 34 0x8>;
  170. interrupt-parent = <&ipic>;
  171. phy-handle = <&phy0>;
  172. linux,network-index = <0>;
  173. };
  174. enet1: ethernet@25000 {
  175. cell-index = <1>;
  176. device_type = "network";
  177. model = "TSEC";
  178. compatible = "gianfar";
  179. reg = <0x25000 0x1000>;
  180. local-mac-address = [ 00 00 00 00 00 00 ];
  181. interrupts = <35 0x8 36 0x8 37 0x8>;
  182. interrupt-parent = <&ipic>;
  183. phy-handle = <&phy1>;
  184. linux,network-index = <1>;
  185. };
  186. serial0: serial@4500 {
  187. cell-index = <0>;
  188. device_type = "serial";
  189. compatible = "ns16550";
  190. reg = <0x4500 0x100>;
  191. clock-frequency = <0>;
  192. interrupts = <9 0x8>;
  193. interrupt-parent = <&ipic>;
  194. };
  195. serial1: serial@4600 {
  196. cell-index = <1>;
  197. device_type = "serial";
  198. compatible = "ns16550";
  199. reg = <0x4600 0x100>;
  200. clock-frequency = <0>;
  201. interrupts = <10 0x8>;
  202. interrupt-parent = <&ipic>;
  203. };
  204. crypto@30000 {
  205. compatible = "fsl,sec2.0";
  206. reg = <0x30000 0x10000>;
  207. interrupts = <11 0x8>;
  208. interrupt-parent = <&ipic>;
  209. fsl,num-channels = <4>;
  210. fsl,channel-fifo-len = <24>;
  211. fsl,exec-units-mask = <0x7e>;
  212. fsl,descriptor-types-mask = <0x01010ebf>;
  213. };
  214. /* IPIC
  215. * interrupts cell = <intr #, sense>
  216. * sense values match linux IORESOURCE_IRQ_* defines:
  217. * sense == 8: Level, low assertion
  218. * sense == 2: Edge, high-to-low change
  219. */
  220. ipic: pic@700 {
  221. interrupt-controller;
  222. #address-cells = <0>;
  223. #interrupt-cells = <2>;
  224. reg = <0x700 0x100>;
  225. device_type = "ipic";
  226. };
  227. };
  228. pci0: pci@e0008500 {
  229. cell-index = <1>;
  230. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  231. interrupt-map = <
  232. /* IDSEL 0x11 */
  233. 0x8800 0x0 0x0 0x1 &ipic 20 0x8
  234. 0x8800 0x0 0x0 0x2 &ipic 21 0x8
  235. 0x8800 0x0 0x0 0x3 &ipic 22 0x8
  236. 0x8800 0x0 0x0 0x4 &ipic 23 0x8>;
  237. interrupt-parent = <&ipic>;
  238. interrupts = <0x42 0x8>;
  239. bus-range = <0 0>;
  240. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  241. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  242. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
  243. clock-frequency = <66666666>;
  244. #interrupt-cells = <1>;
  245. #size-cells = <2>;
  246. #address-cells = <3>;
  247. reg = <0xe0008500 0x100>;
  248. compatible = "fsl,mpc8349-pci";
  249. device_type = "pci";
  250. };
  251. };