mpc8378_rdb.dts 7.0 KB

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  1. /*
  2. * MPC8378E RDB Device Tree Source
  3. *
  4. * Copyright 2007, 2008 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. compatible = "fsl,mpc8378rdb";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. aliases {
  17. ethernet0 = &enet0;
  18. ethernet1 = &enet1;
  19. serial0 = &serial0;
  20. serial1 = &serial1;
  21. pci0 = &pci0;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8378@0 {
  27. device_type = "cpu";
  28. reg = <0x0>;
  29. d-cache-line-size = <32>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <32768>;
  32. i-cache-size = <32768>;
  33. timebase-frequency = <0>;
  34. bus-frequency = <0>;
  35. clock-frequency = <0>;
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <0x00000000 0x10000000>; // 256MB at 0
  41. };
  42. localbus@e0005000 {
  43. #address-cells = <2>;
  44. #size-cells = <1>;
  45. compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
  46. reg = <0xe0005000 0x1000>;
  47. interrupts = <77 0x8>;
  48. interrupt-parent = <&ipic>;
  49. // CS0 and CS1 are swapped when
  50. // booting from nand, but the
  51. // addresses are the same.
  52. ranges = <0x0 0x0 0xfe000000 0x00800000
  53. 0x1 0x0 0xe0600000 0x00008000
  54. 0x2 0x0 0xf0000000 0x00020000
  55. 0x3 0x0 0xfa000000 0x00008000>;
  56. flash@0,0 {
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. compatible = "cfi-flash";
  60. reg = <0x0 0x0 0x800000>;
  61. bank-width = <2>;
  62. device-width = <1>;
  63. };
  64. nand@1,0 {
  65. #address-cells = <1>;
  66. #size-cells = <1>;
  67. compatible = "fsl,mpc8378-fcm-nand",
  68. "fsl,elbc-fcm-nand";
  69. reg = <0x1 0x0 0x8000>;
  70. u-boot@0 {
  71. reg = <0x0 0x100000>;
  72. read-only;
  73. };
  74. kernel@100000 {
  75. reg = <0x100000 0x300000>;
  76. };
  77. fs@400000 {
  78. reg = <0x400000 0x1c00000>;
  79. };
  80. };
  81. };
  82. immr@e0000000 {
  83. #address-cells = <1>;
  84. #size-cells = <1>;
  85. device_type = "soc";
  86. compatible = "simple-bus";
  87. ranges = <0x0 0xe0000000 0x00100000>;
  88. reg = <0xe0000000 0x00000200>;
  89. bus-frequency = <0>;
  90. wdt@200 {
  91. device_type = "watchdog";
  92. compatible = "mpc83xx_wdt";
  93. reg = <0x200 0x100>;
  94. };
  95. i2c@3000 {
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. cell-index = <0>;
  99. compatible = "fsl-i2c";
  100. reg = <0x3000 0x100>;
  101. interrupts = <14 0x8>;
  102. interrupt-parent = <&ipic>;
  103. dfsrr;
  104. rtc@68 {
  105. device_type = "rtc";
  106. compatible = "dallas,ds1339";
  107. reg = <0x68>;
  108. };
  109. };
  110. i2c@3100 {
  111. #address-cells = <1>;
  112. #size-cells = <0>;
  113. cell-index = <1>;
  114. compatible = "fsl-i2c";
  115. reg = <0x3100 0x100>;
  116. interrupts = <15 0x8>;
  117. interrupt-parent = <&ipic>;
  118. dfsrr;
  119. };
  120. spi@7000 {
  121. cell-index = <0>;
  122. compatible = "fsl,spi";
  123. reg = <0x7000 0x1000>;
  124. interrupts = <16 0x8>;
  125. interrupt-parent = <&ipic>;
  126. mode = "cpu";
  127. };
  128. dma@82a8 {
  129. #address-cells = <1>;
  130. #size-cells = <1>;
  131. compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
  132. reg = <0x82a8 4>;
  133. ranges = <0 0x8100 0x1a8>;
  134. interrupt-parent = <&ipic>;
  135. interrupts = <71 8>;
  136. cell-index = <0>;
  137. dma-channel@0 {
  138. compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
  139. reg = <0 0x80>;
  140. interrupt-parent = <&ipic>;
  141. interrupts = <71 8>;
  142. };
  143. dma-channel@80 {
  144. compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
  145. reg = <0x80 0x80>;
  146. interrupt-parent = <&ipic>;
  147. interrupts = <71 8>;
  148. };
  149. dma-channel@100 {
  150. compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
  151. reg = <0x100 0x80>;
  152. interrupt-parent = <&ipic>;
  153. interrupts = <71 8>;
  154. };
  155. dma-channel@180 {
  156. compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
  157. reg = <0x180 0x28>;
  158. interrupt-parent = <&ipic>;
  159. interrupts = <71 8>;
  160. };
  161. };
  162. usb@23000 {
  163. compatible = "fsl-usb2-dr";
  164. reg = <0x23000 0x1000>;
  165. #address-cells = <1>;
  166. #size-cells = <0>;
  167. interrupt-parent = <&ipic>;
  168. interrupts = <38 0x8>;
  169. phy_type = "ulpi";
  170. };
  171. mdio@24520 {
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. compatible = "fsl,gianfar-mdio";
  175. reg = <0x24520 0x20>;
  176. phy2: ethernet-phy@2 {
  177. interrupt-parent = <&ipic>;
  178. interrupts = <17 0x8>;
  179. reg = <0x2>;
  180. device_type = "ethernet-phy";
  181. };
  182. };
  183. enet0: ethernet@24000 {
  184. cell-index = <0>;
  185. device_type = "network";
  186. model = "eTSEC";
  187. compatible = "gianfar";
  188. reg = <0x24000 0x1000>;
  189. local-mac-address = [ 00 00 00 00 00 00 ];
  190. interrupts = <32 0x8 33 0x8 34 0x8>;
  191. phy-connection-type = "mii";
  192. interrupt-parent = <&ipic>;
  193. phy-handle = <&phy2>;
  194. };
  195. enet1: ethernet@25000 {
  196. cell-index = <1>;
  197. device_type = "network";
  198. model = "eTSEC";
  199. compatible = "gianfar";
  200. reg = <0x25000 0x1000>;
  201. local-mac-address = [ 00 00 00 00 00 00 ];
  202. interrupts = <35 0x8 36 0x8 37 0x8>;
  203. phy-connection-type = "mii";
  204. interrupt-parent = <&ipic>;
  205. fixed-link = <1 1 1000 0 0>;
  206. };
  207. serial0: serial@4500 {
  208. cell-index = <0>;
  209. device_type = "serial";
  210. compatible = "ns16550";
  211. reg = <0x4500 0x100>;
  212. clock-frequency = <0>;
  213. interrupts = <9 0x8>;
  214. interrupt-parent = <&ipic>;
  215. };
  216. serial1: serial@4600 {
  217. cell-index = <1>;
  218. device_type = "serial";
  219. compatible = "ns16550";
  220. reg = <0x4600 0x100>;
  221. clock-frequency = <0>;
  222. interrupts = <10 0x8>;
  223. interrupt-parent = <&ipic>;
  224. };
  225. crypto@30000 {
  226. compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
  227. "fsl,sec2.1", "fsl,sec2.0";
  228. reg = <0x30000 0x10000>;
  229. interrupts = <11 0x8>;
  230. interrupt-parent = <&ipic>;
  231. fsl,num-channels = <4>;
  232. fsl,channel-fifo-len = <24>;
  233. fsl,exec-units-mask = <0x9fe>;
  234. fsl,descriptor-types-mask = <0x3ab0ebf>;
  235. };
  236. /* IPIC
  237. * interrupts cell = <intr #, sense>
  238. * sense values match linux IORESOURCE_IRQ_* defines:
  239. * sense == 8: Level, low assertion
  240. * sense == 2: Edge, high-to-low change
  241. */
  242. ipic: interrupt-controller@700 {
  243. compatible = "fsl,ipic";
  244. interrupt-controller;
  245. #address-cells = <0>;
  246. #interrupt-cells = <2>;
  247. reg = <0x700 0x100>;
  248. };
  249. };
  250. pci0: pci@e0008500 {
  251. interrupt-map-mask = <0xf800 0 0 7>;
  252. interrupt-map = <
  253. /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
  254. /* IDSEL AD14 IRQ6 inta */
  255. 0x7000 0x0 0x0 0x1 &ipic 22 0x8
  256. /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
  257. 0x7800 0x0 0x0 0x1 &ipic 21 0x8
  258. 0x7800 0x0 0x0 0x2 &ipic 22 0x8
  259. 0x7800 0x0 0x0 0x4 &ipic 23 0x8
  260. /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
  261. 0xE000 0x0 0x0 0x1 &ipic 23 0x8
  262. 0xE000 0x0 0x0 0x2 &ipic 21 0x8
  263. 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
  264. interrupt-parent = <&ipic>;
  265. interrupts = <66 0x8>;
  266. bus-range = <0 0>;
  267. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  268. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  269. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
  270. clock-frequency = <66666666>;
  271. #interrupt-cells = <1>;
  272. #size-cells = <2>;
  273. #address-cells = <3>;
  274. reg = <0xe0008500 0x100>;
  275. compatible = "fsl,mpc8349-pci";
  276. device_type = "pci";
  277. };
  278. };