mpc834x_mds.dts 9.1 KB

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  1. /*
  2. * MPC8349E MDS Device Tree Source
  3. *
  4. * Copyright 2005, 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8349EMDS";
  14. compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. };
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. PowerPC,8349@0 {
  29. device_type = "cpu";
  30. reg = <0x0>;
  31. d-cache-line-size = <32>;
  32. i-cache-line-size = <32>;
  33. d-cache-size = <32768>;
  34. i-cache-size = <32768>;
  35. timebase-frequency = <0>; // from bootloader
  36. bus-frequency = <0>; // from bootloader
  37. clock-frequency = <0>; // from bootloader
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x00000000 0x10000000>; // 256MB at 0
  43. };
  44. bcsr@e2400000 {
  45. device_type = "board-control";
  46. reg = <0xe2400000 0x8000>;
  47. };
  48. soc8349@e0000000 {
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. device_type = "soc";
  52. compatible = "simple-bus";
  53. ranges = <0x0 0xe0000000 0x00100000>;
  54. reg = <0xe0000000 0x00000200>;
  55. bus-frequency = <0>;
  56. wdt@200 {
  57. device_type = "watchdog";
  58. compatible = "mpc83xx_wdt";
  59. reg = <0x200 0x100>;
  60. };
  61. i2c@3000 {
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. cell-index = <0>;
  65. compatible = "fsl-i2c";
  66. reg = <0x3000 0x100>;
  67. interrupts = <14 0x8>;
  68. interrupt-parent = <&ipic>;
  69. dfsrr;
  70. rtc@68 {
  71. compatible = "dallas,ds1374";
  72. reg = <0x68>;
  73. };
  74. };
  75. i2c@3100 {
  76. #address-cells = <1>;
  77. #size-cells = <0>;
  78. cell-index = <1>;
  79. compatible = "fsl-i2c";
  80. reg = <0x3100 0x100>;
  81. interrupts = <15 0x8>;
  82. interrupt-parent = <&ipic>;
  83. dfsrr;
  84. };
  85. spi@7000 {
  86. cell-index = <0>;
  87. compatible = "fsl,spi";
  88. reg = <0x7000 0x1000>;
  89. interrupts = <16 0x8>;
  90. interrupt-parent = <&ipic>;
  91. mode = "cpu";
  92. };
  93. dma@82a8 {
  94. #address-cells = <1>;
  95. #size-cells = <1>;
  96. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  97. reg = <0x82a8 4>;
  98. ranges = <0 0x8100 0x1a8>;
  99. interrupt-parent = <&ipic>;
  100. interrupts = <71 8>;
  101. cell-index = <0>;
  102. dma-channel@0 {
  103. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  104. reg = <0 0x80>;
  105. interrupt-parent = <&ipic>;
  106. interrupts = <71 8>;
  107. };
  108. dma-channel@80 {
  109. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  110. reg = <0x80 0x80>;
  111. interrupt-parent = <&ipic>;
  112. interrupts = <71 8>;
  113. };
  114. dma-channel@100 {
  115. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  116. reg = <0x100 0x80>;
  117. interrupt-parent = <&ipic>;
  118. interrupts = <71 8>;
  119. };
  120. dma-channel@180 {
  121. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  122. reg = <0x180 0x28>;
  123. interrupt-parent = <&ipic>;
  124. interrupts = <71 8>;
  125. };
  126. };
  127. /* phy type (ULPI or SERIAL) are only types supported for MPH */
  128. /* port = 0 or 1 */
  129. usb@22000 {
  130. compatible = "fsl-usb2-mph";
  131. reg = <0x22000 0x1000>;
  132. #address-cells = <1>;
  133. #size-cells = <0>;
  134. interrupt-parent = <&ipic>;
  135. interrupts = <39 0x8>;
  136. phy_type = "ulpi";
  137. port1;
  138. };
  139. /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
  140. usb@23000 {
  141. compatible = "fsl-usb2-dr";
  142. reg = <0x23000 0x1000>;
  143. #address-cells = <1>;
  144. #size-cells = <0>;
  145. interrupt-parent = <&ipic>;
  146. interrupts = <38 0x8>;
  147. dr_mode = "otg";
  148. phy_type = "ulpi";
  149. };
  150. mdio@24520 {
  151. #address-cells = <1>;
  152. #size-cells = <0>;
  153. compatible = "fsl,gianfar-mdio";
  154. reg = <0x24520 0x20>;
  155. phy0: ethernet-phy@0 {
  156. interrupt-parent = <&ipic>;
  157. interrupts = <17 0x8>;
  158. reg = <0x0>;
  159. device_type = "ethernet-phy";
  160. };
  161. phy1: ethernet-phy@1 {
  162. interrupt-parent = <&ipic>;
  163. interrupts = <18 0x8>;
  164. reg = <0x1>;
  165. device_type = "ethernet-phy";
  166. };
  167. };
  168. enet0: ethernet@24000 {
  169. cell-index = <0>;
  170. device_type = "network";
  171. model = "TSEC";
  172. compatible = "gianfar";
  173. reg = <0x24000 0x1000>;
  174. local-mac-address = [ 00 00 00 00 00 00 ];
  175. interrupts = <32 0x8 33 0x8 34 0x8>;
  176. interrupt-parent = <&ipic>;
  177. phy-handle = <&phy0>;
  178. linux,network-index = <0>;
  179. };
  180. enet1: ethernet@25000 {
  181. cell-index = <1>;
  182. device_type = "network";
  183. model = "TSEC";
  184. compatible = "gianfar";
  185. reg = <0x25000 0x1000>;
  186. local-mac-address = [ 00 00 00 00 00 00 ];
  187. interrupts = <35 0x8 36 0x8 37 0x8>;
  188. interrupt-parent = <&ipic>;
  189. phy-handle = <&phy1>;
  190. linux,network-index = <1>;
  191. };
  192. serial0: serial@4500 {
  193. cell-index = <0>;
  194. device_type = "serial";
  195. compatible = "ns16550";
  196. reg = <0x4500 0x100>;
  197. clock-frequency = <0>;
  198. interrupts = <9 0x8>;
  199. interrupt-parent = <&ipic>;
  200. };
  201. serial1: serial@4600 {
  202. cell-index = <1>;
  203. device_type = "serial";
  204. compatible = "ns16550";
  205. reg = <0x4600 0x100>;
  206. clock-frequency = <0>;
  207. interrupts = <10 0x8>;
  208. interrupt-parent = <&ipic>;
  209. };
  210. crypto@30000 {
  211. compatible = "fsl,sec2.0";
  212. reg = <0x30000 0x10000>;
  213. interrupts = <11 0x8>;
  214. interrupt-parent = <&ipic>;
  215. fsl,num-channels = <4>;
  216. fsl,channel-fifo-len = <24>;
  217. fsl,exec-units-mask = <0x7e>;
  218. fsl,descriptor-types-mask = <0x01010ebf>;
  219. };
  220. /* IPIC
  221. * interrupts cell = <intr #, sense>
  222. * sense values match linux IORESOURCE_IRQ_* defines:
  223. * sense == 8: Level, low assertion
  224. * sense == 2: Edge, high-to-low change
  225. */
  226. ipic: pic@700 {
  227. interrupt-controller;
  228. #address-cells = <0>;
  229. #interrupt-cells = <2>;
  230. reg = <0x700 0x100>;
  231. device_type = "ipic";
  232. };
  233. };
  234. pci0: pci@e0008500 {
  235. cell-index = <1>;
  236. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  237. interrupt-map = <
  238. /* IDSEL 0x11 */
  239. 0x8800 0x0 0x0 0x1 &ipic 20 0x8
  240. 0x8800 0x0 0x0 0x2 &ipic 21 0x8
  241. 0x8800 0x0 0x0 0x3 &ipic 22 0x8
  242. 0x8800 0x0 0x0 0x4 &ipic 23 0x8
  243. /* IDSEL 0x12 */
  244. 0x9000 0x0 0x0 0x1 &ipic 22 0x8
  245. 0x9000 0x0 0x0 0x2 &ipic 23 0x8
  246. 0x9000 0x0 0x0 0x3 &ipic 20 0x8
  247. 0x9000 0x0 0x0 0x4 &ipic 21 0x8
  248. /* IDSEL 0x13 */
  249. 0x9800 0x0 0x0 0x1 &ipic 23 0x8
  250. 0x9800 0x0 0x0 0x2 &ipic 20 0x8
  251. 0x9800 0x0 0x0 0x3 &ipic 21 0x8
  252. 0x9800 0x0 0x0 0x4 &ipic 22 0x8
  253. /* IDSEL 0x15 */
  254. 0xa800 0x0 0x0 0x1 &ipic 20 0x8
  255. 0xa800 0x0 0x0 0x2 &ipic 21 0x8
  256. 0xa800 0x0 0x0 0x3 &ipic 22 0x8
  257. 0xa800 0x0 0x0 0x4 &ipic 23 0x8
  258. /* IDSEL 0x16 */
  259. 0xb000 0x0 0x0 0x1 &ipic 23 0x8
  260. 0xb000 0x0 0x0 0x2 &ipic 20 0x8
  261. 0xb000 0x0 0x0 0x3 &ipic 21 0x8
  262. 0xb000 0x0 0x0 0x4 &ipic 22 0x8
  263. /* IDSEL 0x17 */
  264. 0xb800 0x0 0x0 0x1 &ipic 22 0x8
  265. 0xb800 0x0 0x0 0x2 &ipic 23 0x8
  266. 0xb800 0x0 0x0 0x3 &ipic 20 0x8
  267. 0xb800 0x0 0x0 0x4 &ipic 21 0x8
  268. /* IDSEL 0x18 */
  269. 0xc000 0x0 0x0 0x1 &ipic 21 0x8
  270. 0xc000 0x0 0x0 0x2 &ipic 22 0x8
  271. 0xc000 0x0 0x0 0x3 &ipic 23 0x8
  272. 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
  273. interrupt-parent = <&ipic>;
  274. interrupts = <66 0x8>;
  275. bus-range = <0 0>;
  276. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  277. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  278. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
  279. clock-frequency = <66666666>;
  280. #interrupt-cells = <1>;
  281. #size-cells = <2>;
  282. #address-cells = <3>;
  283. reg = <0xe0008500 0x100>;
  284. compatible = "fsl,mpc8349-pci";
  285. device_type = "pci";
  286. };
  287. pci1: pci@e0008600 {
  288. cell-index = <2>;
  289. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  290. interrupt-map = <
  291. /* IDSEL 0x11 */
  292. 0x8800 0x0 0x0 0x1 &ipic 20 0x8
  293. 0x8800 0x0 0x0 0x2 &ipic 21 0x8
  294. 0x8800 0x0 0x0 0x3 &ipic 22 0x8
  295. 0x8800 0x0 0x0 0x4 &ipic 23 0x8
  296. /* IDSEL 0x12 */
  297. 0x9000 0x0 0x0 0x1 &ipic 22 0x8
  298. 0x9000 0x0 0x0 0x2 &ipic 23 0x8
  299. 0x9000 0x0 0x0 0x3 &ipic 20 0x8
  300. 0x9000 0x0 0x0 0x4 &ipic 21 0x8
  301. /* IDSEL 0x13 */
  302. 0x9800 0x0 0x0 0x1 &ipic 23 0x8
  303. 0x9800 0x0 0x0 0x2 &ipic 20 0x8
  304. 0x9800 0x0 0x0 0x3 &ipic 21 0x8
  305. 0x9800 0x0 0x0 0x4 &ipic 22 0x8
  306. /* IDSEL 0x15 */
  307. 0xa800 0x0 0x0 0x1 &ipic 20 0x8
  308. 0xa800 0x0 0x0 0x2 &ipic 21 0x8
  309. 0xa800 0x0 0x0 0x3 &ipic 22 0x8
  310. 0xa800 0x0 0x0 0x4 &ipic 23 0x8
  311. /* IDSEL 0x16 */
  312. 0xb000 0x0 0x0 0x1 &ipic 23 0x8
  313. 0xb000 0x0 0x0 0x2 &ipic 20 0x8
  314. 0xb000 0x0 0x0 0x3 &ipic 21 0x8
  315. 0xb000 0x0 0x0 0x4 &ipic 22 0x8
  316. /* IDSEL 0x17 */
  317. 0xb800 0x0 0x0 0x1 &ipic 22 0x8
  318. 0xb800 0x0 0x0 0x2 &ipic 23 0x8
  319. 0xb800 0x0 0x0 0x3 &ipic 20 0x8
  320. 0xb800 0x0 0x0 0x4 &ipic 21 0x8
  321. /* IDSEL 0x18 */
  322. 0xc000 0x0 0x0 0x1 &ipic 21 0x8
  323. 0xc000 0x0 0x0 0x2 &ipic 22 0x8
  324. 0xc000 0x0 0x0 0x3 &ipic 23 0x8
  325. 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
  326. interrupt-parent = <&ipic>;
  327. interrupts = <67 0x8>;
  328. bus-range = <0 0>;
  329. ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  330. 0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  331. 0x01000000 0x0 0x00000000 0xe2100000 0x0 0x00100000>;
  332. clock-frequency = <66666666>;
  333. #interrupt-cells = <1>;
  334. #size-cells = <2>;
  335. #address-cells = <3>;
  336. reg = <0xe0008600 0x100>;
  337. compatible = "fsl,mpc8349-pci";
  338. device_type = "pci";
  339. };
  340. };