canyonlands.dts 12 KB

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  1. /*
  2. * Device Tree Source for AMCC Canyonlands (460EX)
  3. *
  4. * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without
  8. * any warranty of any kind, whether express or implied.
  9. */
  10. /dts-v1/;
  11. / {
  12. #address-cells = <2>;
  13. #size-cells = <1>;
  14. model = "amcc,canyonlands";
  15. compatible = "amcc,canyonlands";
  16. dcr-parent = <&{/cpus/cpu@0}>;
  17. aliases {
  18. ethernet0 = &EMAC0;
  19. ethernet1 = &EMAC1;
  20. serial0 = &UART0;
  21. serial1 = &UART1;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. cpu@0 {
  27. device_type = "cpu";
  28. model = "PowerPC,460EX";
  29. reg = <0x00000000>;
  30. clock-frequency = <0>; /* Filled in by U-Boot */
  31. timebase-frequency = <0>; /* Filled in by U-Boot */
  32. i-cache-line-size = <32>;
  33. d-cache-line-size = <32>;
  34. i-cache-size = <32768>;
  35. d-cache-size = <32768>;
  36. dcr-controller;
  37. dcr-access-method = "native";
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
  43. };
  44. UIC0: interrupt-controller0 {
  45. compatible = "ibm,uic-460ex","ibm,uic";
  46. interrupt-controller;
  47. cell-index = <0>;
  48. dcr-reg = <0x0c0 0x009>;
  49. #address-cells = <0>;
  50. #size-cells = <0>;
  51. #interrupt-cells = <2>;
  52. };
  53. UIC1: interrupt-controller1 {
  54. compatible = "ibm,uic-460ex","ibm,uic";
  55. interrupt-controller;
  56. cell-index = <1>;
  57. dcr-reg = <0x0d0 0x009>;
  58. #address-cells = <0>;
  59. #size-cells = <0>;
  60. #interrupt-cells = <2>;
  61. interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
  62. interrupt-parent = <&UIC0>;
  63. };
  64. UIC2: interrupt-controller2 {
  65. compatible = "ibm,uic-460ex","ibm,uic";
  66. interrupt-controller;
  67. cell-index = <2>;
  68. dcr-reg = <0x0e0 0x009>;
  69. #address-cells = <0>;
  70. #size-cells = <0>;
  71. #interrupt-cells = <2>;
  72. interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
  73. interrupt-parent = <&UIC0>;
  74. };
  75. UIC3: interrupt-controller3 {
  76. compatible = "ibm,uic-460ex","ibm,uic";
  77. interrupt-controller;
  78. cell-index = <3>;
  79. dcr-reg = <0x0f0 0x009>;
  80. #address-cells = <0>;
  81. #size-cells = <0>;
  82. #interrupt-cells = <2>;
  83. interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
  84. interrupt-parent = <&UIC0>;
  85. };
  86. SDR0: sdr {
  87. compatible = "ibm,sdr-460ex";
  88. dcr-reg = <0x00e 0x002>;
  89. };
  90. CPR0: cpr {
  91. compatible = "ibm,cpr-460ex";
  92. dcr-reg = <0x00c 0x002>;
  93. };
  94. plb {
  95. compatible = "ibm,plb-460ex", "ibm,plb4";
  96. #address-cells = <2>;
  97. #size-cells = <1>;
  98. ranges;
  99. clock-frequency = <0>; /* Filled in by U-Boot */
  100. SDRAM0: sdram {
  101. compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
  102. dcr-reg = <0x010 0x002>;
  103. };
  104. MAL0: mcmal {
  105. compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
  106. dcr-reg = <0x180 0x062>;
  107. num-tx-chans = <2>;
  108. num-rx-chans = <16>;
  109. #address-cells = <0>;
  110. #size-cells = <0>;
  111. interrupt-parent = <&UIC2>;
  112. interrupts = < /*TXEOB*/ 0x6 0x4
  113. /*RXEOB*/ 0x7 0x4
  114. /*SERR*/ 0x3 0x4
  115. /*TXDE*/ 0x4 0x4
  116. /*RXDE*/ 0x5 0x4>;
  117. };
  118. POB0: opb {
  119. compatible = "ibm,opb-460ex", "ibm,opb";
  120. #address-cells = <1>;
  121. #size-cells = <1>;
  122. ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
  123. clock-frequency = <0>; /* Filled in by U-Boot */
  124. EBC0: ebc {
  125. compatible = "ibm,ebc-460ex", "ibm,ebc";
  126. dcr-reg = <0x012 0x002>;
  127. #address-cells = <2>;
  128. #size-cells = <1>;
  129. clock-frequency = <0>; /* Filled in by U-Boot */
  130. /* ranges property is supplied by U-Boot */
  131. interrupts = <0x6 0x4>;
  132. interrupt-parent = <&UIC1>;
  133. nor_flash@0,0 {
  134. compatible = "amd,s29gl512n", "cfi-flash";
  135. bank-width = <2>;
  136. reg = <0x00000000 0x00000000 0x04000000>;
  137. #address-cells = <1>;
  138. #size-cells = <1>;
  139. partition@0 {
  140. label = "kernel";
  141. reg = <0x00000000 0x001e0000>;
  142. };
  143. partition@1e0000 {
  144. label = "dtb";
  145. reg = <0x001e0000 0x00020000>;
  146. };
  147. partition@200000 {
  148. label = "ramdisk";
  149. reg = <0x00200000 0x01400000>;
  150. };
  151. partition@1600000 {
  152. label = "jffs2";
  153. reg = <0x01600000 0x00400000>;
  154. };
  155. partition@1a00000 {
  156. label = "user";
  157. reg = <0x01a00000 0x02560000>;
  158. };
  159. partition@3f60000 {
  160. label = "env";
  161. reg = <0x03f60000 0x00040000>;
  162. };
  163. partition@3fa0000 {
  164. label = "u-boot";
  165. reg = <0x03fa0000 0x00060000>;
  166. };
  167. };
  168. };
  169. UART0: serial@ef600300 {
  170. device_type = "serial";
  171. compatible = "ns16550";
  172. reg = <0xef600300 0x00000008>;
  173. virtual-reg = <0xef600300>;
  174. clock-frequency = <0>; /* Filled in by U-Boot */
  175. current-speed = <0>; /* Filled in by U-Boot */
  176. interrupt-parent = <&UIC1>;
  177. interrupts = <0x1 0x4>;
  178. };
  179. UART1: serial@ef600400 {
  180. device_type = "serial";
  181. compatible = "ns16550";
  182. reg = <0xef600400 0x00000008>;
  183. virtual-reg = <0xef600400>;
  184. clock-frequency = <0>; /* Filled in by U-Boot */
  185. current-speed = <0>; /* Filled in by U-Boot */
  186. interrupt-parent = <&UIC0>;
  187. interrupts = <0x1 0x4>;
  188. };
  189. UART2: serial@ef600500 {
  190. device_type = "serial";
  191. compatible = "ns16550";
  192. reg = <0xef600500 0x00000008>;
  193. virtual-reg = <0xef600500>;
  194. clock-frequency = <0>; /* Filled in by U-Boot */
  195. current-speed = <0>; /* Filled in by U-Boot */
  196. interrupt-parent = <&UIC1>;
  197. interrupts = <0x1d 0x4>;
  198. };
  199. UART3: serial@ef600600 {
  200. device_type = "serial";
  201. compatible = "ns16550";
  202. reg = <0xef600600 0x00000008>;
  203. virtual-reg = <0xef600600>;
  204. clock-frequency = <0>; /* Filled in by U-Boot */
  205. current-speed = <0>; /* Filled in by U-Boot */
  206. interrupt-parent = <&UIC1>;
  207. interrupts = <0x1e 0x4>;
  208. };
  209. IIC0: i2c@ef600700 {
  210. compatible = "ibm,iic-460ex", "ibm,iic";
  211. reg = <0xef600700 0x00000014>;
  212. interrupt-parent = <&UIC0>;
  213. interrupts = <0x2 0x4>;
  214. };
  215. IIC1: i2c@ef600800 {
  216. compatible = "ibm,iic-460ex", "ibm,iic";
  217. reg = <0xef600800 0x00000014>;
  218. interrupt-parent = <&UIC0>;
  219. interrupts = <0x3 0x4>;
  220. };
  221. ZMII0: emac-zmii@ef600d00 {
  222. compatible = "ibm,zmii-460ex", "ibm,zmii";
  223. reg = <0xef600d00 0x0000000c>;
  224. };
  225. RGMII0: emac-rgmii@ef601500 {
  226. compatible = "ibm,rgmii-460ex", "ibm,rgmii";
  227. reg = <0xef601500 0x00000008>;
  228. has-mdio;
  229. };
  230. TAH0: emac-tah@ef601350 {
  231. compatible = "ibm,tah-460ex", "ibm,tah";
  232. reg = <0xef601350 0x00000030>;
  233. };
  234. TAH1: emac-tah@ef601450 {
  235. compatible = "ibm,tah-460ex", "ibm,tah";
  236. reg = <0xef601450 0x00000030>;
  237. };
  238. EMAC0: ethernet@ef600e00 {
  239. device_type = "network";
  240. compatible = "ibm,emac-460ex", "ibm,emac4sync";
  241. interrupt-parent = <&EMAC0>;
  242. interrupts = <0x0 0x1>;
  243. #interrupt-cells = <1>;
  244. #address-cells = <0>;
  245. #size-cells = <0>;
  246. interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
  247. /*Wake*/ 0x1 &UIC2 0x14 0x4>;
  248. reg = <0xef600e00 0x000000c4>;
  249. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  250. mal-device = <&MAL0>;
  251. mal-tx-channel = <0>;
  252. mal-rx-channel = <0>;
  253. cell-index = <0>;
  254. max-frame-size = <9000>;
  255. rx-fifo-size = <4096>;
  256. tx-fifo-size = <2048>;
  257. phy-mode = "rgmii";
  258. phy-map = <0x00000000>;
  259. rgmii-device = <&RGMII0>;
  260. rgmii-channel = <0>;
  261. tah-device = <&TAH0>;
  262. tah-channel = <0>;
  263. has-inverted-stacr-oc;
  264. has-new-stacr-staopc;
  265. };
  266. EMAC1: ethernet@ef600f00 {
  267. device_type = "network";
  268. compatible = "ibm,emac-460ex", "ibm,emac4sync";
  269. interrupt-parent = <&EMAC1>;
  270. interrupts = <0x0 0x1>;
  271. #interrupt-cells = <1>;
  272. #address-cells = <0>;
  273. #size-cells = <0>;
  274. interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
  275. /*Wake*/ 0x1 &UIC2 0x15 0x4>;
  276. reg = <0xef600f00 0x000000c4>;
  277. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  278. mal-device = <&MAL0>;
  279. mal-tx-channel = <1>;
  280. mal-rx-channel = <8>;
  281. cell-index = <1>;
  282. max-frame-size = <9000>;
  283. rx-fifo-size = <4096>;
  284. tx-fifo-size = <2048>;
  285. phy-mode = "rgmii";
  286. phy-map = <0x00000000>;
  287. rgmii-device = <&RGMII0>;
  288. rgmii-channel = <1>;
  289. tah-device = <&TAH1>;
  290. tah-channel = <1>;
  291. has-inverted-stacr-oc;
  292. has-new-stacr-staopc;
  293. mdio-device = <&EMAC0>;
  294. };
  295. };
  296. PCIX0: pci@c0ec00000 {
  297. device_type = "pci";
  298. #interrupt-cells = <1>;
  299. #size-cells = <2>;
  300. #address-cells = <3>;
  301. compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
  302. primary;
  303. large-inbound-windows;
  304. enable-msi-hole;
  305. reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
  306. 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
  307. 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
  308. 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
  309. 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
  310. /* Outbound ranges, one memory and one IO,
  311. * later cannot be changed
  312. */
  313. ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
  314. 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
  315. /* Inbound 2GB range starting at 0 */
  316. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
  317. /* This drives busses 0 to 0x3f */
  318. bus-range = <0x0 0x3f>;
  319. /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
  320. interrupt-map-mask = <0x0 0x0 0x0 0x0>;
  321. interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
  322. };
  323. PCIE0: pciex@d00000000 {
  324. device_type = "pci";
  325. #interrupt-cells = <1>;
  326. #size-cells = <2>;
  327. #address-cells = <3>;
  328. compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
  329. primary;
  330. port = <0x0>; /* port number */
  331. reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
  332. 0x0000000c 0x08010000 0x00001000>; /* Registers */
  333. dcr-reg = <0x100 0x020>;
  334. sdr-base = <0x300>;
  335. /* Outbound ranges, one memory and one IO,
  336. * later cannot be changed
  337. */
  338. ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
  339. 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
  340. /* Inbound 2GB range starting at 0 */
  341. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
  342. /* This drives busses 40 to 0x7f */
  343. bus-range = <0x40 0x7f>;
  344. /* Legacy interrupts (note the weird polarity, the bridge seems
  345. * to invert PCIe legacy interrupts).
  346. * We are de-swizzling here because the numbers are actually for
  347. * port of the root complex virtual P2P bridge. But I want
  348. * to avoid putting a node for it in the tree, so the numbers
  349. * below are basically de-swizzled numbers.
  350. * The real slot is on idsel 0, so the swizzling is 1:1
  351. */
  352. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  353. interrupt-map = <
  354. 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
  355. 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
  356. 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
  357. 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
  358. };
  359. PCIE1: pciex@d20000000 {
  360. device_type = "pci";
  361. #interrupt-cells = <1>;
  362. #size-cells = <2>;
  363. #address-cells = <3>;
  364. compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
  365. primary;
  366. port = <0x1>; /* port number */
  367. reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
  368. 0x0000000c 0x08011000 0x00001000>; /* Registers */
  369. dcr-reg = <0x120 0x020>;
  370. sdr-base = <0x340>;
  371. /* Outbound ranges, one memory and one IO,
  372. * later cannot be changed
  373. */
  374. ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
  375. 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
  376. /* Inbound 2GB range starting at 0 */
  377. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
  378. /* This drives busses 80 to 0xbf */
  379. bus-range = <0x80 0xbf>;
  380. /* Legacy interrupts (note the weird polarity, the bridge seems
  381. * to invert PCIe legacy interrupts).
  382. * We are de-swizzling here because the numbers are actually for
  383. * port of the root complex virtual P2P bridge. But I want
  384. * to avoid putting a node for it in the tree, so the numbers
  385. * below are basically de-swizzled numbers.
  386. * The real slot is on idsel 0, so the swizzling is 1:1
  387. */
  388. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  389. interrupt-map = <
  390. 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
  391. 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
  392. 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
  393. 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
  394. };
  395. };
  396. };