pci-asb2305.c 8.2 KB

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  1. /* ASB2305 PCI resource stuff
  2. *
  3. * Copyright (C) 2001 Red Hat, Inc. All Rights Reserved.
  4. * Written by David Howells (dhowells@redhat.com)
  5. * - Derived from arch/i386/pci-i386.c
  6. * - Copyright 1997--2000 Martin Mares <mj@suse.cz>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public Licence
  10. * as published by the Free Software Foundation; either version
  11. * 2 of the Licence, or (at your option) any later version.
  12. */
  13. #include <linux/types.h>
  14. #include <linux/kernel.h>
  15. #include <linux/pci.h>
  16. #include <linux/init.h>
  17. #include <linux/ioport.h>
  18. #include <linux/errno.h>
  19. #include "pci-asb2305.h"
  20. /*
  21. * We need to avoid collisions with `mirrored' VGA ports
  22. * and other strange ISA hardware, so we always want the
  23. * addresses to be allocated in the 0x000-0x0ff region
  24. * modulo 0x400.
  25. *
  26. * Why? Because some silly external IO cards only decode
  27. * the low 10 bits of the IO address. The 0x00-0xff region
  28. * is reserved for motherboard devices that decode all 16
  29. * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  30. * but we want to try to avoid allocating at 0x2900-0x2bff
  31. * which might have be mirrored at 0x0100-0x03ff..
  32. */
  33. void pcibios_align_resource(void *data, struct resource *res,
  34. resource_size_t size, resource_size_t align)
  35. {
  36. #if 0
  37. struct pci_dev *dev = data;
  38. printk(KERN_DEBUG
  39. "### PCIBIOS_ALIGN_RESOURCE(%s,,{%08lx-%08lx,%08lx},%lx)\n",
  40. pci_name(dev),
  41. res->start,
  42. res->end,
  43. res->flags,
  44. size
  45. );
  46. #endif
  47. if (res->flags & IORESOURCE_IO) {
  48. unsigned long start = res->start;
  49. if (start & 0x300) {
  50. start = (start + 0x3ff) & ~0x3ff;
  51. res->start = start;
  52. }
  53. }
  54. }
  55. /*
  56. * Handle resources of PCI devices. If the world were perfect, we could
  57. * just allocate all the resource regions and do nothing more. It isn't.
  58. * On the other hand, we cannot just re-allocate all devices, as it would
  59. * require us to know lots of host bridge internals. So we attempt to
  60. * keep as much of the original configuration as possible, but tweak it
  61. * when it's found to be wrong.
  62. *
  63. * Known BIOS problems we have to work around:
  64. * - I/O or memory regions not configured
  65. * - regions configured, but not enabled in the command register
  66. * - bogus I/O addresses above 64K used
  67. * - expansion ROMs left enabled (this may sound harmless, but given
  68. * the fact the PCI specs explicitly allow address decoders to be
  69. * shared between expansion ROMs and other resource regions, it's
  70. * at least dangerous)
  71. *
  72. * Our solution:
  73. * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
  74. * This gives us fixed barriers on where we can allocate.
  75. * (2) Allocate resources for all enabled devices. If there is
  76. * a collision, just mark the resource as unallocated. Also
  77. * disable expansion ROMs during this step.
  78. * (3) Try to allocate resources for disabled devices. If the
  79. * resources were assigned correctly, everything goes well,
  80. * if they weren't, they won't disturb allocation of other
  81. * resources.
  82. * (4) Assign new addresses to resources which were either
  83. * not configured at all or misconfigured. If explicitly
  84. * requested by the user, configure expansion ROM address
  85. * as well.
  86. */
  87. static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
  88. {
  89. struct pci_bus *bus;
  90. struct pci_dev *dev;
  91. int idx;
  92. struct resource *r, *pr;
  93. /* Depth-First Search on bus tree */
  94. list_for_each_entry(bus, bus_list, node) {
  95. dev = bus->self;
  96. if (dev) {
  97. for (idx = PCI_BRIDGE_RESOURCES;
  98. idx < PCI_NUM_RESOURCES;
  99. idx++) {
  100. r = &dev->resource[idx];
  101. if (!r->flags)
  102. continue;
  103. pr = pci_find_parent_resource(dev, r);
  104. if (!r->start ||
  105. !pr ||
  106. request_resource(pr, r) < 0) {
  107. printk(KERN_ERR "PCI:"
  108. " Cannot allocate resource"
  109. " region %d of bridge %s\n",
  110. idx, pci_name(dev));
  111. /* Something is wrong with the region.
  112. * Invalidate the resource to prevent
  113. * child resource allocations in this
  114. * range. */
  115. r->flags = 0;
  116. }
  117. }
  118. }
  119. pcibios_allocate_bus_resources(&bus->children);
  120. }
  121. }
  122. static void __init pcibios_allocate_resources(int pass)
  123. {
  124. struct pci_dev *dev = NULL;
  125. int idx, disabled;
  126. u16 command;
  127. struct resource *r, *pr;
  128. for_each_pci_dev(dev) {
  129. pci_read_config_word(dev, PCI_COMMAND, &command);
  130. for (idx = 0; idx < 6; idx++) {
  131. r = &dev->resource[idx];
  132. if (r->parent) /* Already allocated */
  133. continue;
  134. if (!r->start) /* Address not assigned */
  135. continue;
  136. if (r->flags & IORESOURCE_IO)
  137. disabled = !(command & PCI_COMMAND_IO);
  138. else
  139. disabled = !(command & PCI_COMMAND_MEMORY);
  140. if (pass == disabled) {
  141. DBG("PCI[%s]: Resource %08lx-%08lx"
  142. " (f=%lx, d=%d, p=%d)\n",
  143. pci_name(dev), r->start, r->end, r->flags,
  144. disabled, pass);
  145. pr = pci_find_parent_resource(dev, r);
  146. if (!pr || request_resource(pr, r) < 0) {
  147. printk(KERN_ERR "PCI:"
  148. " Cannot allocate resource"
  149. " region %d of device %s\n",
  150. idx, pci_name(dev));
  151. /* We'll assign a new address later */
  152. r->end -= r->start;
  153. r->start = 0;
  154. }
  155. }
  156. }
  157. if (!pass) {
  158. r = &dev->resource[PCI_ROM_RESOURCE];
  159. if (r->flags & IORESOURCE_ROM_ENABLE) {
  160. /* Turn the ROM off, leave the resource region,
  161. * but keep it unregistered. */
  162. u32 reg;
  163. DBG("PCI: Switching off ROM of %s\n",
  164. pci_name(dev));
  165. r->flags &= ~IORESOURCE_ROM_ENABLE;
  166. pci_read_config_dword(
  167. dev, dev->rom_base_reg, &reg);
  168. pci_write_config_dword(
  169. dev, dev->rom_base_reg,
  170. reg & ~PCI_ROM_ADDRESS_ENABLE);
  171. }
  172. }
  173. }
  174. }
  175. static int __init pcibios_assign_resources(void)
  176. {
  177. struct pci_dev *dev = NULL;
  178. struct resource *r, *pr;
  179. if (!(pci_probe & PCI_ASSIGN_ROMS)) {
  180. /* Try to use BIOS settings for ROMs, otherwise let
  181. pci_assign_unassigned_resources() allocate the new
  182. addresses. */
  183. for_each_pci_dev(dev) {
  184. r = &dev->resource[PCI_ROM_RESOURCE];
  185. if (!r->flags || !r->start)
  186. continue;
  187. pr = pci_find_parent_resource(dev, r);
  188. if (!pr || request_resource(pr, r) < 0) {
  189. r->end -= r->start;
  190. r->start = 0;
  191. }
  192. }
  193. }
  194. pci_assign_unassigned_resources();
  195. return 0;
  196. }
  197. fs_initcall(pcibios_assign_resources);
  198. void __init pcibios_resource_survey(void)
  199. {
  200. DBG("PCI: Allocating resources\n");
  201. pcibios_allocate_bus_resources(&pci_root_buses);
  202. pcibios_allocate_resources(0);
  203. pcibios_allocate_resources(1);
  204. }
  205. int pcibios_enable_resources(struct pci_dev *dev, int mask)
  206. {
  207. u16 cmd, old_cmd;
  208. int idx;
  209. struct resource *r;
  210. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  211. old_cmd = cmd;
  212. for (idx = 0; idx < 6; idx++) {
  213. /* Only set up the requested stuff */
  214. if (!(mask & (1 << idx)))
  215. continue;
  216. r = &dev->resource[idx];
  217. if (!r->start && r->end) {
  218. printk(KERN_ERR
  219. "PCI: Device %s not available because of"
  220. " resource collisions\n",
  221. pci_name(dev));
  222. return -EINVAL;
  223. }
  224. if (r->flags & IORESOURCE_IO)
  225. cmd |= PCI_COMMAND_IO;
  226. if (r->flags & IORESOURCE_MEM)
  227. cmd |= PCI_COMMAND_MEMORY;
  228. }
  229. if (dev->resource[PCI_ROM_RESOURCE].start)
  230. cmd |= PCI_COMMAND_MEMORY;
  231. if (cmd != old_cmd)
  232. pci_write_config_word(dev, PCI_COMMAND, cmd);
  233. return 0;
  234. }
  235. /*
  236. * If we set up a device for bus mastering, we need to check the latency
  237. * timer as certain crappy BIOSes forget to set it properly.
  238. */
  239. unsigned int pcibios_max_latency = 255;
  240. void pcibios_set_master(struct pci_dev *dev)
  241. {
  242. u8 lat;
  243. pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
  244. if (lat < 16)
  245. lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
  246. else if (lat > pcibios_max_latency)
  247. lat = pcibios_max_latency;
  248. else
  249. return;
  250. pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
  251. }
  252. int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
  253. enum pci_mmap_state mmap_state, int write_combine)
  254. {
  255. unsigned long prot;
  256. /* Leave vm_pgoff as-is, the PCI space address is the physical
  257. * address on this platform.
  258. */
  259. vma->vm_flags |= VM_LOCKED | VM_IO;
  260. prot = pgprot_val(vma->vm_page_prot);
  261. prot &= ~_PAGE_CACHE;
  262. vma->vm_page_prot = __pgprot(prot);
  263. /* Write-combine setting is ignored */
  264. if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  265. vma->vm_end - vma->vm_start,
  266. vma->vm_page_prot))
  267. return -EAGAIN;
  268. return 0;
  269. }