smp.c 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180
  1. #include <linux/linkage.h>
  2. #include <linux/sched.h>
  3. #include <asm/pmon.h>
  4. #include <asm/titan_dep.h>
  5. #include <asm/time.h>
  6. #define LAUNCHSTACK_SIZE 256
  7. static __cpuinitdata DEFINE_SPINLOCK(launch_lock);
  8. static unsigned long secondary_sp __cpuinitdata;
  9. static unsigned long secondary_gp __cpuinitdata;
  10. static unsigned char launchstack[LAUNCHSTACK_SIZE] __initdata
  11. __attribute__((aligned(2 * sizeof(long))));
  12. static void __init prom_smp_bootstrap(void)
  13. {
  14. local_irq_disable();
  15. while (spin_is_locked(&launch_lock));
  16. __asm__ __volatile__(
  17. " move $sp, %0 \n"
  18. " move $gp, %1 \n"
  19. " j smp_bootstrap \n"
  20. :
  21. : "r" (secondary_sp), "r" (secondary_gp));
  22. }
  23. /*
  24. * PMON is a fragile beast. It'll blow up once the mappings it's littering
  25. * right into the middle of KSEG3 are blown away so we have to grab the slave
  26. * core early and keep it in a waiting loop.
  27. */
  28. void __init prom_grab_secondary(void)
  29. {
  30. spin_lock(&launch_lock);
  31. pmon_cpustart(1, &prom_smp_bootstrap,
  32. launchstack + LAUNCHSTACK_SIZE, 0);
  33. }
  34. void titan_mailbox_irq(void)
  35. {
  36. int cpu = smp_processor_id();
  37. unsigned long status;
  38. switch (cpu) {
  39. case 0:
  40. status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
  41. OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
  42. if (status & 0x2)
  43. smp_call_function_interrupt();
  44. break;
  45. case 1:
  46. status = OCD_READ(RM9000x2_OCD_INTP1STATUS3);
  47. OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status);
  48. if (status & 0x2)
  49. smp_call_function_interrupt();
  50. break;
  51. }
  52. }
  53. /*
  54. * Send inter-processor interrupt
  55. */
  56. static void yos_send_ipi_single(int cpu, unsigned int action)
  57. {
  58. /*
  59. * Generate an INTMSG so that it can be sent over to the
  60. * destination CPU. The INTMSG will put the STATUS bits
  61. * based on the action desired. An alternative strategy
  62. * is to write to the Interrupt Set register, read the
  63. * Interrupt Status register and clear the Interrupt
  64. * Clear register. The latter is preffered.
  65. */
  66. switch (action) {
  67. case SMP_RESCHEDULE_YOURSELF:
  68. if (cpu == 1)
  69. OCD_WRITE(RM9000x2_OCD_INTP1SET3, 4);
  70. else
  71. OCD_WRITE(RM9000x2_OCD_INTP0SET3, 4);
  72. break;
  73. case SMP_CALL_FUNCTION:
  74. if (cpu == 1)
  75. OCD_WRITE(RM9000x2_OCD_INTP1SET3, 2);
  76. else
  77. OCD_WRITE(RM9000x2_OCD_INTP0SET3, 2);
  78. break;
  79. }
  80. }
  81. static void yos_send_ipi_mask(cpumask_t mask, unsigned int action)
  82. {
  83. unsigned int i;
  84. for_each_cpu_mask(i, mask)
  85. yos_send_ipi_single(i, action);
  86. }
  87. /*
  88. * After we've done initial boot, this function is called to allow the
  89. * board code to clean up state, if needed
  90. */
  91. static void __cpuinit yos_init_secondary(void)
  92. {
  93. set_c0_status(ST0_CO | ST0_IE | ST0_IM);
  94. }
  95. static void __cpuinit yos_smp_finish(void)
  96. {
  97. }
  98. /* Hook for after all CPUs are online */
  99. static void yos_cpus_done(void)
  100. {
  101. }
  102. /*
  103. * Firmware CPU startup hook
  104. * Complicated by PMON's weird interface which tries to minimic the UNIX fork.
  105. * It launches the next * available CPU and copies some information on the
  106. * stack so the first thing we do is throw away that stuff and load useful
  107. * values into the registers ...
  108. */
  109. static void __cpuinit yos_boot_secondary(int cpu, struct task_struct *idle)
  110. {
  111. unsigned long gp = (unsigned long) task_thread_info(idle);
  112. unsigned long sp = __KSTK_TOS(idle);
  113. secondary_sp = sp;
  114. secondary_gp = gp;
  115. spin_unlock(&launch_lock);
  116. }
  117. /*
  118. * Detect available CPUs, populate phys_cpu_present_map before smp_init
  119. *
  120. * We don't want to start the secondary CPU yet nor do we have a nice probing
  121. * feature in PMON so we just assume presence of the secondary core.
  122. */
  123. static void __init yos_smp_setup(void)
  124. {
  125. int i;
  126. cpus_clear(phys_cpu_present_map);
  127. for (i = 0; i < 2; i++) {
  128. cpu_set(i, phys_cpu_present_map);
  129. __cpu_number_map[i] = i;
  130. __cpu_logical_map[i] = i;
  131. }
  132. }
  133. static void __init yos_prepare_cpus(unsigned int max_cpus)
  134. {
  135. /*
  136. * Be paranoid. Enable the IPI only if we're really about to go SMP.
  137. */
  138. if (cpus_weight(cpu_possible_map))
  139. set_c0_status(STATUSF_IP5);
  140. }
  141. struct plat_smp_ops yos_smp_ops = {
  142. .send_ipi_single = yos_send_ipi_single,
  143. .send_ipi_mask = yos_send_ipi_mask,
  144. .init_secondary = yos_init_secondary,
  145. .smp_finish = yos_smp_finish,
  146. .cpus_done = yos_cpus_done,
  147. .boot_secondary = yos_boot_secondary,
  148. .smp_setup = yos_smp_setup,
  149. .prepare_cpus = yos_prepare_cpus,
  150. };