sleeper.S 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154
  1. /*
  2. * Copyright 2002 Embedded Edge, LLC
  3. * Author: dan@embeddededge.com
  4. *
  5. * Sleep helper for Au1xxx sleep mode.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. #include <asm/asm.h>
  13. #include <asm/mipsregs.h>
  14. #include <asm/regdef.h>
  15. #include <asm/stackframe.h>
  16. .text
  17. .set macro
  18. .set noat
  19. .align 5
  20. /* Save all of the processor general registers and go to sleep.
  21. * A wakeup condition will get us back here to restore the registers.
  22. */
  23. LEAF(save_and_sleep)
  24. subu sp, PT_SIZE
  25. sw $1, PT_R1(sp)
  26. sw $2, PT_R2(sp)
  27. sw $3, PT_R3(sp)
  28. sw $4, PT_R4(sp)
  29. sw $5, PT_R5(sp)
  30. sw $6, PT_R6(sp)
  31. sw $7, PT_R7(sp)
  32. sw $8, PT_R8(sp)
  33. sw $9, PT_R9(sp)
  34. sw $10, PT_R10(sp)
  35. sw $11, PT_R11(sp)
  36. sw $12, PT_R12(sp)
  37. sw $13, PT_R13(sp)
  38. sw $14, PT_R14(sp)
  39. sw $15, PT_R15(sp)
  40. sw $16, PT_R16(sp)
  41. sw $17, PT_R17(sp)
  42. sw $18, PT_R18(sp)
  43. sw $19, PT_R19(sp)
  44. sw $20, PT_R20(sp)
  45. sw $21, PT_R21(sp)
  46. sw $22, PT_R22(sp)
  47. sw $23, PT_R23(sp)
  48. sw $24, PT_R24(sp)
  49. sw $25, PT_R25(sp)
  50. sw $26, PT_R26(sp)
  51. sw $27, PT_R27(sp)
  52. sw $28, PT_R28(sp)
  53. sw $29, PT_R29(sp)
  54. sw $30, PT_R30(sp)
  55. sw $31, PT_R31(sp)
  56. mfc0 k0, CP0_STATUS
  57. sw k0, 0x20(sp)
  58. mfc0 k0, CP0_CONTEXT
  59. sw k0, 0x1c(sp)
  60. mfc0 k0, CP0_PAGEMASK
  61. sw k0, 0x18(sp)
  62. mfc0 k0, CP0_CONFIG
  63. sw k0, 0x14(sp)
  64. /* Now set up the scratch registers so the boot rom will
  65. * return to this point upon wakeup.
  66. */
  67. la k0, 1f
  68. lui k1, 0xb190
  69. ori k1, 0x18
  70. sw sp, 0(k1)
  71. ori k1, 0x1c
  72. sw k0, 0(k1)
  73. /* Put SDRAM into self refresh. Preload instructions into cache,
  74. * issue a precharge, then auto refresh, then sleep commands to it.
  75. */
  76. la t0, sdsleep
  77. .set mips3
  78. cache 0x14, 0(t0)
  79. cache 0x14, 32(t0)
  80. cache 0x14, 64(t0)
  81. cache 0x14, 96(t0)
  82. .set mips0
  83. sdsleep:
  84. lui k0, 0xb400
  85. sw zero, 0x001c(k0) /* Precharge */
  86. sw zero, 0x0020(k0) /* Auto refresh */
  87. sw zero, 0x0030(k0) /* SDRAM sleep */
  88. sync
  89. lui k1, 0xb190
  90. sw zero, 0x0078(k1) /* get ready to sleep */
  91. sync
  92. sw zero, 0x007c(k1) /* Put processor to sleep */
  93. sync
  94. /* This is where we return upon wakeup.
  95. * Reload all of the registers and return.
  96. */
  97. 1: nop
  98. lw k0, 0x20(sp)
  99. mtc0 k0, CP0_STATUS
  100. lw k0, 0x1c(sp)
  101. mtc0 k0, CP0_CONTEXT
  102. lw k0, 0x18(sp)
  103. mtc0 k0, CP0_PAGEMASK
  104. lw k0, 0x14(sp)
  105. mtc0 k0, CP0_CONFIG
  106. /* We need to catch the ealry Alchemy SOCs with
  107. * the write-only Config[OD] bit and set it back to one...
  108. */
  109. jal au1x00_fixup_config_od
  110. lw $1, PT_R1(sp)
  111. lw $2, PT_R2(sp)
  112. lw $3, PT_R3(sp)
  113. lw $4, PT_R4(sp)
  114. lw $5, PT_R5(sp)
  115. lw $6, PT_R6(sp)
  116. lw $7, PT_R7(sp)
  117. lw $8, PT_R8(sp)
  118. lw $9, PT_R9(sp)
  119. lw $10, PT_R10(sp)
  120. lw $11, PT_R11(sp)
  121. lw $12, PT_R12(sp)
  122. lw $13, PT_R13(sp)
  123. lw $14, PT_R14(sp)
  124. lw $15, PT_R15(sp)
  125. lw $16, PT_R16(sp)
  126. lw $17, PT_R17(sp)
  127. lw $18, PT_R18(sp)
  128. lw $19, PT_R19(sp)
  129. lw $20, PT_R20(sp)
  130. lw $21, PT_R21(sp)
  131. lw $22, PT_R22(sp)
  132. lw $23, PT_R23(sp)
  133. lw $24, PT_R24(sp)
  134. lw $25, PT_R25(sp)
  135. lw $26, PT_R26(sp)
  136. lw $27, PT_R27(sp)
  137. lw $28, PT_R28(sp)
  138. lw $29, PT_R29(sp)
  139. lw $30, PT_R30(sp)
  140. lw $31, PT_R31(sp)
  141. addiu sp, PT_SIZE
  142. jr ra
  143. END(save_and_sleep)