reset.c 7.1 KB

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  1. /*
  2. *
  3. * BRIEF MODULE DESCRIPTION
  4. * Au1xx0 reset routines.
  5. *
  6. * Copyright 2001, 2006, 2008 MontaVista Software Inc.
  7. * Author: MontaVista Software, Inc. <source@mvista.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. *
  14. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  15. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  16. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  17. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  20. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24. *
  25. * You should have received a copy of the GNU General Public License along
  26. * with this program; if not, write to the Free Software Foundation, Inc.,
  27. * 675 Mass Ave, Cambridge, MA 02139, USA.
  28. */
  29. #include <asm/cacheflush.h>
  30. #include <asm/mach-au1x00/au1000.h>
  31. extern int au_sleep(void);
  32. void au1000_restart(char *command)
  33. {
  34. /* Set all integrated peripherals to disabled states */
  35. extern void board_reset(void);
  36. u32 prid = read_c0_prid();
  37. printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
  38. switch (prid & 0xFF000000) {
  39. case 0x00000000: /* Au1000 */
  40. au_writel(0x02, 0xb0000010); /* ac97_enable */
  41. au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
  42. asm("sync");
  43. au_writel(0x00, 0xb017fffc); /* usbh_enable */
  44. au_writel(0x00, 0xb0200058); /* usbd_enable */
  45. au_writel(0x00, 0xb0300040); /* ir_enable */
  46. au_writel(0x00, 0xb4004104); /* mac dma */
  47. au_writel(0x00, 0xb4004114); /* mac dma */
  48. au_writel(0x00, 0xb4004124); /* mac dma */
  49. au_writel(0x00, 0xb4004134); /* mac dma */
  50. au_writel(0x00, 0xb0520000); /* macen0 */
  51. au_writel(0x00, 0xb0520004); /* macen1 */
  52. au_writel(0x00, 0xb1000008); /* i2s_enable */
  53. au_writel(0x00, 0xb1100100); /* uart0_enable */
  54. au_writel(0x00, 0xb1200100); /* uart1_enable */
  55. au_writel(0x00, 0xb1300100); /* uart2_enable */
  56. au_writel(0x00, 0xb1400100); /* uart3_enable */
  57. au_writel(0x02, 0xb1600100); /* ssi0_enable */
  58. au_writel(0x02, 0xb1680100); /* ssi1_enable */
  59. au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
  60. au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
  61. au_writel(0x00, 0xb1900028); /* sys_clksrc */
  62. au_writel(0x10, 0xb1900060); /* sys_cpupll */
  63. au_writel(0x00, 0xb1900064); /* sys_auxpll */
  64. au_writel(0x00, 0xb1900100); /* sys_pininputen */
  65. break;
  66. case 0x01000000: /* Au1500 */
  67. au_writel(0x02, 0xb0000010); /* ac97_enable */
  68. au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
  69. asm("sync");
  70. au_writel(0x00, 0xb017fffc); /* usbh_enable */
  71. au_writel(0x00, 0xb0200058); /* usbd_enable */
  72. au_writel(0x00, 0xb4004104); /* mac dma */
  73. au_writel(0x00, 0xb4004114); /* mac dma */
  74. au_writel(0x00, 0xb4004124); /* mac dma */
  75. au_writel(0x00, 0xb4004134); /* mac dma */
  76. au_writel(0x00, 0xb1520000); /* macen0 */
  77. au_writel(0x00, 0xb1520004); /* macen1 */
  78. au_writel(0x00, 0xb1100100); /* uart0_enable */
  79. au_writel(0x00, 0xb1400100); /* uart3_enable */
  80. au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
  81. au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
  82. au_writel(0x00, 0xb1900028); /* sys_clksrc */
  83. au_writel(0x10, 0xb1900060); /* sys_cpupll */
  84. au_writel(0x00, 0xb1900064); /* sys_auxpll */
  85. au_writel(0x00, 0xb1900100); /* sys_pininputen */
  86. break;
  87. case 0x02000000: /* Au1100 */
  88. au_writel(0x02, 0xb0000010); /* ac97_enable */
  89. au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
  90. asm("sync");
  91. au_writel(0x00, 0xb017fffc); /* usbh_enable */
  92. au_writel(0x00, 0xb0200058); /* usbd_enable */
  93. au_writel(0x00, 0xb0300040); /* ir_enable */
  94. au_writel(0x00, 0xb4004104); /* mac dma */
  95. au_writel(0x00, 0xb4004114); /* mac dma */
  96. au_writel(0x00, 0xb4004124); /* mac dma */
  97. au_writel(0x00, 0xb4004134); /* mac dma */
  98. au_writel(0x00, 0xb0520000); /* macen0 */
  99. au_writel(0x00, 0xb1000008); /* i2s_enable */
  100. au_writel(0x00, 0xb1100100); /* uart0_enable */
  101. au_writel(0x00, 0xb1200100); /* uart1_enable */
  102. au_writel(0x00, 0xb1400100); /* uart3_enable */
  103. au_writel(0x02, 0xb1600100); /* ssi0_enable */
  104. au_writel(0x02, 0xb1680100); /* ssi1_enable */
  105. au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
  106. au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
  107. au_writel(0x00, 0xb1900028); /* sys_clksrc */
  108. au_writel(0x10, 0xb1900060); /* sys_cpupll */
  109. au_writel(0x00, 0xb1900064); /* sys_auxpll */
  110. au_writel(0x00, 0xb1900100); /* sys_pininputen */
  111. break;
  112. case 0x03000000: /* Au1550 */
  113. au_writel(0x00, 0xb1a00004); /* psc 0 */
  114. au_writel(0x00, 0xb1b00004); /* psc 1 */
  115. au_writel(0x00, 0xb0a00004); /* psc 2 */
  116. au_writel(0x00, 0xb0b00004); /* psc 3 */
  117. au_writel(0x00, 0xb017fffc); /* usbh_enable */
  118. au_writel(0x00, 0xb0200058); /* usbd_enable */
  119. au_writel(0x00, 0xb4004104); /* mac dma */
  120. au_writel(0x00, 0xb4004114); /* mac dma */
  121. au_writel(0x00, 0xb4004124); /* mac dma */
  122. au_writel(0x00, 0xb4004134); /* mac dma */
  123. au_writel(0x00, 0xb1520000); /* macen0 */
  124. au_writel(0x00, 0xb1520004); /* macen1 */
  125. au_writel(0x00, 0xb1100100); /* uart0_enable */
  126. au_writel(0x00, 0xb1200100); /* uart1_enable */
  127. au_writel(0x00, 0xb1400100); /* uart3_enable */
  128. au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
  129. au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
  130. au_writel(0x00, 0xb1900028); /* sys_clksrc */
  131. au_writel(0x10, 0xb1900060); /* sys_cpupll */
  132. au_writel(0x00, 0xb1900064); /* sys_auxpll */
  133. au_writel(0x00, 0xb1900100); /* sys_pininputen */
  134. break;
  135. }
  136. set_c0_status(ST0_BEV | ST0_ERL);
  137. change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
  138. flush_cache_all();
  139. write_c0_wired(0);
  140. /* Give board a chance to do a hardware reset */
  141. board_reset();
  142. /* Jump to the beggining in case board_reset() is empty */
  143. __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
  144. }
  145. void au1000_halt(void)
  146. {
  147. #if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
  148. /* Power off system */
  149. printk(KERN_NOTICE "\n** Powering off...\n");
  150. au_writew(au_readw(0xAF00001C) | (3 << 14), 0xAF00001C);
  151. au_sync();
  152. while (1); /* should not get here */
  153. #else
  154. printk(KERN_NOTICE "\n** You can safely turn off the power\n");
  155. #ifdef CONFIG_MIPS_MIRAGE
  156. au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
  157. #endif
  158. #ifdef CONFIG_MIPS_DB1200
  159. au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C);
  160. #endif
  161. #ifdef CONFIG_PM
  162. au_sleep();
  163. /* Should not get here */
  164. printk(KERN_ERR "Unable to put CPU in sleep mode\n");
  165. while (1);
  166. #else
  167. while (1)
  168. __asm__(".set\tmips3\n\t"
  169. "wait\n\t"
  170. ".set\tmips0");
  171. #endif
  172. #endif /* defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) */
  173. }
  174. void au1000_power_off(void)
  175. {
  176. au1000_halt();
  177. }