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arch
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blackfin
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mach-bf561
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include
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mach
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mem_map.h

mem_map.h 2.0 KB
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  1. /*
    2. 

  2.  * Memory MAP
    3. 

  3.  * Common header file for blackfin BF561 of processors.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef _MEM_MAP_561_H_
    7. 

  7. #define _MEM_MAP_561_H_
    8. 

  8. 

  9. #define COREMMR_BASE           0xFFE00000	 /* Core MMRs */
    10. 

  10. #define SYSMMR_BASE            0xFFC00000	 /* System MMRs */
    11. 

  11. 

  12. /* Async Memory Banks */
    13. 

  13. #define ASYNC_BANK3_BASE	0x2C000000	 /* Async Bank 3 */
    14. 

  14. #define ASYNC_BANK3_SIZE	0x04000000	/* 64M */
    15. 

  15. #define ASYNC_BANK2_BASE	0x28000000	 /* Async Bank 2 */
    16. 

  16. #define ASYNC_BANK2_SIZE	0x04000000	/* 64M */
    17. 

  17. #define ASYNC_BANK1_BASE	0x24000000	 /* Async Bank 1 */
    18. 

  18. #define ASYNC_BANK1_SIZE	0x04000000	/* 64M */
    19. 

  19. #define ASYNC_BANK0_BASE	0x20000000	 /* Async Bank 0 */
    20. 

  20. #define ASYNC_BANK0_SIZE	0x04000000	/* 64M */
    21. 

  21. 

  22. /* Boot ROM Memory */
    23. 

  23. 

  24. #define BOOT_ROM_START		0xEF000000
    25. 

  25. #define BOOT_ROM_LENGTH		0x800
    26. 

  26. 

  27. /* Level 1 Memory */
    28. 

  28. 

  29. #ifdef CONFIG_BFIN_ICACHE
    30. 

  30. #define BFIN_ICACHESIZE	(16*1024)
    31. 

  31. #else
    32. 

  32. #define BFIN_ICACHESIZE	(0*1024)
    33. 

  33. #endif
    34. 

  34. 

  35. /* Memory Map for ADSP-BF561 processors */
    36. 

  36. 

  37. #ifdef CONFIG_BF561
    38. 

  38. #define L1_CODE_START     0xFFA00000
    39. 

  39. #define L1_DATA_A_START     0xFF800000
    40. 

  40. #define L1_DATA_B_START     0xFF900000
    41. 

  41. 

  42. #define L1_CODE_LENGTH      0x4000
    43. 

  43. 

  44. #ifdef CONFIG_BFIN_DCACHE
    45. 

  45. 

  46. #ifdef CONFIG_BFIN_DCACHE_BANKA
    47. 

  47. #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
    48. 

  48. #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
    49. 

  49. #define L1_DATA_B_LENGTH      0x8000
    50. 

  50. #define BFIN_DCACHESIZE	(16*1024)
    51. 

  51. #define BFIN_DSUPBANKS	1
    52. 

  52. #else
    53. 

  53. #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
    54. 

  54. #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
    55. 

  55. #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
    56. 

  56. #define BFIN_DCACHESIZE	(32*1024)
    57. 

  57. #define BFIN_DSUPBANKS	2
    58. 

  58. #endif
    59. 

  59. 

  60. #else
    61. 

  61. #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
    62. 

  62. #define L1_DATA_A_LENGTH      0x8000
    63. 

  63. #define L1_DATA_B_LENGTH      0x8000
    64. 

  64. #define BFIN_DCACHESIZE	(0*1024)
    65. 

  65. #define BFIN_DSUPBANKS	0
    66. 

  66. #endif /*CONFIG_BFIN_DCACHE*/
    67. 

  67. #endif
    68. 

  68. 

  69. /* Level 2 Memory */
    70. 

  70. #define L2_START		0xFEB00000
    71. 

  71. #define L2_LENGTH		0x20000
    72. 

  72. 

  73. /* Scratch Pad Memory */
    74. 

  74. 

  75. #define L1_SCRATCH_START	0xFFB00000
    76. 

  76. #define L1_SCRATCH_LENGTH	0x1000
    77. 

  77. 

  78. #endif				/* _MEM_MAP_533_H_ */
    79.