cm_bf533.c 9.9 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf533/boards/cm_bf533.c
  3. * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
  4. * Author: Aidan Williams <aidan@nicta.com.au> Copyright 2005
  5. *
  6. * Created: 2005
  7. * Description: Board description file
  8. *
  9. * Modified:
  10. * Copyright 2004-2006 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #include <linux/device.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/mtd/mtd.h>
  32. #include <linux/mtd/partitions.h>
  33. #include <linux/spi/spi.h>
  34. #include <linux/spi/flash.h>
  35. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  36. #include <linux/usb/isp1362.h>
  37. #endif
  38. #include <linux/irq.h>
  39. #include <asm/dma.h>
  40. #include <asm/bfin5xx_spi.h>
  41. #include <asm/portmux.h>
  42. #include <asm/dpmc.h>
  43. /*
  44. * Name the Board for the /proc/cpuinfo
  45. */
  46. const char bfin_board_name[] = "Bluetechnix CM BF533";
  47. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  48. /* all SPI peripherals info goes here */
  49. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  50. static struct mtd_partition bfin_spi_flash_partitions[] = {
  51. {
  52. .name = "bootloader(spi)",
  53. .size = 0x00020000,
  54. .offset = 0,
  55. .mask_flags = MTD_CAP_ROM
  56. }, {
  57. .name = "linux kernel(spi)",
  58. .size = 0xe0000,
  59. .offset = 0x20000
  60. }, {
  61. .name = "file system(spi)",
  62. .size = 0x700000,
  63. .offset = 0x00100000,
  64. }
  65. };
  66. static struct flash_platform_data bfin_spi_flash_data = {
  67. .name = "m25p80",
  68. .parts = bfin_spi_flash_partitions,
  69. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  70. .type = "m25p64",
  71. };
  72. /* SPI flash chip (m25p64) */
  73. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  74. .enable_dma = 0, /* use dma transfer with this chip*/
  75. .bits_per_word = 8,
  76. };
  77. #endif
  78. /* SPI ADC chip */
  79. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  80. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  81. .enable_dma = 1, /* use dma transfer with this chip*/
  82. .bits_per_word = 16,
  83. };
  84. #endif
  85. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  86. static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
  87. .enable_dma = 0,
  88. .bits_per_word = 16,
  89. };
  90. #endif
  91. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  92. static struct bfin5xx_spi_chip spi_mmc_chip_info = {
  93. .enable_dma = 1,
  94. .bits_per_word = 8,
  95. };
  96. #endif
  97. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  98. #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
  99. {
  100. /* the modalias must be the same as spi device driver name */
  101. .modalias = "m25p80", /* Name of spi_driver for this device */
  102. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  103. .bus_num = 0, /* Framework bus number */
  104. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  105. .platform_data = &bfin_spi_flash_data,
  106. .controller_data = &spi_flash_chip_info,
  107. .mode = SPI_MODE_3,
  108. },
  109. #endif
  110. #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
  111. {
  112. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  113. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  114. .bus_num = 0, /* Framework bus number */
  115. .chip_select = 2, /* Framework chip select. */
  116. .platform_data = NULL, /* No spi_driver specific config */
  117. .controller_data = &spi_adc_chip_info,
  118. },
  119. #endif
  120. #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
  121. {
  122. .modalias = "ad1836-spi",
  123. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  124. .bus_num = 0,
  125. .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
  126. .controller_data = &ad1836_spi_chip_info,
  127. },
  128. #endif
  129. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  130. {
  131. .modalias = "spi_mmc_dummy",
  132. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  133. .bus_num = 0,
  134. .chip_select = 0,
  135. .platform_data = NULL,
  136. .controller_data = &spi_mmc_chip_info,
  137. .mode = SPI_MODE_3,
  138. },
  139. {
  140. .modalias = "spi_mmc",
  141. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  142. .bus_num = 0,
  143. .chip_select = CONFIG_SPI_MMC_CS_CHAN,
  144. .platform_data = NULL,
  145. .controller_data = &spi_mmc_chip_info,
  146. .mode = SPI_MODE_3,
  147. },
  148. #endif
  149. };
  150. /* SPI (0) */
  151. static struct resource bfin_spi0_resource[] = {
  152. [0] = {
  153. .start = SPI0_REGBASE,
  154. .end = SPI0_REGBASE + 0xFF,
  155. .flags = IORESOURCE_MEM,
  156. },
  157. [1] = {
  158. .start = CH_SPI,
  159. .end = CH_SPI,
  160. .flags = IORESOURCE_IRQ,
  161. }
  162. };
  163. /* SPI controller data */
  164. static struct bfin5xx_spi_master bfin_spi0_info = {
  165. .num_chipselect = 8,
  166. .enable_dma = 1, /* master has the ability to do dma transfer */
  167. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  168. };
  169. static struct platform_device bfin_spi0_device = {
  170. .name = "bfin-spi",
  171. .id = 0, /* Bus number */
  172. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  173. .resource = bfin_spi0_resource,
  174. .dev = {
  175. .platform_data = &bfin_spi0_info, /* Passed to driver */
  176. },
  177. };
  178. #endif /* spi master and devices */
  179. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  180. static struct platform_device rtc_device = {
  181. .name = "rtc-bfin",
  182. .id = -1,
  183. };
  184. #endif
  185. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  186. static struct resource smc91x_resources[] = {
  187. {
  188. .start = 0x20200300,
  189. .end = 0x20200300 + 16,
  190. .flags = IORESOURCE_MEM,
  191. }, {
  192. .start = IRQ_PF0,
  193. .end = IRQ_PF0,
  194. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  195. },
  196. };
  197. static struct platform_device smc91x_device = {
  198. .name = "smc91x",
  199. .id = 0,
  200. .num_resources = ARRAY_SIZE(smc91x_resources),
  201. .resource = smc91x_resources,
  202. };
  203. #endif
  204. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  205. static struct resource bfin_uart_resources[] = {
  206. {
  207. .start = 0xFFC00400,
  208. .end = 0xFFC004FF,
  209. .flags = IORESOURCE_MEM,
  210. },
  211. };
  212. static struct platform_device bfin_uart_device = {
  213. .name = "bfin-uart",
  214. .id = 1,
  215. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  216. .resource = bfin_uart_resources,
  217. };
  218. #endif
  219. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  220. static struct resource bfin_sir_resources[] = {
  221. #ifdef CONFIG_BFIN_SIR0
  222. {
  223. .start = 0xFFC00400,
  224. .end = 0xFFC004FF,
  225. .flags = IORESOURCE_MEM,
  226. },
  227. #endif
  228. };
  229. static struct platform_device bfin_sir_device = {
  230. .name = "bfin_sir",
  231. .id = 0,
  232. .num_resources = ARRAY_SIZE(bfin_sir_resources),
  233. .resource = bfin_sir_resources,
  234. };
  235. #endif
  236. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  237. static struct platform_device bfin_sport0_uart_device = {
  238. .name = "bfin-sport-uart",
  239. .id = 0,
  240. };
  241. static struct platform_device bfin_sport1_uart_device = {
  242. .name = "bfin-sport-uart",
  243. .id = 1,
  244. };
  245. #endif
  246. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  247. static struct resource isp1362_hcd_resources[] = {
  248. {
  249. .start = 0x20308000,
  250. .end = 0x20308000,
  251. .flags = IORESOURCE_MEM,
  252. }, {
  253. .start = 0x20308004,
  254. .end = 0x20308004,
  255. .flags = IORESOURCE_MEM,
  256. }, {
  257. .start = IRQ_PF4,
  258. .end = IRQ_PF4,
  259. .flags = IORESOURCE_IRQ,
  260. },
  261. };
  262. static struct isp1362_platform_data isp1362_priv = {
  263. .sel15Kres = 1,
  264. .clknotstop = 0,
  265. .oc_enable = 0,
  266. .int_act_high = 0,
  267. .int_edge_triggered = 0,
  268. .remote_wakeup_connected = 0,
  269. .no_power_switching = 1,
  270. .power_switching_mode = 0,
  271. };
  272. static struct platform_device isp1362_hcd_device = {
  273. .name = "isp1362-hcd",
  274. .id = 0,
  275. .dev = {
  276. .platform_data = &isp1362_priv,
  277. },
  278. .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
  279. .resource = isp1362_hcd_resources,
  280. };
  281. #endif
  282. static const unsigned int cclk_vlev_datasheet[] =
  283. {
  284. VRPAIR(VLEV_085, 250000000),
  285. VRPAIR(VLEV_090, 376000000),
  286. VRPAIR(VLEV_095, 426000000),
  287. VRPAIR(VLEV_100, 426000000),
  288. VRPAIR(VLEV_105, 476000000),
  289. VRPAIR(VLEV_110, 476000000),
  290. VRPAIR(VLEV_115, 476000000),
  291. VRPAIR(VLEV_120, 600000000),
  292. VRPAIR(VLEV_125, 600000000),
  293. VRPAIR(VLEV_130, 600000000),
  294. };
  295. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  296. .tuple_tab = cclk_vlev_datasheet,
  297. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  298. .vr_settling_time = 25 /* us */,
  299. };
  300. static struct platform_device bfin_dpmc = {
  301. .name = "bfin dpmc",
  302. .dev = {
  303. .platform_data = &bfin_dmpc_vreg_data,
  304. },
  305. };
  306. static struct platform_device *cm_bf533_devices[] __initdata = {
  307. &bfin_dpmc,
  308. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  309. &bfin_uart_device,
  310. #endif
  311. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  312. &bfin_sir_device,
  313. #endif
  314. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  315. &bfin_sport0_uart_device,
  316. &bfin_sport1_uart_device,
  317. #endif
  318. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  319. &rtc_device,
  320. #endif
  321. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  322. &isp1362_hcd_device,
  323. #endif
  324. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  325. &smc91x_device,
  326. #endif
  327. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  328. &bfin_spi0_device,
  329. #endif
  330. };
  331. static int __init cm_bf533_init(void)
  332. {
  333. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  334. platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
  335. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  336. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  337. #endif
  338. return 0;
  339. }
  340. arch_initcall(cm_bf533_init);