bfin_serial_5xx.h 5.6 KB

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  1. /*
  2. * file: include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
  3. * based on:
  4. * author:
  5. *
  6. * created:
  7. * description:
  8. * blackfin serial driver head file
  9. * rev:
  10. *
  11. * modified:
  12. *
  13. *
  14. * bugs: enter bugs at http://blackfin.uclinux.org/
  15. *
  16. * this program is free software; you can redistribute it and/or modify
  17. * it under the terms of the gnu general public license as published by
  18. * the free software foundation; either version 2, or (at your option)
  19. * any later version.
  20. *
  21. * this program is distributed in the hope that it will be useful,
  22. * but without any warranty; without even the implied warranty of
  23. * merchantability or fitness for a particular purpose. see the
  24. * gnu general public license for more details.
  25. *
  26. * you should have received a copy of the gnu general public license
  27. * along with this program; see the file copying.
  28. * if not, write to the free software foundation,
  29. * 59 temple place - suite 330, boston, ma 02111-1307, usa.
  30. */
  31. #include <linux/serial.h>
  32. #include <asm/dma.h>
  33. #include <asm/portmux.h>
  34. #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
  35. #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
  36. #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
  37. #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
  38. #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
  39. #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
  40. #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  41. #define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
  42. #define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
  43. #define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
  44. #define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
  45. #define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
  46. #define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
  47. #define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
  48. #define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
  49. #define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
  50. #define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
  51. #define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
  52. #define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
  53. #define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
  54. #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
  55. #define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
  56. #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
  57. # define CONFIG_SERIAL_BFIN_CTSRTS
  58. # ifndef CONFIG_UART0_CTS_PIN
  59. # define CONFIG_UART0_CTS_PIN -1
  60. # endif
  61. # ifndef CONFIG_UART0_RTS_PIN
  62. # define CONFIG_UART0_RTS_PIN -1
  63. # endif
  64. # ifndef CONFIG_UART1_CTS_PIN
  65. # define CONFIG_UART1_CTS_PIN -1
  66. # endif
  67. # ifndef CONFIG_UART1_RTS_PIN
  68. # define CONFIG_UART1_RTS_PIN -1
  69. # endif
  70. #endif
  71. /*
  72. * The pin configuration is different from schematic
  73. */
  74. struct bfin_serial_port {
  75. struct uart_port port;
  76. unsigned int old_status;
  77. unsigned int lsr;
  78. #ifdef CONFIG_SERIAL_BFIN_DMA
  79. int tx_done;
  80. int tx_count;
  81. struct circ_buf rx_dma_buf;
  82. struct timer_list rx_dma_timer;
  83. int rx_dma_nrows;
  84. unsigned int tx_dma_channel;
  85. unsigned int rx_dma_channel;
  86. struct work_struct tx_dma_workqueue;
  87. #endif
  88. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  89. struct timer_list cts_timer;
  90. int cts_pin;
  91. int rts_pin;
  92. #endif
  93. };
  94. /* The hardware clears the LSR bits upon read, so we need to cache
  95. * some of the more fun bits in software so they don't get lost
  96. * when checking the LSR in other code paths (TX).
  97. */
  98. static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
  99. {
  100. unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
  101. uart->lsr |= (lsr & (BI|FE|PE|OE));
  102. return lsr | uart->lsr;
  103. }
  104. static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
  105. {
  106. uart->lsr = 0;
  107. bfin_write16(uart->port.membase + OFFSET_LSR, -1);
  108. }
  109. struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
  110. struct bfin_serial_res {
  111. unsigned long uart_base_addr;
  112. int uart_irq;
  113. #ifdef CONFIG_SERIAL_BFIN_DMA
  114. unsigned int uart_tx_dma_channel;
  115. unsigned int uart_rx_dma_channel;
  116. #endif
  117. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  118. int uart_cts_pin;
  119. int uart_rts_pin;
  120. #endif
  121. };
  122. struct bfin_serial_res bfin_serial_resource[] = {
  123. #ifdef CONFIG_SERIAL_BFIN_UART0
  124. {
  125. 0xFFC00400,
  126. IRQ_UART0_RX,
  127. #ifdef CONFIG_SERIAL_BFIN_DMA
  128. CH_UART0_TX,
  129. CH_UART0_RX,
  130. #endif
  131. #ifdef CONFIG_BFIN_UART0_CTSRTS
  132. CONFIG_UART0_CTS_PIN,
  133. CONFIG_UART0_RTS_PIN,
  134. #endif
  135. },
  136. #endif
  137. #ifdef CONFIG_SERIAL_BFIN_UART1
  138. {
  139. 0xFFC02000,
  140. IRQ_UART1_RX,
  141. #ifdef CONFIG_SERIAL_BFIN_DMA
  142. CH_UART1_TX,
  143. CH_UART1_RX,
  144. #endif
  145. #ifdef CONFIG_BFIN_UART1_CTSRTS
  146. CONFIG_UART1_CTS_PIN,
  147. CONFIG_UART1_RTS_PIN,
  148. #endif
  149. },
  150. #endif
  151. };
  152. int nr_ports = ARRAY_SIZE(bfin_serial_resource);
  153. #define DRIVER_NAME "bfin-uart"
  154. static void bfin_serial_hw_init(struct bfin_serial_port *uart)
  155. {
  156. #ifdef CONFIG_SERIAL_BFIN_UART0
  157. peripheral_request(P_UART0_TX, DRIVER_NAME);
  158. peripheral_request(P_UART0_RX, DRIVER_NAME);
  159. #endif
  160. #ifdef CONFIG_SERIAL_BFIN_UART1
  161. peripheral_request(P_UART1_TX, DRIVER_NAME);
  162. peripheral_request(P_UART1_RX, DRIVER_NAME);
  163. #endif
  164. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  165. if (uart->cts_pin >= 0) {
  166. gpio_request(uart->cts_pin, DRIVER_NAME);
  167. gpio_direction_input(uart->cts_pin);
  168. }
  169. if (uart->rts_pin >= 0) {
  170. gpio_request(uart->rts_pin, DRIVER_NAME);
  171. gpio_direction_output(uart->rts_pin, 0);
  172. }
  173. #endif
  174. }