Kconfig 23 KB

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  1. #
  2. # For a description of the syntax of this configuration file,
  3. # see Documentation/kbuild/kconfig-language.txt.
  4. #
  5. mainmenu "Blackfin Kernel Configuration"
  6. config MMU
  7. bool
  8. default n
  9. config FPU
  10. bool
  11. default n
  12. config RWSEM_GENERIC_SPINLOCK
  13. bool
  14. default y
  15. config RWSEM_XCHGADD_ALGORITHM
  16. bool
  17. default n
  18. config BLACKFIN
  19. bool
  20. default y
  21. select HAVE_IDE
  22. select HAVE_OPROFILE
  23. config ZONE_DMA
  24. bool
  25. default y
  26. config GENERIC_FIND_NEXT_BIT
  27. bool
  28. default y
  29. config GENERIC_HWEIGHT
  30. bool
  31. default y
  32. config GENERIC_HARDIRQS
  33. bool
  34. default y
  35. config GENERIC_IRQ_PROBE
  36. bool
  37. default y
  38. config GENERIC_GPIO
  39. bool
  40. default y
  41. config FORCE_MAX_ZONEORDER
  42. int
  43. default "14"
  44. config GENERIC_CALIBRATE_DELAY
  45. bool
  46. default y
  47. config HARDWARE_PM
  48. def_bool y
  49. depends on OPROFILE
  50. source "init/Kconfig"
  51. source "kernel/Kconfig.preempt"
  52. menu "Blackfin Processor Options"
  53. comment "Processor and Board Settings"
  54. choice
  55. prompt "CPU"
  56. default BF533
  57. config BF522
  58. bool "BF522"
  59. help
  60. BF522 Processor Support.
  61. config BF523
  62. bool "BF523"
  63. help
  64. BF523 Processor Support.
  65. config BF524
  66. bool "BF524"
  67. help
  68. BF524 Processor Support.
  69. config BF525
  70. bool "BF525"
  71. help
  72. BF525 Processor Support.
  73. config BF526
  74. bool "BF526"
  75. help
  76. BF526 Processor Support.
  77. config BF527
  78. bool "BF527"
  79. help
  80. BF527 Processor Support.
  81. config BF531
  82. bool "BF531"
  83. help
  84. BF531 Processor Support.
  85. config BF532
  86. bool "BF532"
  87. help
  88. BF532 Processor Support.
  89. config BF533
  90. bool "BF533"
  91. help
  92. BF533 Processor Support.
  93. config BF534
  94. bool "BF534"
  95. help
  96. BF534 Processor Support.
  97. config BF536
  98. bool "BF536"
  99. help
  100. BF536 Processor Support.
  101. config BF537
  102. bool "BF537"
  103. help
  104. BF537 Processor Support.
  105. config BF542
  106. bool "BF542"
  107. help
  108. BF542 Processor Support.
  109. config BF544
  110. bool "BF544"
  111. help
  112. BF544 Processor Support.
  113. config BF547
  114. bool "BF547"
  115. help
  116. BF547 Processor Support.
  117. config BF548
  118. bool "BF548"
  119. help
  120. BF548 Processor Support.
  121. config BF549
  122. bool "BF549"
  123. help
  124. BF549 Processor Support.
  125. config BF561
  126. bool "BF561"
  127. help
  128. Not Supported Yet - Work in progress - BF561 Processor Support.
  129. endchoice
  130. choice
  131. prompt "Silicon Rev"
  132. default BF_REV_0_1 if BF527
  133. default BF_REV_0_2 if BF537
  134. default BF_REV_0_3 if BF533
  135. default BF_REV_0_0 if BF549
  136. config BF_REV_0_0
  137. bool "0.0"
  138. depends on (BF52x || BF54x)
  139. config BF_REV_0_1
  140. bool "0.1"
  141. depends on (BF52x || BF54x)
  142. config BF_REV_0_2
  143. bool "0.2"
  144. depends on (BF537 || BF536 || BF534)
  145. config BF_REV_0_3
  146. bool "0.3"
  147. depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  148. config BF_REV_0_4
  149. bool "0.4"
  150. depends on (BF561 || BF533 || BF532 || BF531)
  151. config BF_REV_0_5
  152. bool "0.5"
  153. depends on (BF561 || BF533 || BF532 || BF531)
  154. config BF_REV_ANY
  155. bool "any"
  156. config BF_REV_NONE
  157. bool "none"
  158. endchoice
  159. config BF52x
  160. bool
  161. depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
  162. default y
  163. config BF53x
  164. bool
  165. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  166. default y
  167. config BF54x
  168. bool
  169. depends on (BF542 || BF544 || BF547 || BF548 || BF549)
  170. default y
  171. config MEM_GENERIC_BOARD
  172. bool
  173. depends on GENERIC_BOARD
  174. default y
  175. config MEM_MT48LC64M4A2FB_7E
  176. bool
  177. depends on (BFIN533_STAMP)
  178. default y
  179. config MEM_MT48LC16M16A2TG_75
  180. bool
  181. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  182. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
  183. || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
  184. default y
  185. config MEM_MT48LC32M8A2_75
  186. bool
  187. depends on (BFIN537_STAMP || PNAV10)
  188. default y
  189. config MEM_MT48LC8M32B2B5_7
  190. bool
  191. depends on (BFIN561_BLUETECHNIX_CM)
  192. default y
  193. config MEM_MT48LC32M16A2TG_75
  194. bool
  195. depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
  196. default y
  197. source "arch/blackfin/mach-bf527/Kconfig"
  198. source "arch/blackfin/mach-bf533/Kconfig"
  199. source "arch/blackfin/mach-bf561/Kconfig"
  200. source "arch/blackfin/mach-bf537/Kconfig"
  201. source "arch/blackfin/mach-bf548/Kconfig"
  202. menu "Board customizations"
  203. config CMDLINE_BOOL
  204. bool "Default bootloader kernel arguments"
  205. config CMDLINE
  206. string "Initial kernel command string"
  207. depends on CMDLINE_BOOL
  208. default "console=ttyBF0,57600"
  209. help
  210. If you don't have a boot loader capable of passing a command line string
  211. to the kernel, you may specify one here. As a minimum, you should specify
  212. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  213. config BOOT_LOAD
  214. hex "Kernel load address for booting"
  215. default "0x1000"
  216. range 0x1000 0x20000000
  217. help
  218. This option allows you to set the load address of the kernel.
  219. This can be useful if you are on a board which has a small amount
  220. of memory or you wish to reserve some memory at the beginning of
  221. the address space.
  222. Note that you need to keep this value above 4k (0x1000) as this
  223. memory region is used to capture NULL pointer references as well
  224. as some core kernel functions.
  225. comment "Clock/PLL Setup"
  226. config CLKIN_HZ
  227. int "Frequency of the crystal on the board in Hz"
  228. default "11059200" if BFIN533_STAMP
  229. default "27000000" if BFIN533_EZKIT
  230. default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP)
  231. default "30000000" if BFIN561_EZKIT
  232. default "24576000" if PNAV10
  233. default "10000000" if BFIN532_IP0X
  234. help
  235. The frequency of CLKIN crystal oscillator on the board in Hz.
  236. Warning: This value should match the crystal on the board. Otherwise,
  237. peripherals won't work properly.
  238. config BFIN_KERNEL_CLOCK
  239. bool "Re-program Clocks while Kernel boots?"
  240. default n
  241. help
  242. This option decides if kernel clocks are re-programed from the
  243. bootloader settings. If the clocks are not set, the SDRAM settings
  244. are also not changed, and the Bootloader does 100% of the hardware
  245. configuration.
  246. config PLL_BYPASS
  247. bool "Bypass PLL"
  248. depends on BFIN_KERNEL_CLOCK
  249. default n
  250. config CLKIN_HALF
  251. bool "Half Clock In"
  252. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  253. default n
  254. help
  255. If this is set the clock will be divided by 2, before it goes to the PLL.
  256. config VCO_MULT
  257. int "VCO Multiplier"
  258. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  259. range 1 64
  260. default "22" if BFIN533_EZKIT
  261. default "45" if BFIN533_STAMP
  262. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
  263. default "22" if BFIN533_BLUETECHNIX_CM
  264. default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
  265. default "20" if BFIN561_EZKIT
  266. default "16" if (H8606_HVSISTEMAS || BLACKSTAMP)
  267. help
  268. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  269. PLL Frequency = (Crystal Frequency) * (this setting)
  270. choice
  271. prompt "Core Clock Divider"
  272. depends on BFIN_KERNEL_CLOCK
  273. default CCLK_DIV_1
  274. help
  275. This sets the frequency of the core. It can be 1, 2, 4 or 8
  276. Core Frequency = (PLL frequency) / (this setting)
  277. config CCLK_DIV_1
  278. bool "1"
  279. config CCLK_DIV_2
  280. bool "2"
  281. config CCLK_DIV_4
  282. bool "4"
  283. config CCLK_DIV_8
  284. bool "8"
  285. endchoice
  286. config SCLK_DIV
  287. int "System Clock Divider"
  288. depends on BFIN_KERNEL_CLOCK
  289. range 1 15
  290. default 5
  291. help
  292. This sets the frequency of the system clock (including SDRAM or DDR).
  293. This can be between 1 and 15
  294. System Clock = (PLL frequency) / (this setting)
  295. config MAX_MEM_SIZE
  296. int "Max SDRAM Memory Size in MBytes"
  297. depends on !MPU
  298. default 512
  299. help
  300. This is the max memory size that the kernel will create CPLB
  301. tables for. Your system will not be able to handle any more.
  302. choice
  303. prompt "DDR SDRAM Chip Type"
  304. depends on BFIN_KERNEL_CLOCK
  305. depends on BF54x
  306. default MEM_MT46V32M16_5B
  307. config MEM_MT46V32M16_6T
  308. bool "MT46V32M16_6T"
  309. config MEM_MT46V32M16_5B
  310. bool "MT46V32M16_5B"
  311. endchoice
  312. #
  313. # Max & Min Speeds for various Chips
  314. #
  315. config MAX_VCO_HZ
  316. int
  317. default 600000000 if BF522
  318. default 400000000 if BF523
  319. default 400000000 if BF524
  320. default 600000000 if BF525
  321. default 400000000 if BF526
  322. default 600000000 if BF527
  323. default 400000000 if BF531
  324. default 400000000 if BF532
  325. default 750000000 if BF533
  326. default 500000000 if BF534
  327. default 400000000 if BF536
  328. default 600000000 if BF537
  329. default 533333333 if BF538
  330. default 533333333 if BF539
  331. default 600000000 if BF542
  332. default 533333333 if BF544
  333. default 600000000 if BF547
  334. default 600000000 if BF548
  335. default 533333333 if BF549
  336. default 600000000 if BF561
  337. config MIN_VCO_HZ
  338. int
  339. default 50000000
  340. config MAX_SCLK_HZ
  341. int
  342. default 133333333
  343. config MIN_SCLK_HZ
  344. int
  345. default 27000000
  346. comment "Kernel Timer/Scheduler"
  347. source kernel/Kconfig.hz
  348. config GENERIC_TIME
  349. bool "Generic time"
  350. default y
  351. config GENERIC_CLOCKEVENTS
  352. bool "Generic clock events"
  353. depends on GENERIC_TIME
  354. default y
  355. config CYCLES_CLOCKSOURCE
  356. bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
  357. depends on EXPERIMENTAL
  358. depends on GENERIC_CLOCKEVENTS
  359. depends on !BFIN_SCRATCH_REG_CYCLES
  360. default n
  361. help
  362. If you say Y here, you will enable support for using the 'cycles'
  363. registers as a clock source. Doing so means you will be unable to
  364. safely write to the 'cycles' register during runtime. You will
  365. still be able to read it (such as for performance monitoring), but
  366. writing the registers will most likely crash the kernel.
  367. source kernel/time/Kconfig
  368. comment "Memory Setup"
  369. comment "Misc"
  370. choice
  371. prompt "Blackfin Exception Scratch Register"
  372. default BFIN_SCRATCH_REG_RETN
  373. help
  374. Select the resource to reserve for the Exception handler:
  375. - RETN: Non-Maskable Interrupt (NMI)
  376. - RETE: Exception Return (JTAG/ICE)
  377. - CYCLES: Performance counter
  378. If you are unsure, please select "RETN".
  379. config BFIN_SCRATCH_REG_RETN
  380. bool "RETN"
  381. help
  382. Use the RETN register in the Blackfin exception handler
  383. as a stack scratch register. This means you cannot
  384. safely use NMI on the Blackfin while running Linux, but
  385. you can debug the system with a JTAG ICE and use the
  386. CYCLES performance registers.
  387. If you are unsure, please select "RETN".
  388. config BFIN_SCRATCH_REG_RETE
  389. bool "RETE"
  390. help
  391. Use the RETE register in the Blackfin exception handler
  392. as a stack scratch register. This means you cannot
  393. safely use a JTAG ICE while debugging a Blackfin board,
  394. but you can safely use the CYCLES performance registers
  395. and the NMI.
  396. If you are unsure, please select "RETN".
  397. config BFIN_SCRATCH_REG_CYCLES
  398. bool "CYCLES"
  399. help
  400. Use the CYCLES register in the Blackfin exception handler
  401. as a stack scratch register. This means you cannot
  402. safely use the CYCLES performance registers on a Blackfin
  403. board at anytime, but you can debug the system with a JTAG
  404. ICE and use the NMI.
  405. If you are unsure, please select "RETN".
  406. endchoice
  407. endmenu
  408. menu "Blackfin Kernel Optimizations"
  409. comment "Memory Optimizations"
  410. config I_ENTRY_L1
  411. bool "Locate interrupt entry code in L1 Memory"
  412. default y
  413. help
  414. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  415. into L1 instruction memory. (less latency)
  416. config EXCPT_IRQ_SYSC_L1
  417. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  418. default y
  419. help
  420. If enabled, the entire ASM lowlevel exception and interrupt entry code
  421. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  422. (less latency)
  423. config DO_IRQ_L1
  424. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  425. default y
  426. help
  427. If enabled, the frequently called do_irq dispatcher function is linked
  428. into L1 instruction memory. (less latency)
  429. config CORE_TIMER_IRQ_L1
  430. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  431. default y
  432. help
  433. If enabled, the frequently called timer_interrupt() function is linked
  434. into L1 instruction memory. (less latency)
  435. config IDLE_L1
  436. bool "Locate frequently idle function in L1 Memory"
  437. default y
  438. help
  439. If enabled, the frequently called idle function is linked
  440. into L1 instruction memory. (less latency)
  441. config SCHEDULE_L1
  442. bool "Locate kernel schedule function in L1 Memory"
  443. default y
  444. help
  445. If enabled, the frequently called kernel schedule is linked
  446. into L1 instruction memory. (less latency)
  447. config ARITHMETIC_OPS_L1
  448. bool "Locate kernel owned arithmetic functions in L1 Memory"
  449. default y
  450. help
  451. If enabled, arithmetic functions are linked
  452. into L1 instruction memory. (less latency)
  453. config ACCESS_OK_L1
  454. bool "Locate access_ok function in L1 Memory"
  455. default y
  456. help
  457. If enabled, the access_ok function is linked
  458. into L1 instruction memory. (less latency)
  459. config MEMSET_L1
  460. bool "Locate memset function in L1 Memory"
  461. default y
  462. help
  463. If enabled, the memset function is linked
  464. into L1 instruction memory. (less latency)
  465. config MEMCPY_L1
  466. bool "Locate memcpy function in L1 Memory"
  467. default y
  468. help
  469. If enabled, the memcpy function is linked
  470. into L1 instruction memory. (less latency)
  471. config SYS_BFIN_SPINLOCK_L1
  472. bool "Locate sys_bfin_spinlock function in L1 Memory"
  473. default y
  474. help
  475. If enabled, sys_bfin_spinlock function is linked
  476. into L1 instruction memory. (less latency)
  477. config IP_CHECKSUM_L1
  478. bool "Locate IP Checksum function in L1 Memory"
  479. default n
  480. help
  481. If enabled, the IP Checksum function is linked
  482. into L1 instruction memory. (less latency)
  483. config CACHELINE_ALIGNED_L1
  484. bool "Locate cacheline_aligned data to L1 Data Memory"
  485. default y if !BF54x
  486. default n if BF54x
  487. depends on !BF531
  488. help
  489. If enabled, cacheline_anligned data is linked
  490. into L1 data memory. (less latency)
  491. config SYSCALL_TAB_L1
  492. bool "Locate Syscall Table L1 Data Memory"
  493. default n
  494. depends on !BF531
  495. help
  496. If enabled, the Syscall LUT is linked
  497. into L1 data memory. (less latency)
  498. config CPLB_SWITCH_TAB_L1
  499. bool "Locate CPLB Switch Tables L1 Data Memory"
  500. default n
  501. depends on !BF531
  502. help
  503. If enabled, the CPLB Switch Tables are linked
  504. into L1 data memory. (less latency)
  505. comment "Speed Optimizations"
  506. config BFIN_INS_LOWOVERHEAD
  507. bool "ins[bwl] low overhead, higher interrupt latency"
  508. default y
  509. help
  510. Reads on the Blackfin are speculative. In Blackfin terms, this means
  511. they can be interrupted at any time (even after they have been issued
  512. on to the external bus), and re-issued after the interrupt occurs.
  513. For memory - this is not a big deal, since memory does not change if
  514. it sees a read.
  515. If a FIFO is sitting on the end of the read, it will see two reads,
  516. when the core only sees one since the FIFO receives both the read
  517. which is cancelled (and not delivered to the core) and the one which
  518. is re-issued (which is delivered to the core).
  519. To solve this, interrupts are turned off before reads occur to
  520. I/O space. This option controls which the overhead/latency of
  521. controlling interrupts during this time
  522. "n" turns interrupts off every read
  523. (higher overhead, but lower interrupt latency)
  524. "y" turns interrupts off every loop
  525. (low overhead, but longer interrupt latency)
  526. default behavior is to leave this set to on (type "Y"). If you are experiencing
  527. interrupt latency issues, it is safe and OK to turn this off.
  528. endmenu
  529. choice
  530. prompt "Kernel executes from"
  531. help
  532. Choose the memory type that the kernel will be running in.
  533. config RAMKERNEL
  534. bool "RAM"
  535. help
  536. The kernel will be resident in RAM when running.
  537. config ROMKERNEL
  538. bool "ROM"
  539. help
  540. The kernel will be resident in FLASH/ROM when running.
  541. endchoice
  542. source "mm/Kconfig"
  543. config BFIN_GPTIMERS
  544. tristate "Enable Blackfin General Purpose Timers API"
  545. default n
  546. help
  547. Enable support for the General Purpose Timers API. If you
  548. are unsure, say N.
  549. To compile this driver as a module, choose M here: the module
  550. will be called gptimers.ko.
  551. config BFIN_DMA_5XX
  552. bool "Enable DMA Support"
  553. depends on (BF52x || BF53x || BF561 || BF54x)
  554. default y
  555. help
  556. DMA driver for BF5xx.
  557. choice
  558. prompt "Uncached SDRAM region"
  559. default DMA_UNCACHED_1M
  560. depends on BFIN_DMA_5XX
  561. config DMA_UNCACHED_4M
  562. bool "Enable 4M DMA region"
  563. config DMA_UNCACHED_2M
  564. bool "Enable 2M DMA region"
  565. config DMA_UNCACHED_1M
  566. bool "Enable 1M DMA region"
  567. config DMA_UNCACHED_NONE
  568. bool "Disable DMA region"
  569. endchoice
  570. comment "Cache Support"
  571. config BFIN_ICACHE
  572. bool "Enable ICACHE"
  573. config BFIN_DCACHE
  574. bool "Enable DCACHE"
  575. config BFIN_DCACHE_BANKA
  576. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  577. depends on BFIN_DCACHE && !BF531
  578. default n
  579. config BFIN_ICACHE_LOCK
  580. bool "Enable Instruction Cache Locking"
  581. choice
  582. prompt "Policy"
  583. depends on BFIN_DCACHE
  584. default BFIN_WB
  585. config BFIN_WB
  586. bool "Write back"
  587. help
  588. Write Back Policy:
  589. Cached data will be written back to SDRAM only when needed.
  590. This can give a nice increase in performance, but beware of
  591. broken drivers that do not properly invalidate/flush their
  592. cache.
  593. Write Through Policy:
  594. Cached data will always be written back to SDRAM when the
  595. cache is updated. This is a completely safe setting, but
  596. performance is worse than Write Back.
  597. If you are unsure of the options and you want to be safe,
  598. then go with Write Through.
  599. config BFIN_WT
  600. bool "Write through"
  601. help
  602. Write Back Policy:
  603. Cached data will be written back to SDRAM only when needed.
  604. This can give a nice increase in performance, but beware of
  605. broken drivers that do not properly invalidate/flush their
  606. cache.
  607. Write Through Policy:
  608. Cached data will always be written back to SDRAM when the
  609. cache is updated. This is a completely safe setting, but
  610. performance is worse than Write Back.
  611. If you are unsure of the options and you want to be safe,
  612. then go with Write Through.
  613. endchoice
  614. config MPU
  615. bool "Enable the memory protection unit (EXPERIMENTAL)"
  616. default n
  617. help
  618. Use the processor's MPU to protect applications from accessing
  619. memory they do not own. This comes at a performance penalty
  620. and is recommended only for debugging.
  621. comment "Asynchonous Memory Configuration"
  622. menu "EBIU_AMGCTL Global Control"
  623. config C_AMCKEN
  624. bool "Enable CLKOUT"
  625. default y
  626. config C_CDPRIO
  627. bool "DMA has priority over core for ext. accesses"
  628. default n
  629. config C_B0PEN
  630. depends on BF561
  631. bool "Bank 0 16 bit packing enable"
  632. default y
  633. config C_B1PEN
  634. depends on BF561
  635. bool "Bank 1 16 bit packing enable"
  636. default y
  637. config C_B2PEN
  638. depends on BF561
  639. bool "Bank 2 16 bit packing enable"
  640. default y
  641. config C_B3PEN
  642. depends on BF561
  643. bool "Bank 3 16 bit packing enable"
  644. default n
  645. choice
  646. prompt"Enable Asynchonous Memory Banks"
  647. default C_AMBEN_ALL
  648. config C_AMBEN
  649. bool "Disable All Banks"
  650. config C_AMBEN_B0
  651. bool "Enable Bank 0"
  652. config C_AMBEN_B0_B1
  653. bool "Enable Bank 0 & 1"
  654. config C_AMBEN_B0_B1_B2
  655. bool "Enable Bank 0 & 1 & 2"
  656. config C_AMBEN_ALL
  657. bool "Enable All Banks"
  658. endchoice
  659. endmenu
  660. menu "EBIU_AMBCTL Control"
  661. config BANK_0
  662. hex "Bank 0"
  663. default 0x7BB0
  664. config BANK_1
  665. hex "Bank 1"
  666. default 0x7BB0
  667. default 0x5558 if BF54x
  668. config BANK_2
  669. hex "Bank 2"
  670. default 0x7BB0
  671. config BANK_3
  672. hex "Bank 3"
  673. default 0x99B3
  674. endmenu
  675. config EBIU_MBSCTLVAL
  676. hex "EBIU Bank Select Control Register"
  677. depends on BF54x
  678. default 0
  679. config EBIU_MODEVAL
  680. hex "Flash Memory Mode Control Register"
  681. depends on BF54x
  682. default 1
  683. config EBIU_FCTLVAL
  684. hex "Flash Memory Bank Control Register"
  685. depends on BF54x
  686. default 6
  687. endmenu
  688. #############################################################################
  689. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  690. config PCI
  691. bool "PCI support"
  692. depends on BROKEN
  693. help
  694. Support for PCI bus.
  695. source "drivers/pci/Kconfig"
  696. config HOTPLUG
  697. bool "Support for hot-pluggable device"
  698. help
  699. Say Y here if you want to plug devices into your computer while
  700. the system is running, and be able to use them quickly. In many
  701. cases, the devices can likewise be unplugged at any time too.
  702. One well known example of this is PCMCIA- or PC-cards, credit-card
  703. size devices such as network cards, modems or hard drives which are
  704. plugged into slots found on all modern laptop computers. Another
  705. example, used on modern desktops as well as laptops, is USB.
  706. Enable HOTPLUG and build a modular kernel. Get agent software
  707. (from <http://linux-hotplug.sourceforge.net/>) and install it.
  708. Then your kernel will automatically call out to a user mode "policy
  709. agent" (/sbin/hotplug) to load modules and set up software needed
  710. to use devices as you hotplug them.
  711. source "drivers/pcmcia/Kconfig"
  712. source "drivers/pci/hotplug/Kconfig"
  713. endmenu
  714. menu "Executable file formats"
  715. source "fs/Kconfig.binfmt"
  716. endmenu
  717. menu "Power management options"
  718. source "kernel/power/Kconfig"
  719. config ARCH_SUSPEND_POSSIBLE
  720. def_bool y
  721. depends on !SMP
  722. choice
  723. prompt "Standby Power Saving Mode"
  724. depends on PM
  725. default PM_BFIN_SLEEP_DEEPER
  726. config PM_BFIN_SLEEP_DEEPER
  727. bool "Sleep Deeper"
  728. help
  729. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  730. power dissipation by disabling the clock to the processor core (CCLK).
  731. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  732. to 0.85 V to provide the greatest power savings, while preserving the
  733. processor state.
  734. The PLL and system clock (SCLK) continue to operate at a very low
  735. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  736. the SDRAM is put into Self Refresh Mode. Typically an external event
  737. such as GPIO interrupt or RTC activity wakes up the processor.
  738. Various Peripherals such as UART, SPORT, PPI may not function as
  739. normal during Sleep Deeper, due to the reduced SCLK frequency.
  740. When in the sleep mode, system DMA access to L1 memory is not supported.
  741. If unsure, select "Sleep Deeper".
  742. config PM_BFIN_SLEEP
  743. bool "Sleep"
  744. help
  745. Sleep Mode (High Power Savings) - The sleep mode reduces power
  746. dissipation by disabling the clock to the processor core (CCLK).
  747. The PLL and system clock (SCLK), however, continue to operate in
  748. this mode. Typically an external event or RTC activity will wake
  749. up the processor. When in the sleep mode, system DMA access to L1
  750. memory is not supported.
  751. If unsure, select "Sleep Deeper".
  752. endchoice
  753. config PM_WAKEUP_BY_GPIO
  754. bool "Allow Wakeup from Standby by GPIO"
  755. config PM_WAKEUP_GPIO_NUMBER
  756. int "GPIO number"
  757. range 0 47
  758. depends on PM_WAKEUP_BY_GPIO
  759. default 2 if BFIN537_STAMP
  760. choice
  761. prompt "GPIO Polarity"
  762. depends on PM_WAKEUP_BY_GPIO
  763. default PM_WAKEUP_GPIO_POLAR_H
  764. config PM_WAKEUP_GPIO_POLAR_H
  765. bool "Active High"
  766. config PM_WAKEUP_GPIO_POLAR_L
  767. bool "Active Low"
  768. config PM_WAKEUP_GPIO_POLAR_EDGE_F
  769. bool "Falling EDGE"
  770. config PM_WAKEUP_GPIO_POLAR_EDGE_R
  771. bool "Rising EDGE"
  772. config PM_WAKEUP_GPIO_POLAR_EDGE_B
  773. bool "Both EDGE"
  774. endchoice
  775. comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  776. depends on PM
  777. config PM_BFIN_WAKE_PH6
  778. bool "Allow Wake-Up from on-chip PHY or PH6 GP"
  779. depends on PM && (BF52x || BF534 || BF536 || BF537)
  780. default n
  781. help
  782. Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
  783. config PM_BFIN_WAKE_GP
  784. bool "Allow Wake-Up from GPIOs"
  785. depends on PM && BF54x
  786. default n
  787. help
  788. Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
  789. endmenu
  790. menu "CPU Frequency scaling"
  791. source "drivers/cpufreq/Kconfig"
  792. config CPU_VOLTAGE
  793. bool "CPU Voltage scaling"
  794. depends on EXPERIMENTAL
  795. depends on CPU_FREQ
  796. default n
  797. help
  798. Say Y here if you want CPU voltage scaling according to the CPU frequency.
  799. This option violates the PLL BYPASS recommendation in the Blackfin Processor
  800. manuals. There is a theoretical risk that during VDDINT transitions
  801. the PLL may unlock.
  802. endmenu
  803. source "net/Kconfig"
  804. source "drivers/Kconfig"
  805. source "fs/Kconfig"
  806. source "arch/blackfin/Kconfig.debug"
  807. source "security/Kconfig"
  808. source "crypto/Kconfig"
  809. source "lib/Kconfig"