dma.c 4.9 KB

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  1. /* linux/arch/arm/mach-s3c2443/dma.c
  2. *
  3. * Copyright (c) 2007 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2443 DMA selection
  7. *
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/sysdev.h>
  17. #include <linux/serial_core.h>
  18. #include <linux/io.h>
  19. #include <asm/dma.h>
  20. #include <mach/dma.h>
  21. #include <asm/plat-s3c24xx/dma.h>
  22. #include <asm/plat-s3c24xx/cpu.h>
  23. #include <asm/plat-s3c/regs-serial.h>
  24. #include <mach/regs-gpio.h>
  25. #include <asm/plat-s3c/regs-ac97.h>
  26. #include <mach/regs-mem.h>
  27. #include <mach/regs-lcd.h>
  28. #include <mach/regs-sdi.h>
  29. #include <asm/plat-s3c24xx/regs-iis.h>
  30. #include <asm/plat-s3c24xx/regs-spi.h>
  31. #define MAP(x) { \
  32. [0] = (x) | DMA_CH_VALID, \
  33. [1] = (x) | DMA_CH_VALID, \
  34. [2] = (x) | DMA_CH_VALID, \
  35. [3] = (x) | DMA_CH_VALID, \
  36. [4] = (x) | DMA_CH_VALID, \
  37. [5] = (x) | DMA_CH_VALID, \
  38. }
  39. static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
  40. [DMACH_XD0] = {
  41. .name = "xdreq0",
  42. .channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
  43. },
  44. [DMACH_XD1] = {
  45. .name = "xdreq1",
  46. .channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
  47. },
  48. [DMACH_SDI] = {
  49. .name = "sdi",
  50. .channels = MAP(S3C2443_DMAREQSEL_SDI),
  51. .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
  52. .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
  53. },
  54. [DMACH_SPI0] = {
  55. .name = "spi0",
  56. .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
  57. .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
  58. .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
  59. },
  60. [DMACH_SPI1] = {
  61. .name = "spi1",
  62. .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
  63. .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
  64. .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
  65. },
  66. [DMACH_UART0] = {
  67. .name = "uart0",
  68. .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
  69. .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
  70. .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
  71. },
  72. [DMACH_UART1] = {
  73. .name = "uart1",
  74. .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
  75. .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
  76. .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
  77. },
  78. [DMACH_UART2] = {
  79. .name = "uart2",
  80. .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
  81. .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
  82. .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
  83. },
  84. [DMACH_UART3] = {
  85. .name = "uart3",
  86. .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
  87. .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
  88. .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
  89. },
  90. [DMACH_UART0_SRC2] = {
  91. .name = "uart0",
  92. .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
  93. .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
  94. .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
  95. },
  96. [DMACH_UART1_SRC2] = {
  97. .name = "uart1",
  98. .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
  99. .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
  100. .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
  101. },
  102. [DMACH_UART2_SRC2] = {
  103. .name = "uart2",
  104. .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
  105. .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
  106. .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
  107. },
  108. [DMACH_UART3_SRC2] = {
  109. .name = "uart3",
  110. .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
  111. .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
  112. .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
  113. },
  114. [DMACH_TIMER] = {
  115. .name = "timer",
  116. .channels = MAP(S3C2443_DMAREQSEL_TIMER),
  117. },
  118. [DMACH_I2S_IN] = {
  119. .name = "i2s-sdi",
  120. .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
  121. .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
  122. },
  123. [DMACH_I2S_OUT] = {
  124. .name = "i2s-sdo",
  125. .channels = MAP(S3C2443_DMAREQSEL_I2STX),
  126. .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
  127. },
  128. [DMACH_PCM_IN] = {
  129. .name = "pcm-in",
  130. .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
  131. .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
  132. },
  133. [DMACH_PCM_OUT] = {
  134. .name = "pcm-out",
  135. .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
  136. .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
  137. },
  138. [DMACH_MIC_IN] = {
  139. .name = "mic-in",
  140. .channels = MAP(S3C2443_DMAREQSEL_MICIN),
  141. .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
  142. },
  143. };
  144. static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
  145. struct s3c24xx_dma_map *map)
  146. {
  147. writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
  148. chan->regs + S3C2443_DMA_DMAREQSEL);
  149. }
  150. static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
  151. .select = s3c2443_dma_select,
  152. .dcon_mask = 0,
  153. .map = s3c2443_dma_mappings,
  154. .map_size = ARRAY_SIZE(s3c2443_dma_mappings),
  155. };
  156. static int __init s3c2443_dma_add(struct sys_device *sysdev)
  157. {
  158. s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
  159. return s3c24xx_dma_init_map(&s3c2443_dma_sel);
  160. }
  161. static struct sysdev_driver s3c2443_dma_driver = {
  162. .add = s3c2443_dma_add,
  163. };
  164. static int __init s3c2443_dma_init(void)
  165. {
  166. return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_dma_driver);
  167. }
  168. arch_initcall(s3c2443_dma_init);