mach-qt2410.c 8.0 KB

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  1. /* linux/arch/arm/mach-s3c2410/mach-qt2410.c
  2. *
  3. * Copyright (C) 2006 by OpenMoko, Inc.
  4. * Author: Harald Welte <laforge@openmoko.org>
  5. * All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/types.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/list.h>
  27. #include <linux/timer.h>
  28. #include <linux/init.h>
  29. #include <linux/sysdev.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/serial_core.h>
  32. #include <linux/spi/spi.h>
  33. #include <linux/spi/spi_bitbang.h>
  34. #include <linux/io.h>
  35. #include <linux/mtd/mtd.h>
  36. #include <linux/mtd/nand.h>
  37. #include <linux/mtd/nand_ecc.h>
  38. #include <linux/mtd/partitions.h>
  39. #include <asm/mach/arch.h>
  40. #include <asm/mach/map.h>
  41. #include <asm/mach/irq.h>
  42. #include <mach/hardware.h>
  43. #include <asm/irq.h>
  44. #include <asm/mach-types.h>
  45. #include <mach/regs-gpio.h>
  46. #include <mach/leds-gpio.h>
  47. #include <asm/plat-s3c/regs-serial.h>
  48. #include <mach/fb.h>
  49. #include <asm/plat-s3c/nand.h>
  50. #include <asm/plat-s3c24xx/udc.h>
  51. #include <mach/spi.h>
  52. #include <mach/spi-gpio.h>
  53. #include <asm/plat-s3c24xx/common-smdk.h>
  54. #include <asm/plat-s3c24xx/devs.h>
  55. #include <asm/plat-s3c24xx/cpu.h>
  56. #include <asm/plat-s3c24xx/pm.h>
  57. static struct map_desc qt2410_iodesc[] __initdata = {
  58. { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
  59. };
  60. #define UCON S3C2410_UCON_DEFAULT
  61. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  62. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  63. static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
  64. [0] = {
  65. .hwport = 0,
  66. .flags = 0,
  67. .ucon = UCON,
  68. .ulcon = ULCON,
  69. .ufcon = UFCON,
  70. },
  71. [1] = {
  72. .hwport = 1,
  73. .flags = 0,
  74. .ucon = UCON,
  75. .ulcon = ULCON,
  76. .ufcon = UFCON,
  77. },
  78. [2] = {
  79. .hwport = 2,
  80. .flags = 0,
  81. .ucon = UCON,
  82. .ulcon = ULCON,
  83. .ufcon = UFCON,
  84. }
  85. };
  86. /* LCD driver info */
  87. static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
  88. {
  89. /* Configuration for 640x480 SHARP LQ080V3DG01 */
  90. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  91. S3C2410_LCDCON5_INVVLINE |
  92. S3C2410_LCDCON5_INVVFRAME |
  93. S3C2410_LCDCON5_PWREN |
  94. S3C2410_LCDCON5_HWSWP,
  95. .type = S3C2410_LCDCON1_TFT,
  96. .width = 640,
  97. .height = 480,
  98. .pixclock = 40000, /* HCLK/4 */
  99. .xres = 640,
  100. .yres = 480,
  101. .bpp = 16,
  102. .left_margin = 44,
  103. .right_margin = 116,
  104. .hsync_len = 96,
  105. .upper_margin = 19,
  106. .lower_margin = 11,
  107. .vsync_len = 15,
  108. },
  109. {
  110. /* Configuration for 480x640 toppoly TD028TTEC1 */
  111. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  112. S3C2410_LCDCON5_INVVLINE |
  113. S3C2410_LCDCON5_INVVFRAME |
  114. S3C2410_LCDCON5_PWREN |
  115. S3C2410_LCDCON5_HWSWP,
  116. .type = S3C2410_LCDCON1_TFT,
  117. .width = 480,
  118. .height = 640,
  119. .pixclock = 40000, /* HCLK/4 */
  120. .xres = 480,
  121. .yres = 640,
  122. .bpp = 16,
  123. .left_margin = 8,
  124. .right_margin = 24,
  125. .hsync_len = 8,
  126. .upper_margin = 2,
  127. .lower_margin = 4,
  128. .vsync_len = 2,
  129. },
  130. {
  131. /* Config for 240x320 LCD */
  132. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  133. S3C2410_LCDCON5_INVVLINE |
  134. S3C2410_LCDCON5_INVVFRAME |
  135. S3C2410_LCDCON5_PWREN |
  136. S3C2410_LCDCON5_HWSWP,
  137. .type = S3C2410_LCDCON1_TFT,
  138. .width = 240,
  139. .height = 320,
  140. .pixclock = 100000, /* HCLK/10 */
  141. .xres = 240,
  142. .yres = 320,
  143. .bpp = 16,
  144. .left_margin = 13,
  145. .right_margin = 8,
  146. .hsync_len = 4,
  147. .upper_margin = 2,
  148. .lower_margin = 7,
  149. .vsync_len = 4,
  150. },
  151. };
  152. static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
  153. .displays = qt2410_lcd_cfg,
  154. .num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
  155. .default_display = 0,
  156. .lpcsel = ((0xCE6) & ~7) | 1<<4,
  157. };
  158. /* CS8900 */
  159. static struct resource qt2410_cs89x0_resources[] = {
  160. [0] = {
  161. .start = 0x19000000,
  162. .end = 0x19000000 + 16,
  163. .flags = IORESOURCE_MEM,
  164. },
  165. [1] = {
  166. .start = IRQ_EINT9,
  167. .end = IRQ_EINT9,
  168. .flags = IORESOURCE_IRQ,
  169. },
  170. };
  171. static struct platform_device qt2410_cs89x0 = {
  172. .name = "cirrus-cs89x0",
  173. .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
  174. .resource = qt2410_cs89x0_resources,
  175. };
  176. /* LED */
  177. static struct s3c24xx_led_platdata qt2410_pdata_led = {
  178. .gpio = S3C2410_GPB0,
  179. .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
  180. .name = "led",
  181. .def_trigger = "timer",
  182. };
  183. static struct platform_device qt2410_led = {
  184. .name = "s3c24xx_led",
  185. .id = 0,
  186. .dev = {
  187. .platform_data = &qt2410_pdata_led,
  188. },
  189. };
  190. /* SPI */
  191. static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
  192. {
  193. switch (cs) {
  194. case BITBANG_CS_ACTIVE:
  195. s3c2410_gpio_setpin(S3C2410_GPB5, 0);
  196. break;
  197. case BITBANG_CS_INACTIVE:
  198. s3c2410_gpio_setpin(S3C2410_GPB5, 1);
  199. break;
  200. }
  201. }
  202. static struct s3c2410_spigpio_info spi_gpio_cfg = {
  203. .pin_clk = S3C2410_GPG7,
  204. .pin_mosi = S3C2410_GPG6,
  205. .pin_miso = S3C2410_GPG5,
  206. .chip_select = &spi_gpio_cs,
  207. };
  208. static struct platform_device qt2410_spi = {
  209. .name = "s3c24xx-spi-gpio",
  210. .id = 1,
  211. .dev = {
  212. .platform_data = &spi_gpio_cfg,
  213. },
  214. };
  215. /* Board devices */
  216. static struct platform_device *qt2410_devices[] __initdata = {
  217. &s3c_device_usb,
  218. &s3c_device_lcd,
  219. &s3c_device_wdt,
  220. &s3c_device_i2c,
  221. &s3c_device_iis,
  222. &s3c_device_sdi,
  223. &s3c_device_usbgadget,
  224. &qt2410_spi,
  225. &qt2410_cs89x0,
  226. &qt2410_led,
  227. };
  228. static struct mtd_partition qt2410_nand_part[] = {
  229. [0] = {
  230. .name = "U-Boot",
  231. .size = 0x30000,
  232. .offset = 0,
  233. },
  234. [1] = {
  235. .name = "U-Boot environment",
  236. .offset = 0x30000,
  237. .size = 0x4000,
  238. },
  239. [2] = {
  240. .name = "kernel",
  241. .offset = 0x34000,
  242. .size = SZ_2M,
  243. },
  244. [3] = {
  245. .name = "initrd",
  246. .offset = 0x234000,
  247. .size = SZ_4M,
  248. },
  249. [4] = {
  250. .name = "jffs2",
  251. .offset = 0x634000,
  252. .size = 0x39cc000,
  253. },
  254. };
  255. static struct s3c2410_nand_set qt2410_nand_sets[] = {
  256. [0] = {
  257. .name = "NAND",
  258. .nr_chips = 1,
  259. .nr_partitions = ARRAY_SIZE(qt2410_nand_part),
  260. .partitions = qt2410_nand_part,
  261. },
  262. };
  263. /* choose a set of timings which should suit most 512Mbit
  264. * chips and beyond.
  265. */
  266. static struct s3c2410_platform_nand qt2410_nand_info = {
  267. .tacls = 20,
  268. .twrph0 = 60,
  269. .twrph1 = 20,
  270. .nr_sets = ARRAY_SIZE(qt2410_nand_sets),
  271. .sets = qt2410_nand_sets,
  272. };
  273. /* UDC */
  274. static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
  275. };
  276. static char tft_type = 's';
  277. static int __init qt2410_tft_setup(char *str)
  278. {
  279. tft_type = str[0];
  280. return 1;
  281. }
  282. __setup("tft=", qt2410_tft_setup);
  283. static void __init qt2410_map_io(void)
  284. {
  285. s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
  286. s3c24xx_init_clocks(12*1000*1000);
  287. s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
  288. }
  289. static void __init qt2410_machine_init(void)
  290. {
  291. s3c_device_nand.dev.platform_data = &qt2410_nand_info;
  292. switch (tft_type) {
  293. case 'p': /* production */
  294. qt2410_fb_info.default_display = 1;
  295. break;
  296. case 'b': /* big */
  297. qt2410_fb_info.default_display = 0;
  298. break;
  299. case 's': /* small */
  300. default:
  301. qt2410_fb_info.default_display = 2;
  302. break;
  303. }
  304. s3c24xx_fb_set_platdata(&qt2410_fb_info);
  305. s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
  306. s3c2410_gpio_setpin(S3C2410_GPB0, 1);
  307. s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
  308. s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
  309. platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
  310. s3c2410_pm_init();
  311. }
  312. MACHINE_START(QT2410, "QT2410")
  313. .phys_io = S3C2410_PA_UART,
  314. .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
  315. .boot_params = S3C2410_SDRAM_PA + 0x100,
  316. .map_io = qt2410_map_io,
  317. .init_irq = s3c24xx_init_irq,
  318. .init_machine = qt2410_machine_init,
  319. .timer = &s3c24xx_timer,
  320. MACHINE_END