pci.c 6.1 KB

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  1. /*
  2. * arch/arm/mach-ixp23xx/pci.c
  3. *
  4. * PCI routines for IXP23XX based systems
  5. *
  6. * Copyright (c) 2005 MontaVista Software, Inc.
  7. *
  8. * based on original code:
  9. *
  10. * Author: Naeem Afzal <naeem.m.afzal@intel.com>
  11. * Copyright 2002-2005 Intel Corp.
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. */
  18. #include <linux/sched.h>
  19. #include <linux/kernel.h>
  20. #include <linux/pci.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/mm.h>
  23. #include <linux/init.h>
  24. #include <linux/ioport.h>
  25. #include <linux/slab.h>
  26. #include <linux/delay.h>
  27. #include <linux/io.h>
  28. #include <asm/irq.h>
  29. #include <asm/sizes.h>
  30. #include <asm/system.h>
  31. #include <asm/mach/pci.h>
  32. #include <mach/hardware.h>
  33. extern int (*external_fault) (unsigned long, struct pt_regs *);
  34. static volatile int pci_master_aborts = 0;
  35. #ifdef DEBUG
  36. #define DBG(x...) printk(x)
  37. #else
  38. #define DBG(x...)
  39. #endif
  40. int clear_master_aborts(void);
  41. static u32
  42. *ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
  43. {
  44. u32 *paddress;
  45. /*
  46. * Must be dword aligned
  47. */
  48. where &= ~3;
  49. /*
  50. * For top bus, generate type 0, else type 1
  51. */
  52. if (!bus_nr) {
  53. if (PCI_SLOT(devfn) >= 8)
  54. return 0;
  55. paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
  56. | (1 << (PCI_SLOT(devfn) + 16))
  57. | (PCI_FUNC(devfn) << 8) | where);
  58. } else {
  59. paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
  60. | (bus_nr << 16)
  61. | (PCI_SLOT(devfn) << 11)
  62. | (PCI_FUNC(devfn) << 8) | where);
  63. }
  64. return paddress;
  65. }
  66. /*
  67. * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
  68. * 0 and 3 are not valid indexes...
  69. */
  70. static u32 bytemask[] = {
  71. /*0*/ 0,
  72. /*1*/ 0xff,
  73. /*2*/ 0xffff,
  74. /*3*/ 0,
  75. /*4*/ 0xffffffff,
  76. };
  77. static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  78. int where, int size, u32 *value)
  79. {
  80. u32 n;
  81. u32 *addr;
  82. n = where % 4;
  83. DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
  84. bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
  85. addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
  86. if (!addr)
  87. return PCIBIOS_DEVICE_NOT_FOUND;
  88. pci_master_aborts = 0;
  89. *value = (*addr >> (8*n)) & bytemask[size];
  90. if (pci_master_aborts) {
  91. pci_master_aborts = 0;
  92. *value = 0xffffffff;
  93. return PCIBIOS_DEVICE_NOT_FOUND;
  94. }
  95. return PCIBIOS_SUCCESSFUL;
  96. }
  97. /*
  98. * We don't do error checking on the address for writes.
  99. * It's assumed that the user checked for the device existing first
  100. * by doing a read first.
  101. */
  102. static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
  103. int where, int size, u32 value)
  104. {
  105. u32 mask;
  106. u32 *addr;
  107. u32 temp;
  108. mask = ~(bytemask[size] << ((where % 0x4) * 8));
  109. addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
  110. if (!addr)
  111. return PCIBIOS_DEVICE_NOT_FOUND;
  112. temp = (u32) (value) << ((where % 0x4) * 8);
  113. *addr = (*addr & mask) | temp;
  114. clear_master_aborts();
  115. return PCIBIOS_SUCCESSFUL;
  116. }
  117. struct pci_ops ixp23xx_pci_ops = {
  118. .read = ixp23xx_pci_read_config,
  119. .write = ixp23xx_pci_write_config,
  120. };
  121. struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
  122. {
  123. return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata);
  124. }
  125. int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
  126. {
  127. volatile unsigned long temp;
  128. unsigned long flags;
  129. pci_master_aborts = 1;
  130. local_irq_save(flags);
  131. temp = *IXP23XX_PCI_CONTROL;
  132. /*
  133. * master abort and cmd tgt err
  134. */
  135. if (temp & ((1 << 8) | (1 << 5)))
  136. *IXP23XX_PCI_CONTROL = temp;
  137. temp = *IXP23XX_PCI_CMDSTAT;
  138. if (temp & (1 << 29))
  139. *IXP23XX_PCI_CMDSTAT = temp;
  140. local_irq_restore(flags);
  141. /*
  142. * If it was an imprecise abort, then we need to correct the
  143. * return address to be _after_ the instruction.
  144. */
  145. if (fsr & (1 << 10))
  146. regs->ARM_pc += 4;
  147. return 0;
  148. }
  149. int clear_master_aborts(void)
  150. {
  151. volatile u32 temp;
  152. temp = *IXP23XX_PCI_CONTROL;
  153. /*
  154. * master abort and cmd tgt err
  155. */
  156. if (temp & ((1 << 8) | (1 << 5)))
  157. *IXP23XX_PCI_CONTROL = temp;
  158. temp = *IXP23XX_PCI_CMDSTAT;
  159. if (temp & (1 << 29))
  160. *IXP23XX_PCI_CMDSTAT = temp;
  161. return 0;
  162. }
  163. static void __init ixp23xx_pci_common_init(void)
  164. {
  165. #ifdef __ARMEB__
  166. *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */
  167. #endif
  168. /*
  169. * ADDR_31 needs to be clear for PCI memory access to CPP memory
  170. */
  171. *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
  172. *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
  173. /*
  174. * Select correct memory for PCI inbound transactions
  175. */
  176. if (ixp23xx_cpp_boot()) {
  177. *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
  178. } else {
  179. *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
  180. /*
  181. * Enable coherency on A2 silicon.
  182. */
  183. if (arch_is_coherent())
  184. *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF;
  185. }
  186. }
  187. void __init ixp23xx_pci_preinit(void)
  188. {
  189. ixp23xx_pci_common_init();
  190. hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS,
  191. "PCI config cycle to non-existent device");
  192. *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
  193. }
  194. /*
  195. * Prevent PCI layer from seeing the inbound host-bridge resources
  196. */
  197. static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
  198. {
  199. int i;
  200. dev->class &= 0xff;
  201. dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
  202. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  203. dev->resource[i].start = 0;
  204. dev->resource[i].end = 0;
  205. dev->resource[i].flags = 0;
  206. }
  207. }
  208. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
  209. /*
  210. * IXP2300 systems often have large resource requirements, so we just
  211. * use our own resource space.
  212. */
  213. static struct resource ixp23xx_pci_mem_space = {
  214. .start = IXP23XX_PCI_MEM_START,
  215. .end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
  216. .flags = IORESOURCE_MEM,
  217. .name = "PCI Mem Space"
  218. };
  219. static struct resource ixp23xx_pci_io_space = {
  220. .start = 0x00000100,
  221. .end = 0x01ffffff,
  222. .flags = IORESOURCE_IO,
  223. .name = "PCI I/O Space"
  224. };
  225. int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
  226. {
  227. if (nr >= 1)
  228. return 0;
  229. sys->resource[0] = &ixp23xx_pci_io_space;
  230. sys->resource[1] = &ixp23xx_pci_mem_space;
  231. sys->resource[2] = NULL;
  232. return 1;
  233. }
  234. void __init ixp23xx_pci_slave_init(void)
  235. {
  236. ixp23xx_pci_common_init();
  237. }