twl4030.c 16 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include "twl4030.h"
  36. /*
  37. * twl4030 register cache & default register settings
  38. */
  39. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  40. 0x00, /* this register not used */
  41. 0x93, /* REG_CODEC_MODE (0x1) */
  42. 0xc3, /* REG_OPTION (0x2) */
  43. 0x00, /* REG_UNKNOWN (0x3) */
  44. 0x00, /* REG_MICBIAS_CTL (0x4) */
  45. 0x24, /* REG_ANAMICL (0x5) */
  46. 0x04, /* REG_ANAMICR (0x6) */
  47. 0x0a, /* REG_AVADC_CTL (0x7) */
  48. 0x00, /* REG_ADCMICSEL (0x8) */
  49. 0x00, /* REG_DIGMIXING (0x9) */
  50. 0x0c, /* REG_ATXL1PGA (0xA) */
  51. 0x0c, /* REG_ATXR1PGA (0xB) */
  52. 0x00, /* REG_AVTXL2PGA (0xC) */
  53. 0x00, /* REG_AVTXR2PGA (0xD) */
  54. 0x01, /* REG_AUDIO_IF (0xE) */
  55. 0x00, /* REG_VOICE_IF (0xF) */
  56. 0x00, /* REG_ARXR1PGA (0x10) */
  57. 0x00, /* REG_ARXL1PGA (0x11) */
  58. 0x6c, /* REG_ARXR2PGA (0x12) */
  59. 0x6c, /* REG_ARXL2PGA (0x13) */
  60. 0x00, /* REG_VRXPGA (0x14) */
  61. 0x00, /* REG_VSTPGA (0x15) */
  62. 0x00, /* REG_VRX2ARXPGA (0x16) */
  63. 0x0c, /* REG_AVDAC_CTL (0x17) */
  64. 0x00, /* REG_ARX2VTXPGA (0x18) */
  65. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  66. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  67. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  68. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  69. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  70. 0x00, /* REG_BT_IF (0x1E) */
  71. 0x00, /* REG_BTPGA (0x1F) */
  72. 0x00, /* REG_BTSTPGA (0x20) */
  73. 0x00, /* REG_EAR_CTL (0x21) */
  74. 0x24, /* REG_HS_SEL (0x22) */
  75. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  76. 0x00, /* REG_HS_POPN_SET (0x24) */
  77. 0x00, /* REG_PREDL_CTL (0x25) */
  78. 0x00, /* REG_PREDR_CTL (0x26) */
  79. 0x00, /* REG_PRECKL_CTL (0x27) */
  80. 0x00, /* REG_PRECKR_CTL (0x28) */
  81. 0x00, /* REG_HFL_CTL (0x29) */
  82. 0x00, /* REG_HFR_CTL (0x2A) */
  83. 0x00, /* REG_ALC_CTL (0x2B) */
  84. 0x00, /* REG_ALC_SET1 (0x2C) */
  85. 0x00, /* REG_ALC_SET2 (0x2D) */
  86. 0x00, /* REG_BOOST_CTL (0x2E) */
  87. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  88. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  89. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  90. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  91. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  92. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  93. 0x00, /* REG_DTMF_TONOFF (0x35) */
  94. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  95. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  98. 0x16, /* REG_APLL_CTL (0x3A) */
  99. 0x00, /* REG_DTMF_CTL (0x3B) */
  100. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  101. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  102. 0x00, /* REG_MISC_SET_1 (0x3E) */
  103. 0x00, /* REG_PCMBTMUX (0x3F) */
  104. 0x00, /* not used (0x40) */
  105. 0x00, /* not used (0x41) */
  106. 0x00, /* not used (0x42) */
  107. 0x00, /* REG_RX_PATH_SEL (0x43) */
  108. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  109. 0x00, /* REG_VIBRA_CTL (0x45) */
  110. 0x00, /* REG_VIBRA_SET (0x46) */
  111. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  112. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  113. 0x00, /* REG_MISC_SET_2 (0x49) */
  114. };
  115. /*
  116. * read twl4030 register cache
  117. */
  118. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  119. unsigned int reg)
  120. {
  121. u8 *cache = codec->reg_cache;
  122. return cache[reg];
  123. }
  124. /*
  125. * write twl4030 register cache
  126. */
  127. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  128. u8 reg, u8 value)
  129. {
  130. u8 *cache = codec->reg_cache;
  131. if (reg >= TWL4030_CACHEREGNUM)
  132. return;
  133. cache[reg] = value;
  134. }
  135. /*
  136. * write to the twl4030 register space
  137. */
  138. static int twl4030_write(struct snd_soc_codec *codec,
  139. unsigned int reg, unsigned int value)
  140. {
  141. twl4030_write_reg_cache(codec, reg, value);
  142. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  143. }
  144. static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
  145. {
  146. u8 mode;
  147. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  148. twl4030_write(codec, TWL4030_REG_CODEC_MODE,
  149. mode & ~TWL4030_CODECPDZ);
  150. /* REVISIT: this delay is present in TI sample drivers */
  151. /* but there seems to be no TRM requirement for it */
  152. udelay(10);
  153. }
  154. static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
  155. {
  156. u8 mode;
  157. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  158. twl4030_write(codec, TWL4030_REG_CODEC_MODE,
  159. mode | TWL4030_CODECPDZ);
  160. /* REVISIT: this delay is present in TI sample drivers */
  161. /* but there seems to be no TRM requirement for it */
  162. udelay(10);
  163. }
  164. static void twl4030_init_chip(struct snd_soc_codec *codec)
  165. {
  166. int i;
  167. /* clear CODECPDZ prior to setting register defaults */
  168. twl4030_clear_codecpdz(codec);
  169. /* set all audio section registers to reasonable defaults */
  170. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  171. twl4030_write(codec, i, twl4030_reg[i]);
  172. }
  173. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  174. SOC_DOUBLE_R("Master Playback Volume",
  175. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  176. 0, 0x3f, 0),
  177. SOC_DOUBLE_R("Capture Volume",
  178. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  179. 0, 0x1f, 0),
  180. };
  181. /* add non dapm controls */
  182. static int twl4030_add_controls(struct snd_soc_codec *codec)
  183. {
  184. int err, i;
  185. for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
  186. err = snd_ctl_add(codec->card,
  187. snd_soc_cnew(&twl4030_snd_controls[i],
  188. codec, NULL));
  189. if (err < 0)
  190. return err;
  191. }
  192. return 0;
  193. }
  194. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  195. SND_SOC_DAPM_INPUT("INL"),
  196. SND_SOC_DAPM_INPUT("INR"),
  197. SND_SOC_DAPM_OUTPUT("OUTL"),
  198. SND_SOC_DAPM_OUTPUT("OUTR"),
  199. SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
  200. SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
  201. SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
  202. SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
  203. };
  204. static const struct snd_soc_dapm_route intercon[] = {
  205. /* outputs */
  206. {"OUTL", NULL, "DACL"},
  207. {"OUTR", NULL, "DACR"},
  208. /* inputs */
  209. {"ADCL", NULL, "INL"},
  210. {"ADCR", NULL, "INR"},
  211. };
  212. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  213. {
  214. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  215. ARRAY_SIZE(twl4030_dapm_widgets));
  216. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  217. snd_soc_dapm_new_widgets(codec);
  218. return 0;
  219. }
  220. static void twl4030_power_up(struct snd_soc_codec *codec)
  221. {
  222. u8 anamicl, regmisc1, byte, popn, hsgain;
  223. int i = 0;
  224. /* set CODECPDZ to turn on codec */
  225. twl4030_set_codecpdz(codec);
  226. /* initiate offset cancellation */
  227. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  228. twl4030_write(codec, TWL4030_REG_ANAMICL,
  229. anamicl | TWL4030_CNCL_OFFSET_START);
  230. /* wait for offset cancellation to complete */
  231. do {
  232. /* this takes a little while, so don't slam i2c */
  233. udelay(2000);
  234. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  235. TWL4030_REG_ANAMICL);
  236. } while ((i++ < 100) &&
  237. ((byte & TWL4030_CNCL_OFFSET_START) ==
  238. TWL4030_CNCL_OFFSET_START));
  239. /* anti-pop when changing analog gain */
  240. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  241. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  242. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  243. /* toggle CODECPDZ as per TRM */
  244. twl4030_clear_codecpdz(codec);
  245. twl4030_set_codecpdz(codec);
  246. /* program anti-pop with bias ramp delay */
  247. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  248. popn &= TWL4030_RAMP_DELAY;
  249. popn |= TWL4030_RAMP_DELAY_645MS;
  250. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  251. popn |= TWL4030_VMID_EN;
  252. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  253. /* enable output stage and gain setting */
  254. hsgain = TWL4030_HSR_GAIN_0DB | TWL4030_HSL_GAIN_0DB;
  255. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
  256. /* enable anti-pop ramp */
  257. popn |= TWL4030_RAMP_EN;
  258. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  259. }
  260. static void twl4030_power_down(struct snd_soc_codec *codec)
  261. {
  262. u8 popn, hsgain;
  263. /* disable anti-pop ramp */
  264. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  265. popn &= ~TWL4030_RAMP_EN;
  266. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  267. /* disable output stage and gain setting */
  268. hsgain = TWL4030_HSR_GAIN_PWR_DOWN | TWL4030_HSL_GAIN_PWR_DOWN;
  269. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hsgain);
  270. /* disable bias out */
  271. popn &= ~TWL4030_VMID_EN;
  272. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  273. /* power down */
  274. twl4030_clear_codecpdz(codec);
  275. }
  276. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  277. enum snd_soc_bias_level level)
  278. {
  279. switch (level) {
  280. case SND_SOC_BIAS_ON:
  281. twl4030_power_up(codec);
  282. break;
  283. case SND_SOC_BIAS_PREPARE:
  284. /* TODO: develop a twl4030_prepare function */
  285. break;
  286. case SND_SOC_BIAS_STANDBY:
  287. /* TODO: develop a twl4030_standby function */
  288. twl4030_power_down(codec);
  289. break;
  290. case SND_SOC_BIAS_OFF:
  291. twl4030_power_down(codec);
  292. break;
  293. }
  294. codec->bias_level = level;
  295. return 0;
  296. }
  297. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  298. struct snd_pcm_hw_params *params,
  299. struct snd_soc_dai *dai)
  300. {
  301. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  302. struct snd_soc_device *socdev = rtd->socdev;
  303. struct snd_soc_codec *codec = socdev->codec;
  304. u8 mode, old_mode, format, old_format;
  305. /* bit rate */
  306. old_mode = twl4030_read_reg_cache(codec,
  307. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  308. mode = old_mode & ~TWL4030_APLL_RATE;
  309. switch (params_rate(params)) {
  310. case 8000:
  311. mode |= TWL4030_APLL_RATE_8000;
  312. break;
  313. case 11025:
  314. mode |= TWL4030_APLL_RATE_11025;
  315. break;
  316. case 12000:
  317. mode |= TWL4030_APLL_RATE_12000;
  318. break;
  319. case 16000:
  320. mode |= TWL4030_APLL_RATE_16000;
  321. break;
  322. case 22050:
  323. mode |= TWL4030_APLL_RATE_22050;
  324. break;
  325. case 24000:
  326. mode |= TWL4030_APLL_RATE_24000;
  327. break;
  328. case 32000:
  329. mode |= TWL4030_APLL_RATE_32000;
  330. break;
  331. case 44100:
  332. mode |= TWL4030_APLL_RATE_44100;
  333. break;
  334. case 48000:
  335. mode |= TWL4030_APLL_RATE_48000;
  336. break;
  337. default:
  338. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  339. params_rate(params));
  340. return -EINVAL;
  341. }
  342. if (mode != old_mode) {
  343. /* change rate and set CODECPDZ */
  344. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  345. twl4030_set_codecpdz(codec);
  346. }
  347. /* sample size */
  348. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  349. format = old_format;
  350. format &= ~TWL4030_DATA_WIDTH;
  351. switch (params_format(params)) {
  352. case SNDRV_PCM_FORMAT_S16_LE:
  353. format |= TWL4030_DATA_WIDTH_16S_16W;
  354. break;
  355. case SNDRV_PCM_FORMAT_S24_LE:
  356. format |= TWL4030_DATA_WIDTH_32S_24W;
  357. break;
  358. default:
  359. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  360. params_format(params));
  361. return -EINVAL;
  362. }
  363. if (format != old_format) {
  364. /* clear CODECPDZ before changing format (codec requirement) */
  365. twl4030_clear_codecpdz(codec);
  366. /* change format */
  367. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  368. /* set CODECPDZ afterwards */
  369. twl4030_set_codecpdz(codec);
  370. }
  371. return 0;
  372. }
  373. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  374. int clk_id, unsigned int freq, int dir)
  375. {
  376. struct snd_soc_codec *codec = codec_dai->codec;
  377. u8 infreq;
  378. switch (freq) {
  379. case 19200000:
  380. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  381. break;
  382. case 26000000:
  383. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  384. break;
  385. case 38400000:
  386. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  387. break;
  388. default:
  389. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  390. freq);
  391. return -EINVAL;
  392. }
  393. infreq |= TWL4030_APLL_EN;
  394. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  395. return 0;
  396. }
  397. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  398. unsigned int fmt)
  399. {
  400. struct snd_soc_codec *codec = codec_dai->codec;
  401. u8 old_format, format;
  402. /* get format */
  403. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  404. format = old_format;
  405. /* set master/slave audio interface */
  406. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  407. case SND_SOC_DAIFMT_CBM_CFM:
  408. format &= ~(TWL4030_AIF_SLAVE_EN);
  409. format &= ~(TWL4030_CLK256FS_EN);
  410. break;
  411. case SND_SOC_DAIFMT_CBS_CFS:
  412. format |= TWL4030_AIF_SLAVE_EN;
  413. format |= TWL4030_CLK256FS_EN;
  414. break;
  415. default:
  416. return -EINVAL;
  417. }
  418. /* interface format */
  419. format &= ~TWL4030_AIF_FORMAT;
  420. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  421. case SND_SOC_DAIFMT_I2S:
  422. format |= TWL4030_AIF_FORMAT_CODEC;
  423. break;
  424. default:
  425. return -EINVAL;
  426. }
  427. if (format != old_format) {
  428. /* clear CODECPDZ before changing format (codec requirement) */
  429. twl4030_clear_codecpdz(codec);
  430. /* change format */
  431. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  432. /* set CODECPDZ afterwards */
  433. twl4030_set_codecpdz(codec);
  434. }
  435. return 0;
  436. }
  437. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  438. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  439. struct snd_soc_dai twl4030_dai = {
  440. .name = "twl4030",
  441. .playback = {
  442. .stream_name = "Playback",
  443. .channels_min = 2,
  444. .channels_max = 2,
  445. .rates = TWL4030_RATES,
  446. .formats = TWL4030_FORMATS,},
  447. .capture = {
  448. .stream_name = "Capture",
  449. .channels_min = 2,
  450. .channels_max = 2,
  451. .rates = TWL4030_RATES,
  452. .formats = TWL4030_FORMATS,},
  453. .ops = {
  454. .hw_params = twl4030_hw_params,
  455. .set_sysclk = twl4030_set_dai_sysclk,
  456. .set_fmt = twl4030_set_dai_fmt,
  457. }
  458. };
  459. EXPORT_SYMBOL_GPL(twl4030_dai);
  460. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  461. {
  462. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  463. struct snd_soc_codec *codec = socdev->codec;
  464. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  465. return 0;
  466. }
  467. static int twl4030_resume(struct platform_device *pdev)
  468. {
  469. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  470. struct snd_soc_codec *codec = socdev->codec;
  471. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  472. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  473. return 0;
  474. }
  475. /*
  476. * initialize the driver
  477. * register the mixer and dsp interfaces with the kernel
  478. */
  479. static int twl4030_init(struct snd_soc_device *socdev)
  480. {
  481. struct snd_soc_codec *codec = socdev->codec;
  482. int ret = 0;
  483. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  484. codec->name = "twl4030";
  485. codec->owner = THIS_MODULE;
  486. codec->read = twl4030_read_reg_cache;
  487. codec->write = twl4030_write;
  488. codec->set_bias_level = twl4030_set_bias_level;
  489. codec->dai = &twl4030_dai;
  490. codec->num_dai = 1;
  491. codec->reg_cache_size = sizeof(twl4030_reg);
  492. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  493. GFP_KERNEL);
  494. if (codec->reg_cache == NULL)
  495. return -ENOMEM;
  496. /* register pcms */
  497. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  498. if (ret < 0) {
  499. printk(KERN_ERR "twl4030: failed to create pcms\n");
  500. goto pcm_err;
  501. }
  502. twl4030_init_chip(codec);
  503. /* power on device */
  504. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  505. twl4030_add_controls(codec);
  506. twl4030_add_widgets(codec);
  507. ret = snd_soc_register_card(socdev);
  508. if (ret < 0) {
  509. printk(KERN_ERR "twl4030: failed to register card\n");
  510. goto card_err;
  511. }
  512. return ret;
  513. card_err:
  514. snd_soc_free_pcms(socdev);
  515. snd_soc_dapm_free(socdev);
  516. pcm_err:
  517. kfree(codec->reg_cache);
  518. return ret;
  519. }
  520. static struct snd_soc_device *twl4030_socdev;
  521. static int twl4030_probe(struct platform_device *pdev)
  522. {
  523. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  524. struct snd_soc_codec *codec;
  525. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  526. if (codec == NULL)
  527. return -ENOMEM;
  528. socdev->codec = codec;
  529. mutex_init(&codec->mutex);
  530. INIT_LIST_HEAD(&codec->dapm_widgets);
  531. INIT_LIST_HEAD(&codec->dapm_paths);
  532. twl4030_socdev = socdev;
  533. twl4030_init(socdev);
  534. return 0;
  535. }
  536. static int twl4030_remove(struct platform_device *pdev)
  537. {
  538. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  539. struct snd_soc_codec *codec = socdev->codec;
  540. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  541. kfree(codec);
  542. return 0;
  543. }
  544. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  545. .probe = twl4030_probe,
  546. .remove = twl4030_remove,
  547. .suspend = twl4030_suspend,
  548. .resume = twl4030_resume,
  549. };
  550. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  551. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  552. MODULE_AUTHOR("Steve Sakoman");
  553. MODULE_LICENSE("GPL");