synclink_cs.c 117 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566
  1. /*
  2. * linux/drivers/char/pcmcia/synclink_cs.c
  3. *
  4. * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
  5. *
  6. * Device driver for Microgate SyncLink PC Card
  7. * multiprotocol serial adapter.
  8. *
  9. * written by Paul Fulghum for Microgate Corporation
  10. * paulkf@microgate.com
  11. *
  12. * Microgate and SyncLink are trademarks of Microgate Corporation
  13. *
  14. * This code is released under the GNU General Public License (GPL)
  15. *
  16. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  17. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  20. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  22. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  24. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  26. * OF THE POSSIBILITY OF SUCH DAMAGE.
  27. */
  28. #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29. #if defined(__i386__)
  30. # define BREAKPOINT() asm(" int $3");
  31. #else
  32. # define BREAKPOINT() { }
  33. #endif
  34. #define MAX_DEVICE_COUNT 4
  35. #include <linux/config.h>
  36. #include <linux/module.h>
  37. #include <linux/errno.h>
  38. #include <linux/signal.h>
  39. #include <linux/sched.h>
  40. #include <linux/timer.h>
  41. #include <linux/time.h>
  42. #include <linux/interrupt.h>
  43. #include <linux/pci.h>
  44. #include <linux/tty.h>
  45. #include <linux/tty_flip.h>
  46. #include <linux/serial.h>
  47. #include <linux/major.h>
  48. #include <linux/string.h>
  49. #include <linux/fcntl.h>
  50. #include <linux/ptrace.h>
  51. #include <linux/ioport.h>
  52. #include <linux/mm.h>
  53. #include <linux/slab.h>
  54. #include <linux/netdevice.h>
  55. #include <linux/vmalloc.h>
  56. #include <linux/init.h>
  57. #include <asm/serial.h>
  58. #include <linux/delay.h>
  59. #include <linux/ioctl.h>
  60. #include <asm/system.h>
  61. #include <asm/io.h>
  62. #include <asm/irq.h>
  63. #include <asm/dma.h>
  64. #include <linux/bitops.h>
  65. #include <asm/types.h>
  66. #include <linux/termios.h>
  67. #include <linux/workqueue.h>
  68. #include <linux/hdlc.h>
  69. #include <pcmcia/cs_types.h>
  70. #include <pcmcia/cs.h>
  71. #include <pcmcia/cistpl.h>
  72. #include <pcmcia/cisreg.h>
  73. #include <pcmcia/ds.h>
  74. #ifdef CONFIG_HDLC_MODULE
  75. #define CONFIG_HDLC 1
  76. #endif
  77. #define GET_USER(error,value,addr) error = get_user(value,addr)
  78. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  79. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  80. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  81. #include <asm/uaccess.h>
  82. #include "linux/synclink.h"
  83. static MGSL_PARAMS default_params = {
  84. MGSL_MODE_HDLC, /* unsigned long mode */
  85. 0, /* unsigned char loopback; */
  86. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  87. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  88. 0, /* unsigned long clock_speed; */
  89. 0xff, /* unsigned char addr_filter; */
  90. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  91. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  92. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  93. 9600, /* unsigned long data_rate; */
  94. 8, /* unsigned char data_bits; */
  95. 1, /* unsigned char stop_bits; */
  96. ASYNC_PARITY_NONE /* unsigned char parity; */
  97. };
  98. typedef struct
  99. {
  100. int count;
  101. unsigned char status;
  102. char data[1];
  103. } RXBUF;
  104. /* The queue of BH actions to be performed */
  105. #define BH_RECEIVE 1
  106. #define BH_TRANSMIT 2
  107. #define BH_STATUS 4
  108. #define IO_PIN_SHUTDOWN_LIMIT 100
  109. #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
  110. struct _input_signal_events {
  111. int ri_up;
  112. int ri_down;
  113. int dsr_up;
  114. int dsr_down;
  115. int dcd_up;
  116. int dcd_down;
  117. int cts_up;
  118. int cts_down;
  119. };
  120. /*
  121. * Device instance data structure
  122. */
  123. typedef struct _mgslpc_info {
  124. void *if_ptr; /* General purpose pointer (used by SPPP) */
  125. int magic;
  126. int flags;
  127. int count; /* count of opens */
  128. int line;
  129. unsigned short close_delay;
  130. unsigned short closing_wait; /* time to wait before closing */
  131. struct mgsl_icount icount;
  132. struct tty_struct *tty;
  133. int timeout;
  134. int x_char; /* xon/xoff character */
  135. int blocked_open; /* # of blocked opens */
  136. unsigned char read_status_mask;
  137. unsigned char ignore_status_mask;
  138. unsigned char *tx_buf;
  139. int tx_put;
  140. int tx_get;
  141. int tx_count;
  142. /* circular list of fixed length rx buffers */
  143. unsigned char *rx_buf; /* memory allocated for all rx buffers */
  144. int rx_buf_total_size; /* size of memory allocated for rx buffers */
  145. int rx_put; /* index of next empty rx buffer */
  146. int rx_get; /* index of next full rx buffer */
  147. int rx_buf_size; /* size in bytes of single rx buffer */
  148. int rx_buf_count; /* total number of rx buffers */
  149. int rx_frame_count; /* number of full rx buffers */
  150. wait_queue_head_t open_wait;
  151. wait_queue_head_t close_wait;
  152. wait_queue_head_t status_event_wait_q;
  153. wait_queue_head_t event_wait_q;
  154. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  155. struct _mgslpc_info *next_device; /* device list link */
  156. unsigned short imra_value;
  157. unsigned short imrb_value;
  158. unsigned char pim_value;
  159. spinlock_t lock;
  160. struct work_struct task; /* task structure for scheduling bh */
  161. u32 max_frame_size;
  162. u32 pending_bh;
  163. int bh_running;
  164. int bh_requested;
  165. int dcd_chkcount; /* check counts to prevent */
  166. int cts_chkcount; /* too many IRQs if a signal */
  167. int dsr_chkcount; /* is floating */
  168. int ri_chkcount;
  169. int rx_enabled;
  170. int rx_overflow;
  171. int tx_enabled;
  172. int tx_active;
  173. int tx_aborting;
  174. u32 idle_mode;
  175. int if_mode; /* serial interface selection (RS-232, v.35 etc) */
  176. char device_name[25]; /* device instance name */
  177. unsigned int io_base; /* base I/O address of adapter */
  178. unsigned int irq_level;
  179. MGSL_PARAMS params; /* communications parameters */
  180. unsigned char serial_signals; /* current serial signal states */
  181. char irq_occurred; /* for diagnostics use */
  182. char testing_irq;
  183. unsigned int init_error; /* startup error (DIAGS) */
  184. char flag_buf[MAX_ASYNC_BUFFER_SIZE];
  185. BOOLEAN drop_rts_on_tx_done;
  186. struct _input_signal_events input_signal_events;
  187. /* PCMCIA support */
  188. dev_link_t link;
  189. dev_node_t node;
  190. int stop;
  191. /* SPPP/Cisco HDLC device parts */
  192. int netcount;
  193. int dosyncppp;
  194. spinlock_t netlock;
  195. #ifdef CONFIG_HDLC
  196. struct net_device *netdev;
  197. #endif
  198. } MGSLPC_INFO;
  199. #define MGSLPC_MAGIC 0x5402
  200. /*
  201. * The size of the serial xmit buffer is 1 page, or 4096 bytes
  202. */
  203. #define TXBUFSIZE 4096
  204. #define CHA 0x00 /* channel A offset */
  205. #define CHB 0x40 /* channel B offset */
  206. /*
  207. * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
  208. */
  209. #undef PVR
  210. #define RXFIFO 0
  211. #define TXFIFO 0
  212. #define STAR 0x20
  213. #define CMDR 0x20
  214. #define RSTA 0x21
  215. #define PRE 0x21
  216. #define MODE 0x22
  217. #define TIMR 0x23
  218. #define XAD1 0x24
  219. #define XAD2 0x25
  220. #define RAH1 0x26
  221. #define RAH2 0x27
  222. #define DAFO 0x27
  223. #define RAL1 0x28
  224. #define RFC 0x28
  225. #define RHCR 0x29
  226. #define RAL2 0x29
  227. #define RBCL 0x2a
  228. #define XBCL 0x2a
  229. #define RBCH 0x2b
  230. #define XBCH 0x2b
  231. #define CCR0 0x2c
  232. #define CCR1 0x2d
  233. #define CCR2 0x2e
  234. #define CCR3 0x2f
  235. #define VSTR 0x34
  236. #define BGR 0x34
  237. #define RLCR 0x35
  238. #define AML 0x36
  239. #define AMH 0x37
  240. #define GIS 0x38
  241. #define IVA 0x38
  242. #define IPC 0x39
  243. #define ISR 0x3a
  244. #define IMR 0x3a
  245. #define PVR 0x3c
  246. #define PIS 0x3d
  247. #define PIM 0x3d
  248. #define PCR 0x3e
  249. #define CCR4 0x3f
  250. // IMR/ISR
  251. #define IRQ_BREAK_ON BIT15 // rx break detected
  252. #define IRQ_DATAOVERRUN BIT14 // receive data overflow
  253. #define IRQ_ALLSENT BIT13 // all sent
  254. #define IRQ_UNDERRUN BIT12 // transmit data underrun
  255. #define IRQ_TIMER BIT11 // timer interrupt
  256. #define IRQ_CTS BIT10 // CTS status change
  257. #define IRQ_TXREPEAT BIT9 // tx message repeat
  258. #define IRQ_TXFIFO BIT8 // transmit pool ready
  259. #define IRQ_RXEOM BIT7 // receive message end
  260. #define IRQ_EXITHUNT BIT6 // receive frame start
  261. #define IRQ_RXTIME BIT6 // rx char timeout
  262. #define IRQ_DCD BIT2 // carrier detect status change
  263. #define IRQ_OVERRUN BIT1 // receive frame overflow
  264. #define IRQ_RXFIFO BIT0 // receive pool full
  265. // STAR
  266. #define XFW BIT6 // transmit FIFO write enable
  267. #define CEC BIT2 // command executing
  268. #define CTS BIT1 // CTS state
  269. #define PVR_DTR BIT0
  270. #define PVR_DSR BIT1
  271. #define PVR_RI BIT2
  272. #define PVR_AUTOCTS BIT3
  273. #define PVR_RS232 0x20 /* 0010b */
  274. #define PVR_V35 0xe0 /* 1110b */
  275. #define PVR_RS422 0x40 /* 0100b */
  276. /* Register access functions */
  277. #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
  278. #define read_reg(info, reg) inb((info)->io_base + (reg))
  279. #define read_reg16(info, reg) inw((info)->io_base + (reg))
  280. #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
  281. #define set_reg_bits(info, reg, mask) \
  282. write_reg(info, (reg), \
  283. (unsigned char) (read_reg(info, (reg)) | (mask)))
  284. #define clear_reg_bits(info, reg, mask) \
  285. write_reg(info, (reg), \
  286. (unsigned char) (read_reg(info, (reg)) & ~(mask)))
  287. /*
  288. * interrupt enable/disable routines
  289. */
  290. static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  291. {
  292. if (channel == CHA) {
  293. info->imra_value |= mask;
  294. write_reg16(info, CHA + IMR, info->imra_value);
  295. } else {
  296. info->imrb_value |= mask;
  297. write_reg16(info, CHB + IMR, info->imrb_value);
  298. }
  299. }
  300. static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  301. {
  302. if (channel == CHA) {
  303. info->imra_value &= ~mask;
  304. write_reg16(info, CHA + IMR, info->imra_value);
  305. } else {
  306. info->imrb_value &= ~mask;
  307. write_reg16(info, CHB + IMR, info->imrb_value);
  308. }
  309. }
  310. #define port_irq_disable(info, mask) \
  311. { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
  312. #define port_irq_enable(info, mask) \
  313. { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
  314. static void rx_start(MGSLPC_INFO *info);
  315. static void rx_stop(MGSLPC_INFO *info);
  316. static void tx_start(MGSLPC_INFO *info);
  317. static void tx_stop(MGSLPC_INFO *info);
  318. static void tx_set_idle(MGSLPC_INFO *info);
  319. static void get_signals(MGSLPC_INFO *info);
  320. static void set_signals(MGSLPC_INFO *info);
  321. static void reset_device(MGSLPC_INFO *info);
  322. static void hdlc_mode(MGSLPC_INFO *info);
  323. static void async_mode(MGSLPC_INFO *info);
  324. static void tx_timeout(unsigned long context);
  325. static int ioctl_common(MGSLPC_INFO *info, unsigned int cmd, unsigned long arg);
  326. #ifdef CONFIG_HDLC
  327. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  328. static void hdlcdev_tx_done(MGSLPC_INFO *info);
  329. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
  330. static int hdlcdev_init(MGSLPC_INFO *info);
  331. static void hdlcdev_exit(MGSLPC_INFO *info);
  332. #endif
  333. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
  334. static BOOLEAN register_test(MGSLPC_INFO *info);
  335. static BOOLEAN irq_test(MGSLPC_INFO *info);
  336. static int adapter_test(MGSLPC_INFO *info);
  337. static int claim_resources(MGSLPC_INFO *info);
  338. static void release_resources(MGSLPC_INFO *info);
  339. static void mgslpc_add_device(MGSLPC_INFO *info);
  340. static void mgslpc_remove_device(MGSLPC_INFO *info);
  341. static int rx_get_frame(MGSLPC_INFO *info);
  342. static void rx_reset_buffers(MGSLPC_INFO *info);
  343. static int rx_alloc_buffers(MGSLPC_INFO *info);
  344. static void rx_free_buffers(MGSLPC_INFO *info);
  345. static irqreturn_t mgslpc_isr(int irq, void *dev_id, struct pt_regs * regs);
  346. /*
  347. * Bottom half interrupt handlers
  348. */
  349. static void bh_handler(void* Context);
  350. static void bh_transmit(MGSLPC_INFO *info);
  351. static void bh_status(MGSLPC_INFO *info);
  352. /*
  353. * ioctl handlers
  354. */
  355. static int tiocmget(struct tty_struct *tty, struct file *file);
  356. static int tiocmset(struct tty_struct *tty, struct file *file,
  357. unsigned int set, unsigned int clear);
  358. static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
  359. static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
  360. static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params);
  361. static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
  362. static int set_txidle(MGSLPC_INFO *info, int idle_mode);
  363. static int set_txenable(MGSLPC_INFO *info, int enable);
  364. static int tx_abort(MGSLPC_INFO *info);
  365. static int set_rxenable(MGSLPC_INFO *info, int enable);
  366. static int wait_events(MGSLPC_INFO *info, int __user *mask);
  367. static MGSLPC_INFO *mgslpc_device_list = NULL;
  368. static int mgslpc_device_count = 0;
  369. /*
  370. * Set this param to non-zero to load eax with the
  371. * .text section address and breakpoint on module load.
  372. * This is useful for use with gdb and add-symbol-file command.
  373. */
  374. static int break_on_load=0;
  375. /*
  376. * Driver major number, defaults to zero to get auto
  377. * assigned major number. May be forced as module parameter.
  378. */
  379. static int ttymajor=0;
  380. static int debug_level = 0;
  381. static int maxframe[MAX_DEVICE_COUNT] = {0,};
  382. static int dosyncppp[MAX_DEVICE_COUNT] = {1,1,1,1};
  383. module_param(break_on_load, bool, 0);
  384. module_param(ttymajor, int, 0);
  385. module_param(debug_level, int, 0);
  386. module_param_array(maxframe, int, NULL, 0);
  387. module_param_array(dosyncppp, int, NULL, 0);
  388. MODULE_LICENSE("GPL");
  389. static char *driver_name = "SyncLink PC Card driver";
  390. static char *driver_version = "$Revision: 4.34 $";
  391. static struct tty_driver *serial_driver;
  392. /* number of characters left in xmit buffer before we ask for more */
  393. #define WAKEUP_CHARS 256
  394. static void mgslpc_change_params(MGSLPC_INFO *info);
  395. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
  396. /* PCMCIA prototypes */
  397. static void mgslpc_config(dev_link_t *link);
  398. static void mgslpc_release(u_long arg);
  399. static void mgslpc_detach(struct pcmcia_device *p_dev);
  400. /*
  401. * 1st function defined in .text section. Calling this function in
  402. * init_module() followed by a breakpoint allows a remote debugger
  403. * (gdb) to get the .text address for the add-symbol-file command.
  404. * This allows remote debugging of dynamically loadable modules.
  405. */
  406. static void* mgslpc_get_text_ptr(void)
  407. {
  408. return mgslpc_get_text_ptr;
  409. }
  410. /**
  411. * line discipline callback wrappers
  412. *
  413. * The wrappers maintain line discipline references
  414. * while calling into the line discipline.
  415. *
  416. * ldisc_flush_buffer - flush line discipline receive buffers
  417. * ldisc_receive_buf - pass receive data to line discipline
  418. */
  419. static void ldisc_flush_buffer(struct tty_struct *tty)
  420. {
  421. struct tty_ldisc *ld = tty_ldisc_ref(tty);
  422. if (ld) {
  423. if (ld->flush_buffer)
  424. ld->flush_buffer(tty);
  425. tty_ldisc_deref(ld);
  426. }
  427. }
  428. static void ldisc_receive_buf(struct tty_struct *tty,
  429. const __u8 *data, char *flags, int count)
  430. {
  431. struct tty_ldisc *ld;
  432. if (!tty)
  433. return;
  434. ld = tty_ldisc_ref(tty);
  435. if (ld) {
  436. if (ld->receive_buf)
  437. ld->receive_buf(tty, data, flags, count);
  438. tty_ldisc_deref(ld);
  439. }
  440. }
  441. static int mgslpc_attach(struct pcmcia_device *p_dev)
  442. {
  443. MGSLPC_INFO *info;
  444. dev_link_t *link;
  445. if (debug_level >= DEBUG_LEVEL_INFO)
  446. printk("mgslpc_attach\n");
  447. info = (MGSLPC_INFO *)kmalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
  448. if (!info) {
  449. printk("Error can't allocate device instance data\n");
  450. return -ENOMEM;
  451. }
  452. memset(info, 0, sizeof(MGSLPC_INFO));
  453. info->magic = MGSLPC_MAGIC;
  454. INIT_WORK(&info->task, bh_handler, info);
  455. info->max_frame_size = 4096;
  456. info->close_delay = 5*HZ/10;
  457. info->closing_wait = 30*HZ;
  458. init_waitqueue_head(&info->open_wait);
  459. init_waitqueue_head(&info->close_wait);
  460. init_waitqueue_head(&info->status_event_wait_q);
  461. init_waitqueue_head(&info->event_wait_q);
  462. spin_lock_init(&info->lock);
  463. spin_lock_init(&info->netlock);
  464. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  465. info->idle_mode = HDLC_TXIDLE_FLAGS;
  466. info->imra_value = 0xffff;
  467. info->imrb_value = 0xffff;
  468. info->pim_value = 0xff;
  469. link = &info->link;
  470. link->priv = info;
  471. /* Initialize the dev_link_t structure */
  472. /* Interrupt setup */
  473. link->irq.Attributes = IRQ_TYPE_EXCLUSIVE;
  474. link->irq.IRQInfo1 = IRQ_LEVEL_ID;
  475. link->irq.Handler = NULL;
  476. link->conf.Attributes = 0;
  477. link->conf.Vcc = 50;
  478. link->conf.IntType = INT_MEMORY_AND_IO;
  479. link->handle = p_dev;
  480. p_dev->instance = link;
  481. link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
  482. mgslpc_config(link);
  483. mgslpc_add_device(info);
  484. return 0;
  485. }
  486. /* Card has been inserted.
  487. */
  488. #define CS_CHECK(fn, ret) \
  489. do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
  490. static void mgslpc_config(dev_link_t *link)
  491. {
  492. client_handle_t handle = link->handle;
  493. MGSLPC_INFO *info = link->priv;
  494. tuple_t tuple;
  495. cisparse_t parse;
  496. int last_fn, last_ret;
  497. u_char buf[64];
  498. config_info_t conf;
  499. cistpl_cftable_entry_t dflt = { 0 };
  500. cistpl_cftable_entry_t *cfg;
  501. if (debug_level >= DEBUG_LEVEL_INFO)
  502. printk("mgslpc_config(0x%p)\n", link);
  503. /* read CONFIG tuple to find its configuration registers */
  504. tuple.DesiredTuple = CISTPL_CONFIG;
  505. tuple.Attributes = 0;
  506. tuple.TupleData = buf;
  507. tuple.TupleDataMax = sizeof(buf);
  508. tuple.TupleOffset = 0;
  509. CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
  510. CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
  511. CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
  512. link->conf.ConfigBase = parse.config.base;
  513. link->conf.Present = parse.config.rmask[0];
  514. /* Configure card */
  515. link->state |= DEV_CONFIG;
  516. /* Look up the current Vcc */
  517. CS_CHECK(GetConfigurationInfo, pcmcia_get_configuration_info(handle, &conf));
  518. link->conf.Vcc = conf.Vcc;
  519. /* get CIS configuration entry */
  520. tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
  521. CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
  522. cfg = &(parse.cftable_entry);
  523. CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
  524. CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
  525. if (cfg->flags & CISTPL_CFTABLE_DEFAULT) dflt = *cfg;
  526. if (cfg->index == 0)
  527. goto cs_failed;
  528. link->conf.ConfigIndex = cfg->index;
  529. link->conf.Attributes |= CONF_ENABLE_IRQ;
  530. /* IO window settings */
  531. link->io.NumPorts1 = 0;
  532. if ((cfg->io.nwin > 0) || (dflt.io.nwin > 0)) {
  533. cistpl_io_t *io = (cfg->io.nwin) ? &cfg->io : &dflt.io;
  534. link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
  535. if (!(io->flags & CISTPL_IO_8BIT))
  536. link->io.Attributes1 = IO_DATA_PATH_WIDTH_16;
  537. if (!(io->flags & CISTPL_IO_16BIT))
  538. link->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
  539. link->io.IOAddrLines = io->flags & CISTPL_IO_LINES_MASK;
  540. link->io.BasePort1 = io->win[0].base;
  541. link->io.NumPorts1 = io->win[0].len;
  542. CS_CHECK(RequestIO, pcmcia_request_io(link->handle, &link->io));
  543. }
  544. link->conf.Attributes = CONF_ENABLE_IRQ;
  545. link->conf.Vcc = 50;
  546. link->conf.IntType = INT_MEMORY_AND_IO;
  547. link->conf.ConfigIndex = 8;
  548. link->conf.Present = PRESENT_OPTION;
  549. link->irq.Attributes |= IRQ_HANDLE_PRESENT;
  550. link->irq.Handler = mgslpc_isr;
  551. link->irq.Instance = info;
  552. CS_CHECK(RequestIRQ, pcmcia_request_irq(link->handle, &link->irq));
  553. CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link->handle, &link->conf));
  554. info->io_base = link->io.BasePort1;
  555. info->irq_level = link->irq.AssignedIRQ;
  556. /* add to linked list of devices */
  557. sprintf(info->node.dev_name, "mgslpc0");
  558. info->node.major = info->node.minor = 0;
  559. link->dev = &info->node;
  560. printk(KERN_INFO "%s: index 0x%02x:",
  561. info->node.dev_name, link->conf.ConfigIndex);
  562. if (link->conf.Attributes & CONF_ENABLE_IRQ)
  563. printk(", irq %d", link->irq.AssignedIRQ);
  564. if (link->io.NumPorts1)
  565. printk(", io 0x%04x-0x%04x", link->io.BasePort1,
  566. link->io.BasePort1+link->io.NumPorts1-1);
  567. printk("\n");
  568. link->state &= ~DEV_CONFIG_PENDING;
  569. return;
  570. cs_failed:
  571. cs_error(link->handle, last_fn, last_ret);
  572. mgslpc_release((u_long)link);
  573. }
  574. /* Card has been removed.
  575. * Unregister device and release PCMCIA configuration.
  576. * If device is open, postpone until it is closed.
  577. */
  578. static void mgslpc_release(u_long arg)
  579. {
  580. dev_link_t *link = (dev_link_t *)arg;
  581. if (debug_level >= DEBUG_LEVEL_INFO)
  582. printk("mgslpc_release(0x%p)\n", link);
  583. /* Unlink the device chain */
  584. link->dev = NULL;
  585. link->state &= ~DEV_CONFIG;
  586. pcmcia_release_configuration(link->handle);
  587. if (link->io.NumPorts1)
  588. pcmcia_release_io(link->handle, &link->io);
  589. if (link->irq.AssignedIRQ)
  590. pcmcia_release_irq(link->handle, &link->irq);
  591. }
  592. static void mgslpc_detach(struct pcmcia_device *p_dev)
  593. {
  594. dev_link_t *link = dev_to_instance(p_dev);
  595. if (debug_level >= DEBUG_LEVEL_INFO)
  596. printk("mgslpc_detach(0x%p)\n", link);
  597. if (link->state & DEV_CONFIG) {
  598. ((MGSLPC_INFO *)link->priv)->stop = 1;
  599. mgslpc_release((u_long)link);
  600. }
  601. mgslpc_remove_device((MGSLPC_INFO *)link->priv);
  602. }
  603. static int mgslpc_suspend(struct pcmcia_device *dev)
  604. {
  605. dev_link_t *link = dev_to_instance(dev);
  606. MGSLPC_INFO *info = link->priv;
  607. link->state |= DEV_SUSPEND;
  608. info->stop = 1;
  609. if (link->state & DEV_CONFIG)
  610. pcmcia_release_configuration(link->handle);
  611. return 0;
  612. }
  613. static int mgslpc_resume(struct pcmcia_device *dev)
  614. {
  615. dev_link_t *link = dev_to_instance(dev);
  616. MGSLPC_INFO *info = link->priv;
  617. link->state &= ~DEV_SUSPEND;
  618. if (link->state & DEV_CONFIG)
  619. pcmcia_request_configuration(link->handle, &link->conf);
  620. info->stop = 0;
  621. return 0;
  622. }
  623. static inline int mgslpc_paranoia_check(MGSLPC_INFO *info,
  624. char *name, const char *routine)
  625. {
  626. #ifdef MGSLPC_PARANOIA_CHECK
  627. static const char *badmagic =
  628. "Warning: bad magic number for mgsl struct (%s) in %s\n";
  629. static const char *badinfo =
  630. "Warning: null mgslpc_info for (%s) in %s\n";
  631. if (!info) {
  632. printk(badinfo, name, routine);
  633. return 1;
  634. }
  635. if (info->magic != MGSLPC_MAGIC) {
  636. printk(badmagic, name, routine);
  637. return 1;
  638. }
  639. #else
  640. if (!info)
  641. return 1;
  642. #endif
  643. return 0;
  644. }
  645. #define CMD_RXFIFO BIT7 // release current rx FIFO
  646. #define CMD_RXRESET BIT6 // receiver reset
  647. #define CMD_RXFIFO_READ BIT5
  648. #define CMD_START_TIMER BIT4
  649. #define CMD_TXFIFO BIT3 // release current tx FIFO
  650. #define CMD_TXEOM BIT1 // transmit end message
  651. #define CMD_TXRESET BIT0 // transmit reset
  652. static BOOLEAN wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
  653. {
  654. int i = 0;
  655. /* wait for command completion */
  656. while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
  657. udelay(1);
  658. if (i++ == 1000)
  659. return FALSE;
  660. }
  661. return TRUE;
  662. }
  663. static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
  664. {
  665. wait_command_complete(info, channel);
  666. write_reg(info, (unsigned char) (channel + CMDR), cmd);
  667. }
  668. static void tx_pause(struct tty_struct *tty)
  669. {
  670. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  671. unsigned long flags;
  672. if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
  673. return;
  674. if (debug_level >= DEBUG_LEVEL_INFO)
  675. printk("tx_pause(%s)\n",info->device_name);
  676. spin_lock_irqsave(&info->lock,flags);
  677. if (info->tx_enabled)
  678. tx_stop(info);
  679. spin_unlock_irqrestore(&info->lock,flags);
  680. }
  681. static void tx_release(struct tty_struct *tty)
  682. {
  683. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  684. unsigned long flags;
  685. if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
  686. return;
  687. if (debug_level >= DEBUG_LEVEL_INFO)
  688. printk("tx_release(%s)\n",info->device_name);
  689. spin_lock_irqsave(&info->lock,flags);
  690. if (!info->tx_enabled)
  691. tx_start(info);
  692. spin_unlock_irqrestore(&info->lock,flags);
  693. }
  694. /* Return next bottom half action to perform.
  695. * or 0 if nothing to do.
  696. */
  697. static int bh_action(MGSLPC_INFO *info)
  698. {
  699. unsigned long flags;
  700. int rc = 0;
  701. spin_lock_irqsave(&info->lock,flags);
  702. if (info->pending_bh & BH_RECEIVE) {
  703. info->pending_bh &= ~BH_RECEIVE;
  704. rc = BH_RECEIVE;
  705. } else if (info->pending_bh & BH_TRANSMIT) {
  706. info->pending_bh &= ~BH_TRANSMIT;
  707. rc = BH_TRANSMIT;
  708. } else if (info->pending_bh & BH_STATUS) {
  709. info->pending_bh &= ~BH_STATUS;
  710. rc = BH_STATUS;
  711. }
  712. if (!rc) {
  713. /* Mark BH routine as complete */
  714. info->bh_running = 0;
  715. info->bh_requested = 0;
  716. }
  717. spin_unlock_irqrestore(&info->lock,flags);
  718. return rc;
  719. }
  720. void bh_handler(void* Context)
  721. {
  722. MGSLPC_INFO *info = (MGSLPC_INFO*)Context;
  723. int action;
  724. if (!info)
  725. return;
  726. if (debug_level >= DEBUG_LEVEL_BH)
  727. printk( "%s(%d):bh_handler(%s) entry\n",
  728. __FILE__,__LINE__,info->device_name);
  729. info->bh_running = 1;
  730. while((action = bh_action(info)) != 0) {
  731. /* Process work item */
  732. if ( debug_level >= DEBUG_LEVEL_BH )
  733. printk( "%s(%d):bh_handler() work item action=%d\n",
  734. __FILE__,__LINE__,action);
  735. switch (action) {
  736. case BH_RECEIVE:
  737. while(rx_get_frame(info));
  738. break;
  739. case BH_TRANSMIT:
  740. bh_transmit(info);
  741. break;
  742. case BH_STATUS:
  743. bh_status(info);
  744. break;
  745. default:
  746. /* unknown work item ID */
  747. printk("Unknown work item ID=%08X!\n", action);
  748. break;
  749. }
  750. }
  751. if (debug_level >= DEBUG_LEVEL_BH)
  752. printk( "%s(%d):bh_handler(%s) exit\n",
  753. __FILE__,__LINE__,info->device_name);
  754. }
  755. void bh_transmit(MGSLPC_INFO *info)
  756. {
  757. struct tty_struct *tty = info->tty;
  758. if (debug_level >= DEBUG_LEVEL_BH)
  759. printk("bh_transmit() entry on %s\n", info->device_name);
  760. if (tty) {
  761. tty_wakeup(tty);
  762. wake_up_interruptible(&tty->write_wait);
  763. }
  764. }
  765. void bh_status(MGSLPC_INFO *info)
  766. {
  767. info->ri_chkcount = 0;
  768. info->dsr_chkcount = 0;
  769. info->dcd_chkcount = 0;
  770. info->cts_chkcount = 0;
  771. }
  772. /* eom: non-zero = end of frame */
  773. static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
  774. {
  775. unsigned char data[2];
  776. unsigned char fifo_count, read_count, i;
  777. RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
  778. if (debug_level >= DEBUG_LEVEL_ISR)
  779. printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
  780. if (!info->rx_enabled)
  781. return;
  782. if (info->rx_frame_count >= info->rx_buf_count) {
  783. /* no more free buffers */
  784. issue_command(info, CHA, CMD_RXRESET);
  785. info->pending_bh |= BH_RECEIVE;
  786. info->rx_overflow = 1;
  787. info->icount.buf_overrun++;
  788. return;
  789. }
  790. if (eom) {
  791. /* end of frame, get FIFO count from RBCL register */
  792. if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
  793. fifo_count = 32;
  794. } else
  795. fifo_count = 32;
  796. do {
  797. if (fifo_count == 1) {
  798. read_count = 1;
  799. data[0] = read_reg(info, CHA + RXFIFO);
  800. } else {
  801. read_count = 2;
  802. *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
  803. }
  804. fifo_count -= read_count;
  805. if (!fifo_count && eom)
  806. buf->status = data[--read_count];
  807. for (i = 0; i < read_count; i++) {
  808. if (buf->count >= info->max_frame_size) {
  809. /* frame too large, reset receiver and reset current buffer */
  810. issue_command(info, CHA, CMD_RXRESET);
  811. buf->count = 0;
  812. return;
  813. }
  814. *(buf->data + buf->count) = data[i];
  815. buf->count++;
  816. }
  817. } while (fifo_count);
  818. if (eom) {
  819. info->pending_bh |= BH_RECEIVE;
  820. info->rx_frame_count++;
  821. info->rx_put++;
  822. if (info->rx_put >= info->rx_buf_count)
  823. info->rx_put = 0;
  824. }
  825. issue_command(info, CHA, CMD_RXFIFO);
  826. }
  827. static void rx_ready_async(MGSLPC_INFO *info, int tcd)
  828. {
  829. unsigned char data, status;
  830. int fifo_count;
  831. struct tty_struct *tty = info->tty;
  832. struct mgsl_icount *icount = &info->icount;
  833. if (tcd) {
  834. /* early termination, get FIFO count from RBCL register */
  835. fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
  836. /* Zero fifo count could mean 0 or 32 bytes available.
  837. * If BIT5 of STAR is set then at least 1 byte is available.
  838. */
  839. if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
  840. fifo_count = 32;
  841. } else
  842. fifo_count = 32;
  843. /* Flush received async data to receive data buffer. */
  844. while (fifo_count) {
  845. data = read_reg(info, CHA + RXFIFO);
  846. status = read_reg(info, CHA + RXFIFO);
  847. fifo_count -= 2;
  848. if (tty->flip.count >= TTY_FLIPBUF_SIZE)
  849. break;
  850. *tty->flip.char_buf_ptr = data;
  851. icount->rx++;
  852. *tty->flip.flag_buf_ptr = 0;
  853. // if no frameing/crc error then save data
  854. // BIT7:parity error
  855. // BIT6:framing error
  856. if (status & (BIT7 + BIT6)) {
  857. if (status & BIT7)
  858. icount->parity++;
  859. else
  860. icount->frame++;
  861. /* discard char if tty control flags say so */
  862. if (status & info->ignore_status_mask)
  863. continue;
  864. status &= info->read_status_mask;
  865. if (status & BIT7)
  866. *tty->flip.flag_buf_ptr = TTY_PARITY;
  867. else if (status & BIT6)
  868. *tty->flip.flag_buf_ptr = TTY_FRAME;
  869. }
  870. tty->flip.flag_buf_ptr++;
  871. tty->flip.char_buf_ptr++;
  872. tty->flip.count++;
  873. }
  874. issue_command(info, CHA, CMD_RXFIFO);
  875. if (debug_level >= DEBUG_LEVEL_ISR) {
  876. printk("%s(%d):rx_ready_async count=%d\n",
  877. __FILE__,__LINE__,tty->flip.count);
  878. printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  879. __FILE__,__LINE__,icount->rx,icount->brk,
  880. icount->parity,icount->frame,icount->overrun);
  881. }
  882. if (tty->flip.count)
  883. tty_flip_buffer_push(tty);
  884. }
  885. static void tx_done(MGSLPC_INFO *info)
  886. {
  887. if (!info->tx_active)
  888. return;
  889. info->tx_active = 0;
  890. info->tx_aborting = 0;
  891. if (info->params.mode == MGSL_MODE_ASYNC)
  892. return;
  893. info->tx_count = info->tx_put = info->tx_get = 0;
  894. del_timer(&info->tx_timer);
  895. if (info->drop_rts_on_tx_done) {
  896. get_signals(info);
  897. if (info->serial_signals & SerialSignal_RTS) {
  898. info->serial_signals &= ~SerialSignal_RTS;
  899. set_signals(info);
  900. }
  901. info->drop_rts_on_tx_done = 0;
  902. }
  903. #ifdef CONFIG_HDLC
  904. if (info->netcount)
  905. hdlcdev_tx_done(info);
  906. else
  907. #endif
  908. {
  909. if (info->tty->stopped || info->tty->hw_stopped) {
  910. tx_stop(info);
  911. return;
  912. }
  913. info->pending_bh |= BH_TRANSMIT;
  914. }
  915. }
  916. static void tx_ready(MGSLPC_INFO *info)
  917. {
  918. unsigned char fifo_count = 32;
  919. int c;
  920. if (debug_level >= DEBUG_LEVEL_ISR)
  921. printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
  922. if (info->params.mode == MGSL_MODE_HDLC) {
  923. if (!info->tx_active)
  924. return;
  925. } else {
  926. if (info->tty->stopped || info->tty->hw_stopped) {
  927. tx_stop(info);
  928. return;
  929. }
  930. if (!info->tx_count)
  931. info->tx_active = 0;
  932. }
  933. if (!info->tx_count)
  934. return;
  935. while (info->tx_count && fifo_count) {
  936. c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
  937. if (c == 1) {
  938. write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
  939. } else {
  940. write_reg16(info, CHA + TXFIFO,
  941. *((unsigned short*)(info->tx_buf + info->tx_get)));
  942. }
  943. info->tx_count -= c;
  944. info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
  945. fifo_count -= c;
  946. }
  947. if (info->params.mode == MGSL_MODE_ASYNC) {
  948. if (info->tx_count < WAKEUP_CHARS)
  949. info->pending_bh |= BH_TRANSMIT;
  950. issue_command(info, CHA, CMD_TXFIFO);
  951. } else {
  952. if (info->tx_count)
  953. issue_command(info, CHA, CMD_TXFIFO);
  954. else
  955. issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
  956. }
  957. }
  958. static void cts_change(MGSLPC_INFO *info)
  959. {
  960. get_signals(info);
  961. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  962. irq_disable(info, CHB, IRQ_CTS);
  963. info->icount.cts++;
  964. if (info->serial_signals & SerialSignal_CTS)
  965. info->input_signal_events.cts_up++;
  966. else
  967. info->input_signal_events.cts_down++;
  968. wake_up_interruptible(&info->status_event_wait_q);
  969. wake_up_interruptible(&info->event_wait_q);
  970. if (info->flags & ASYNC_CTS_FLOW) {
  971. if (info->tty->hw_stopped) {
  972. if (info->serial_signals & SerialSignal_CTS) {
  973. if (debug_level >= DEBUG_LEVEL_ISR)
  974. printk("CTS tx start...");
  975. if (info->tty)
  976. info->tty->hw_stopped = 0;
  977. tx_start(info);
  978. info->pending_bh |= BH_TRANSMIT;
  979. return;
  980. }
  981. } else {
  982. if (!(info->serial_signals & SerialSignal_CTS)) {
  983. if (debug_level >= DEBUG_LEVEL_ISR)
  984. printk("CTS tx stop...");
  985. if (info->tty)
  986. info->tty->hw_stopped = 1;
  987. tx_stop(info);
  988. }
  989. }
  990. }
  991. info->pending_bh |= BH_STATUS;
  992. }
  993. static void dcd_change(MGSLPC_INFO *info)
  994. {
  995. get_signals(info);
  996. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  997. irq_disable(info, CHB, IRQ_DCD);
  998. info->icount.dcd++;
  999. if (info->serial_signals & SerialSignal_DCD) {
  1000. info->input_signal_events.dcd_up++;
  1001. }
  1002. else
  1003. info->input_signal_events.dcd_down++;
  1004. #ifdef CONFIG_HDLC
  1005. if (info->netcount)
  1006. hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, info->netdev);
  1007. #endif
  1008. wake_up_interruptible(&info->status_event_wait_q);
  1009. wake_up_interruptible(&info->event_wait_q);
  1010. if (info->flags & ASYNC_CHECK_CD) {
  1011. if (debug_level >= DEBUG_LEVEL_ISR)
  1012. printk("%s CD now %s...", info->device_name,
  1013. (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
  1014. if (info->serial_signals & SerialSignal_DCD)
  1015. wake_up_interruptible(&info->open_wait);
  1016. else {
  1017. if (debug_level >= DEBUG_LEVEL_ISR)
  1018. printk("doing serial hangup...");
  1019. if (info->tty)
  1020. tty_hangup(info->tty);
  1021. }
  1022. }
  1023. info->pending_bh |= BH_STATUS;
  1024. }
  1025. static void dsr_change(MGSLPC_INFO *info)
  1026. {
  1027. get_signals(info);
  1028. if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1029. port_irq_disable(info, PVR_DSR);
  1030. info->icount.dsr++;
  1031. if (info->serial_signals & SerialSignal_DSR)
  1032. info->input_signal_events.dsr_up++;
  1033. else
  1034. info->input_signal_events.dsr_down++;
  1035. wake_up_interruptible(&info->status_event_wait_q);
  1036. wake_up_interruptible(&info->event_wait_q);
  1037. info->pending_bh |= BH_STATUS;
  1038. }
  1039. static void ri_change(MGSLPC_INFO *info)
  1040. {
  1041. get_signals(info);
  1042. if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1043. port_irq_disable(info, PVR_RI);
  1044. info->icount.rng++;
  1045. if (info->serial_signals & SerialSignal_RI)
  1046. info->input_signal_events.ri_up++;
  1047. else
  1048. info->input_signal_events.ri_down++;
  1049. wake_up_interruptible(&info->status_event_wait_q);
  1050. wake_up_interruptible(&info->event_wait_q);
  1051. info->pending_bh |= BH_STATUS;
  1052. }
  1053. /* Interrupt service routine entry point.
  1054. *
  1055. * Arguments:
  1056. *
  1057. * irq interrupt number that caused interrupt
  1058. * dev_id device ID supplied during interrupt registration
  1059. * regs interrupted processor context
  1060. */
  1061. static irqreturn_t mgslpc_isr(int irq, void *dev_id, struct pt_regs * regs)
  1062. {
  1063. MGSLPC_INFO * info = (MGSLPC_INFO *)dev_id;
  1064. unsigned short isr;
  1065. unsigned char gis, pis;
  1066. int count=0;
  1067. if (debug_level >= DEBUG_LEVEL_ISR)
  1068. printk("mgslpc_isr(%d) entry.\n", irq);
  1069. if (!info)
  1070. return IRQ_NONE;
  1071. if (!(info->link.state & DEV_CONFIG))
  1072. return IRQ_HANDLED;
  1073. spin_lock(&info->lock);
  1074. while ((gis = read_reg(info, CHA + GIS))) {
  1075. if (debug_level >= DEBUG_LEVEL_ISR)
  1076. printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
  1077. if ((gis & 0x70) || count > 1000) {
  1078. printk("synclink_cs:hardware failed or ejected\n");
  1079. break;
  1080. }
  1081. count++;
  1082. if (gis & (BIT1 + BIT0)) {
  1083. isr = read_reg16(info, CHB + ISR);
  1084. if (isr & IRQ_DCD)
  1085. dcd_change(info);
  1086. if (isr & IRQ_CTS)
  1087. cts_change(info);
  1088. }
  1089. if (gis & (BIT3 + BIT2))
  1090. {
  1091. isr = read_reg16(info, CHA + ISR);
  1092. if (isr & IRQ_TIMER) {
  1093. info->irq_occurred = 1;
  1094. irq_disable(info, CHA, IRQ_TIMER);
  1095. }
  1096. /* receive IRQs */
  1097. if (isr & IRQ_EXITHUNT) {
  1098. info->icount.exithunt++;
  1099. wake_up_interruptible(&info->event_wait_q);
  1100. }
  1101. if (isr & IRQ_BREAK_ON) {
  1102. info->icount.brk++;
  1103. if (info->flags & ASYNC_SAK)
  1104. do_SAK(info->tty);
  1105. }
  1106. if (isr & IRQ_RXTIME) {
  1107. issue_command(info, CHA, CMD_RXFIFO_READ);
  1108. }
  1109. if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
  1110. if (info->params.mode == MGSL_MODE_HDLC)
  1111. rx_ready_hdlc(info, isr & IRQ_RXEOM);
  1112. else
  1113. rx_ready_async(info, isr & IRQ_RXEOM);
  1114. }
  1115. /* transmit IRQs */
  1116. if (isr & IRQ_UNDERRUN) {
  1117. if (info->tx_aborting)
  1118. info->icount.txabort++;
  1119. else
  1120. info->icount.txunder++;
  1121. tx_done(info);
  1122. }
  1123. else if (isr & IRQ_ALLSENT) {
  1124. info->icount.txok++;
  1125. tx_done(info);
  1126. }
  1127. else if (isr & IRQ_TXFIFO)
  1128. tx_ready(info);
  1129. }
  1130. if (gis & BIT7) {
  1131. pis = read_reg(info, CHA + PIS);
  1132. if (pis & BIT1)
  1133. dsr_change(info);
  1134. if (pis & BIT2)
  1135. ri_change(info);
  1136. }
  1137. }
  1138. /* Request bottom half processing if there's something
  1139. * for it to do and the bh is not already running
  1140. */
  1141. if (info->pending_bh && !info->bh_running && !info->bh_requested) {
  1142. if ( debug_level >= DEBUG_LEVEL_ISR )
  1143. printk("%s(%d):%s queueing bh task.\n",
  1144. __FILE__,__LINE__,info->device_name);
  1145. schedule_work(&info->task);
  1146. info->bh_requested = 1;
  1147. }
  1148. spin_unlock(&info->lock);
  1149. if (debug_level >= DEBUG_LEVEL_ISR)
  1150. printk("%s(%d):mgslpc_isr(%d)exit.\n",
  1151. __FILE__,__LINE__,irq);
  1152. return IRQ_HANDLED;
  1153. }
  1154. /* Initialize and start device.
  1155. */
  1156. static int startup(MGSLPC_INFO * info)
  1157. {
  1158. int retval = 0;
  1159. if (debug_level >= DEBUG_LEVEL_INFO)
  1160. printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
  1161. if (info->flags & ASYNC_INITIALIZED)
  1162. return 0;
  1163. if (!info->tx_buf) {
  1164. /* allocate a page of memory for a transmit buffer */
  1165. info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
  1166. if (!info->tx_buf) {
  1167. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  1168. __FILE__,__LINE__,info->device_name);
  1169. return -ENOMEM;
  1170. }
  1171. }
  1172. info->pending_bh = 0;
  1173. memset(&info->icount, 0, sizeof(info->icount));
  1174. init_timer(&info->tx_timer);
  1175. info->tx_timer.data = (unsigned long)info;
  1176. info->tx_timer.function = tx_timeout;
  1177. /* Allocate and claim adapter resources */
  1178. retval = claim_resources(info);
  1179. /* perform existance check and diagnostics */
  1180. if ( !retval )
  1181. retval = adapter_test(info);
  1182. if ( retval ) {
  1183. if (capable(CAP_SYS_ADMIN) && info->tty)
  1184. set_bit(TTY_IO_ERROR, &info->tty->flags);
  1185. release_resources(info);
  1186. return retval;
  1187. }
  1188. /* program hardware for current parameters */
  1189. mgslpc_change_params(info);
  1190. if (info->tty)
  1191. clear_bit(TTY_IO_ERROR, &info->tty->flags);
  1192. info->flags |= ASYNC_INITIALIZED;
  1193. return 0;
  1194. }
  1195. /* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
  1196. */
  1197. static void shutdown(MGSLPC_INFO * info)
  1198. {
  1199. unsigned long flags;
  1200. if (!(info->flags & ASYNC_INITIALIZED))
  1201. return;
  1202. if (debug_level >= DEBUG_LEVEL_INFO)
  1203. printk("%s(%d):mgslpc_shutdown(%s)\n",
  1204. __FILE__,__LINE__, info->device_name );
  1205. /* clear status wait queue because status changes */
  1206. /* can't happen after shutting down the hardware */
  1207. wake_up_interruptible(&info->status_event_wait_q);
  1208. wake_up_interruptible(&info->event_wait_q);
  1209. del_timer(&info->tx_timer);
  1210. if (info->tx_buf) {
  1211. free_page((unsigned long) info->tx_buf);
  1212. info->tx_buf = NULL;
  1213. }
  1214. spin_lock_irqsave(&info->lock,flags);
  1215. rx_stop(info);
  1216. tx_stop(info);
  1217. /* TODO:disable interrupts instead of reset to preserve signal states */
  1218. reset_device(info);
  1219. if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
  1220. info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
  1221. set_signals(info);
  1222. }
  1223. spin_unlock_irqrestore(&info->lock,flags);
  1224. release_resources(info);
  1225. if (info->tty)
  1226. set_bit(TTY_IO_ERROR, &info->tty->flags);
  1227. info->flags &= ~ASYNC_INITIALIZED;
  1228. }
  1229. static void mgslpc_program_hw(MGSLPC_INFO *info)
  1230. {
  1231. unsigned long flags;
  1232. spin_lock_irqsave(&info->lock,flags);
  1233. rx_stop(info);
  1234. tx_stop(info);
  1235. info->tx_count = info->tx_put = info->tx_get = 0;
  1236. if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
  1237. hdlc_mode(info);
  1238. else
  1239. async_mode(info);
  1240. set_signals(info);
  1241. info->dcd_chkcount = 0;
  1242. info->cts_chkcount = 0;
  1243. info->ri_chkcount = 0;
  1244. info->dsr_chkcount = 0;
  1245. irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
  1246. port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
  1247. get_signals(info);
  1248. if (info->netcount || info->tty->termios->c_cflag & CREAD)
  1249. rx_start(info);
  1250. spin_unlock_irqrestore(&info->lock,flags);
  1251. }
  1252. /* Reconfigure adapter based on new parameters
  1253. */
  1254. static void mgslpc_change_params(MGSLPC_INFO *info)
  1255. {
  1256. unsigned cflag;
  1257. int bits_per_char;
  1258. if (!info->tty || !info->tty->termios)
  1259. return;
  1260. if (debug_level >= DEBUG_LEVEL_INFO)
  1261. printk("%s(%d):mgslpc_change_params(%s)\n",
  1262. __FILE__,__LINE__, info->device_name );
  1263. cflag = info->tty->termios->c_cflag;
  1264. /* if B0 rate (hangup) specified then negate DTR and RTS */
  1265. /* otherwise assert DTR and RTS */
  1266. if (cflag & CBAUD)
  1267. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  1268. else
  1269. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1270. /* byte size and parity */
  1271. switch (cflag & CSIZE) {
  1272. case CS5: info->params.data_bits = 5; break;
  1273. case CS6: info->params.data_bits = 6; break;
  1274. case CS7: info->params.data_bits = 7; break;
  1275. case CS8: info->params.data_bits = 8; break;
  1276. default: info->params.data_bits = 7; break;
  1277. }
  1278. if (cflag & CSTOPB)
  1279. info->params.stop_bits = 2;
  1280. else
  1281. info->params.stop_bits = 1;
  1282. info->params.parity = ASYNC_PARITY_NONE;
  1283. if (cflag & PARENB) {
  1284. if (cflag & PARODD)
  1285. info->params.parity = ASYNC_PARITY_ODD;
  1286. else
  1287. info->params.parity = ASYNC_PARITY_EVEN;
  1288. #ifdef CMSPAR
  1289. if (cflag & CMSPAR)
  1290. info->params.parity = ASYNC_PARITY_SPACE;
  1291. #endif
  1292. }
  1293. /* calculate number of jiffies to transmit a full
  1294. * FIFO (32 bytes) at specified data rate
  1295. */
  1296. bits_per_char = info->params.data_bits +
  1297. info->params.stop_bits + 1;
  1298. /* if port data rate is set to 460800 or less then
  1299. * allow tty settings to override, otherwise keep the
  1300. * current data rate.
  1301. */
  1302. if (info->params.data_rate <= 460800) {
  1303. info->params.data_rate = tty_get_baud_rate(info->tty);
  1304. }
  1305. if ( info->params.data_rate ) {
  1306. info->timeout = (32*HZ*bits_per_char) /
  1307. info->params.data_rate;
  1308. }
  1309. info->timeout += HZ/50; /* Add .02 seconds of slop */
  1310. if (cflag & CRTSCTS)
  1311. info->flags |= ASYNC_CTS_FLOW;
  1312. else
  1313. info->flags &= ~ASYNC_CTS_FLOW;
  1314. if (cflag & CLOCAL)
  1315. info->flags &= ~ASYNC_CHECK_CD;
  1316. else
  1317. info->flags |= ASYNC_CHECK_CD;
  1318. /* process tty input control flags */
  1319. info->read_status_mask = 0;
  1320. if (I_INPCK(info->tty))
  1321. info->read_status_mask |= BIT7 | BIT6;
  1322. if (I_IGNPAR(info->tty))
  1323. info->ignore_status_mask |= BIT7 | BIT6;
  1324. mgslpc_program_hw(info);
  1325. }
  1326. /* Add a character to the transmit buffer
  1327. */
  1328. static void mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
  1329. {
  1330. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1331. unsigned long flags;
  1332. if (debug_level >= DEBUG_LEVEL_INFO) {
  1333. printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
  1334. __FILE__,__LINE__,ch,info->device_name);
  1335. }
  1336. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
  1337. return;
  1338. if (!tty || !info->tx_buf)
  1339. return;
  1340. spin_lock_irqsave(&info->lock,flags);
  1341. if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
  1342. if (info->tx_count < TXBUFSIZE - 1) {
  1343. info->tx_buf[info->tx_put++] = ch;
  1344. info->tx_put &= TXBUFSIZE-1;
  1345. info->tx_count++;
  1346. }
  1347. }
  1348. spin_unlock_irqrestore(&info->lock,flags);
  1349. }
  1350. /* Enable transmitter so remaining characters in the
  1351. * transmit buffer are sent.
  1352. */
  1353. static void mgslpc_flush_chars(struct tty_struct *tty)
  1354. {
  1355. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1356. unsigned long flags;
  1357. if (debug_level >= DEBUG_LEVEL_INFO)
  1358. printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
  1359. __FILE__,__LINE__,info->device_name,info->tx_count);
  1360. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
  1361. return;
  1362. if (info->tx_count <= 0 || tty->stopped ||
  1363. tty->hw_stopped || !info->tx_buf)
  1364. return;
  1365. if (debug_level >= DEBUG_LEVEL_INFO)
  1366. printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
  1367. __FILE__,__LINE__,info->device_name);
  1368. spin_lock_irqsave(&info->lock,flags);
  1369. if (!info->tx_active)
  1370. tx_start(info);
  1371. spin_unlock_irqrestore(&info->lock,flags);
  1372. }
  1373. /* Send a block of data
  1374. *
  1375. * Arguments:
  1376. *
  1377. * tty pointer to tty information structure
  1378. * buf pointer to buffer containing send data
  1379. * count size of send data in bytes
  1380. *
  1381. * Returns: number of characters written
  1382. */
  1383. static int mgslpc_write(struct tty_struct * tty,
  1384. const unsigned char *buf, int count)
  1385. {
  1386. int c, ret = 0;
  1387. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1388. unsigned long flags;
  1389. if (debug_level >= DEBUG_LEVEL_INFO)
  1390. printk( "%s(%d):mgslpc_write(%s) count=%d\n",
  1391. __FILE__,__LINE__,info->device_name,count);
  1392. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
  1393. !tty || !info->tx_buf)
  1394. goto cleanup;
  1395. if (info->params.mode == MGSL_MODE_HDLC) {
  1396. if (count > TXBUFSIZE) {
  1397. ret = -EIO;
  1398. goto cleanup;
  1399. }
  1400. if (info->tx_active)
  1401. goto cleanup;
  1402. else if (info->tx_count)
  1403. goto start;
  1404. }
  1405. for (;;) {
  1406. c = min(count,
  1407. min(TXBUFSIZE - info->tx_count - 1,
  1408. TXBUFSIZE - info->tx_put));
  1409. if (c <= 0)
  1410. break;
  1411. memcpy(info->tx_buf + info->tx_put, buf, c);
  1412. spin_lock_irqsave(&info->lock,flags);
  1413. info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
  1414. info->tx_count += c;
  1415. spin_unlock_irqrestore(&info->lock,flags);
  1416. buf += c;
  1417. count -= c;
  1418. ret += c;
  1419. }
  1420. start:
  1421. if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
  1422. spin_lock_irqsave(&info->lock,flags);
  1423. if (!info->tx_active)
  1424. tx_start(info);
  1425. spin_unlock_irqrestore(&info->lock,flags);
  1426. }
  1427. cleanup:
  1428. if (debug_level >= DEBUG_LEVEL_INFO)
  1429. printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
  1430. __FILE__,__LINE__,info->device_name,ret);
  1431. return ret;
  1432. }
  1433. /* Return the count of free bytes in transmit buffer
  1434. */
  1435. static int mgslpc_write_room(struct tty_struct *tty)
  1436. {
  1437. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1438. int ret;
  1439. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
  1440. return 0;
  1441. if (info->params.mode == MGSL_MODE_HDLC) {
  1442. /* HDLC (frame oriented) mode */
  1443. if (info->tx_active)
  1444. return 0;
  1445. else
  1446. return HDLC_MAX_FRAME_SIZE;
  1447. } else {
  1448. ret = TXBUFSIZE - info->tx_count - 1;
  1449. if (ret < 0)
  1450. ret = 0;
  1451. }
  1452. if (debug_level >= DEBUG_LEVEL_INFO)
  1453. printk("%s(%d):mgslpc_write_room(%s)=%d\n",
  1454. __FILE__,__LINE__, info->device_name, ret);
  1455. return ret;
  1456. }
  1457. /* Return the count of bytes in transmit buffer
  1458. */
  1459. static int mgslpc_chars_in_buffer(struct tty_struct *tty)
  1460. {
  1461. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1462. int rc;
  1463. if (debug_level >= DEBUG_LEVEL_INFO)
  1464. printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
  1465. __FILE__,__LINE__, info->device_name );
  1466. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
  1467. return 0;
  1468. if (info->params.mode == MGSL_MODE_HDLC)
  1469. rc = info->tx_active ? info->max_frame_size : 0;
  1470. else
  1471. rc = info->tx_count;
  1472. if (debug_level >= DEBUG_LEVEL_INFO)
  1473. printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
  1474. __FILE__,__LINE__, info->device_name, rc);
  1475. return rc;
  1476. }
  1477. /* Discard all data in the send buffer
  1478. */
  1479. static void mgslpc_flush_buffer(struct tty_struct *tty)
  1480. {
  1481. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1482. unsigned long flags;
  1483. if (debug_level >= DEBUG_LEVEL_INFO)
  1484. printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
  1485. __FILE__,__LINE__, info->device_name );
  1486. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
  1487. return;
  1488. spin_lock_irqsave(&info->lock,flags);
  1489. info->tx_count = info->tx_put = info->tx_get = 0;
  1490. del_timer(&info->tx_timer);
  1491. spin_unlock_irqrestore(&info->lock,flags);
  1492. wake_up_interruptible(&tty->write_wait);
  1493. tty_wakeup(tty);
  1494. }
  1495. /* Send a high-priority XON/XOFF character
  1496. */
  1497. static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
  1498. {
  1499. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1500. unsigned long flags;
  1501. if (debug_level >= DEBUG_LEVEL_INFO)
  1502. printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
  1503. __FILE__,__LINE__, info->device_name, ch );
  1504. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
  1505. return;
  1506. info->x_char = ch;
  1507. if (ch) {
  1508. spin_lock_irqsave(&info->lock,flags);
  1509. if (!info->tx_enabled)
  1510. tx_start(info);
  1511. spin_unlock_irqrestore(&info->lock,flags);
  1512. }
  1513. }
  1514. /* Signal remote device to throttle send data (our receive data)
  1515. */
  1516. static void mgslpc_throttle(struct tty_struct * tty)
  1517. {
  1518. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1519. unsigned long flags;
  1520. if (debug_level >= DEBUG_LEVEL_INFO)
  1521. printk("%s(%d):mgslpc_throttle(%s) entry\n",
  1522. __FILE__,__LINE__, info->device_name );
  1523. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
  1524. return;
  1525. if (I_IXOFF(tty))
  1526. mgslpc_send_xchar(tty, STOP_CHAR(tty));
  1527. if (tty->termios->c_cflag & CRTSCTS) {
  1528. spin_lock_irqsave(&info->lock,flags);
  1529. info->serial_signals &= ~SerialSignal_RTS;
  1530. set_signals(info);
  1531. spin_unlock_irqrestore(&info->lock,flags);
  1532. }
  1533. }
  1534. /* Signal remote device to stop throttling send data (our receive data)
  1535. */
  1536. static void mgslpc_unthrottle(struct tty_struct * tty)
  1537. {
  1538. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1539. unsigned long flags;
  1540. if (debug_level >= DEBUG_LEVEL_INFO)
  1541. printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
  1542. __FILE__,__LINE__, info->device_name );
  1543. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
  1544. return;
  1545. if (I_IXOFF(tty)) {
  1546. if (info->x_char)
  1547. info->x_char = 0;
  1548. else
  1549. mgslpc_send_xchar(tty, START_CHAR(tty));
  1550. }
  1551. if (tty->termios->c_cflag & CRTSCTS) {
  1552. spin_lock_irqsave(&info->lock,flags);
  1553. info->serial_signals |= SerialSignal_RTS;
  1554. set_signals(info);
  1555. spin_unlock_irqrestore(&info->lock,flags);
  1556. }
  1557. }
  1558. /* get the current serial statistics
  1559. */
  1560. static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
  1561. {
  1562. int err;
  1563. if (debug_level >= DEBUG_LEVEL_INFO)
  1564. printk("get_params(%s)\n", info->device_name);
  1565. if (!user_icount) {
  1566. memset(&info->icount, 0, sizeof(info->icount));
  1567. } else {
  1568. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  1569. if (err)
  1570. return -EFAULT;
  1571. }
  1572. return 0;
  1573. }
  1574. /* get the current serial parameters
  1575. */
  1576. static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
  1577. {
  1578. int err;
  1579. if (debug_level >= DEBUG_LEVEL_INFO)
  1580. printk("get_params(%s)\n", info->device_name);
  1581. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  1582. if (err)
  1583. return -EFAULT;
  1584. return 0;
  1585. }
  1586. /* set the serial parameters
  1587. *
  1588. * Arguments:
  1589. *
  1590. * info pointer to device instance data
  1591. * new_params user buffer containing new serial params
  1592. *
  1593. * Returns: 0 if success, otherwise error code
  1594. */
  1595. static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params)
  1596. {
  1597. unsigned long flags;
  1598. MGSL_PARAMS tmp_params;
  1599. int err;
  1600. if (debug_level >= DEBUG_LEVEL_INFO)
  1601. printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
  1602. info->device_name );
  1603. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  1604. if (err) {
  1605. if ( debug_level >= DEBUG_LEVEL_INFO )
  1606. printk( "%s(%d):set_params(%s) user buffer copy failed\n",
  1607. __FILE__,__LINE__,info->device_name);
  1608. return -EFAULT;
  1609. }
  1610. spin_lock_irqsave(&info->lock,flags);
  1611. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  1612. spin_unlock_irqrestore(&info->lock,flags);
  1613. mgslpc_change_params(info);
  1614. return 0;
  1615. }
  1616. static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
  1617. {
  1618. int err;
  1619. if (debug_level >= DEBUG_LEVEL_INFO)
  1620. printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
  1621. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  1622. if (err)
  1623. return -EFAULT;
  1624. return 0;
  1625. }
  1626. static int set_txidle(MGSLPC_INFO * info, int idle_mode)
  1627. {
  1628. unsigned long flags;
  1629. if (debug_level >= DEBUG_LEVEL_INFO)
  1630. printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
  1631. spin_lock_irqsave(&info->lock,flags);
  1632. info->idle_mode = idle_mode;
  1633. tx_set_idle(info);
  1634. spin_unlock_irqrestore(&info->lock,flags);
  1635. return 0;
  1636. }
  1637. static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
  1638. {
  1639. int err;
  1640. if (debug_level >= DEBUG_LEVEL_INFO)
  1641. printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
  1642. COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
  1643. if (err)
  1644. return -EFAULT;
  1645. return 0;
  1646. }
  1647. static int set_interface(MGSLPC_INFO * info, int if_mode)
  1648. {
  1649. unsigned long flags;
  1650. unsigned char val;
  1651. if (debug_level >= DEBUG_LEVEL_INFO)
  1652. printk("set_interface(%s,%d)\n", info->device_name, if_mode);
  1653. spin_lock_irqsave(&info->lock,flags);
  1654. info->if_mode = if_mode;
  1655. val = read_reg(info, PVR) & 0x0f;
  1656. switch (info->if_mode)
  1657. {
  1658. case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
  1659. case MGSL_INTERFACE_V35: val |= PVR_V35; break;
  1660. case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
  1661. }
  1662. write_reg(info, PVR, val);
  1663. spin_unlock_irqrestore(&info->lock,flags);
  1664. return 0;
  1665. }
  1666. static int set_txenable(MGSLPC_INFO * info, int enable)
  1667. {
  1668. unsigned long flags;
  1669. if (debug_level >= DEBUG_LEVEL_INFO)
  1670. printk("set_txenable(%s,%d)\n", info->device_name, enable);
  1671. spin_lock_irqsave(&info->lock,flags);
  1672. if (enable) {
  1673. if (!info->tx_enabled)
  1674. tx_start(info);
  1675. } else {
  1676. if (info->tx_enabled)
  1677. tx_stop(info);
  1678. }
  1679. spin_unlock_irqrestore(&info->lock,flags);
  1680. return 0;
  1681. }
  1682. static int tx_abort(MGSLPC_INFO * info)
  1683. {
  1684. unsigned long flags;
  1685. if (debug_level >= DEBUG_LEVEL_INFO)
  1686. printk("tx_abort(%s)\n", info->device_name);
  1687. spin_lock_irqsave(&info->lock,flags);
  1688. if (info->tx_active && info->tx_count &&
  1689. info->params.mode == MGSL_MODE_HDLC) {
  1690. /* clear data count so FIFO is not filled on next IRQ.
  1691. * This results in underrun and abort transmission.
  1692. */
  1693. info->tx_count = info->tx_put = info->tx_get = 0;
  1694. info->tx_aborting = TRUE;
  1695. }
  1696. spin_unlock_irqrestore(&info->lock,flags);
  1697. return 0;
  1698. }
  1699. static int set_rxenable(MGSLPC_INFO * info, int enable)
  1700. {
  1701. unsigned long flags;
  1702. if (debug_level >= DEBUG_LEVEL_INFO)
  1703. printk("set_rxenable(%s,%d)\n", info->device_name, enable);
  1704. spin_lock_irqsave(&info->lock,flags);
  1705. if (enable) {
  1706. if (!info->rx_enabled)
  1707. rx_start(info);
  1708. } else {
  1709. if (info->rx_enabled)
  1710. rx_stop(info);
  1711. }
  1712. spin_unlock_irqrestore(&info->lock,flags);
  1713. return 0;
  1714. }
  1715. /* wait for specified event to occur
  1716. *
  1717. * Arguments: info pointer to device instance data
  1718. * mask pointer to bitmask of events to wait for
  1719. * Return Value: 0 if successful and bit mask updated with
  1720. * of events triggerred,
  1721. * otherwise error code
  1722. */
  1723. static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
  1724. {
  1725. unsigned long flags;
  1726. int s;
  1727. int rc=0;
  1728. struct mgsl_icount cprev, cnow;
  1729. int events;
  1730. int mask;
  1731. struct _input_signal_events oldsigs, newsigs;
  1732. DECLARE_WAITQUEUE(wait, current);
  1733. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  1734. if (rc)
  1735. return -EFAULT;
  1736. if (debug_level >= DEBUG_LEVEL_INFO)
  1737. printk("wait_events(%s,%d)\n", info->device_name, mask);
  1738. spin_lock_irqsave(&info->lock,flags);
  1739. /* return immediately if state matches requested events */
  1740. get_signals(info);
  1741. s = info->serial_signals;
  1742. events = mask &
  1743. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  1744. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  1745. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  1746. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  1747. if (events) {
  1748. spin_unlock_irqrestore(&info->lock,flags);
  1749. goto exit;
  1750. }
  1751. /* save current irq counts */
  1752. cprev = info->icount;
  1753. oldsigs = info->input_signal_events;
  1754. if ((info->params.mode == MGSL_MODE_HDLC) &&
  1755. (mask & MgslEvent_ExitHuntMode))
  1756. irq_enable(info, CHA, IRQ_EXITHUNT);
  1757. set_current_state(TASK_INTERRUPTIBLE);
  1758. add_wait_queue(&info->event_wait_q, &wait);
  1759. spin_unlock_irqrestore(&info->lock,flags);
  1760. for(;;) {
  1761. schedule();
  1762. if (signal_pending(current)) {
  1763. rc = -ERESTARTSYS;
  1764. break;
  1765. }
  1766. /* get current irq counts */
  1767. spin_lock_irqsave(&info->lock,flags);
  1768. cnow = info->icount;
  1769. newsigs = info->input_signal_events;
  1770. set_current_state(TASK_INTERRUPTIBLE);
  1771. spin_unlock_irqrestore(&info->lock,flags);
  1772. /* if no change, wait aborted for some reason */
  1773. if (newsigs.dsr_up == oldsigs.dsr_up &&
  1774. newsigs.dsr_down == oldsigs.dsr_down &&
  1775. newsigs.dcd_up == oldsigs.dcd_up &&
  1776. newsigs.dcd_down == oldsigs.dcd_down &&
  1777. newsigs.cts_up == oldsigs.cts_up &&
  1778. newsigs.cts_down == oldsigs.cts_down &&
  1779. newsigs.ri_up == oldsigs.ri_up &&
  1780. newsigs.ri_down == oldsigs.ri_down &&
  1781. cnow.exithunt == cprev.exithunt &&
  1782. cnow.rxidle == cprev.rxidle) {
  1783. rc = -EIO;
  1784. break;
  1785. }
  1786. events = mask &
  1787. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  1788. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  1789. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  1790. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  1791. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  1792. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  1793. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  1794. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  1795. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  1796. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  1797. if (events)
  1798. break;
  1799. cprev = cnow;
  1800. oldsigs = newsigs;
  1801. }
  1802. remove_wait_queue(&info->event_wait_q, &wait);
  1803. set_current_state(TASK_RUNNING);
  1804. if (mask & MgslEvent_ExitHuntMode) {
  1805. spin_lock_irqsave(&info->lock,flags);
  1806. if (!waitqueue_active(&info->event_wait_q))
  1807. irq_disable(info, CHA, IRQ_EXITHUNT);
  1808. spin_unlock_irqrestore(&info->lock,flags);
  1809. }
  1810. exit:
  1811. if (rc == 0)
  1812. PUT_USER(rc, events, mask_ptr);
  1813. return rc;
  1814. }
  1815. static int modem_input_wait(MGSLPC_INFO *info,int arg)
  1816. {
  1817. unsigned long flags;
  1818. int rc;
  1819. struct mgsl_icount cprev, cnow;
  1820. DECLARE_WAITQUEUE(wait, current);
  1821. /* save current irq counts */
  1822. spin_lock_irqsave(&info->lock,flags);
  1823. cprev = info->icount;
  1824. add_wait_queue(&info->status_event_wait_q, &wait);
  1825. set_current_state(TASK_INTERRUPTIBLE);
  1826. spin_unlock_irqrestore(&info->lock,flags);
  1827. for(;;) {
  1828. schedule();
  1829. if (signal_pending(current)) {
  1830. rc = -ERESTARTSYS;
  1831. break;
  1832. }
  1833. /* get new irq counts */
  1834. spin_lock_irqsave(&info->lock,flags);
  1835. cnow = info->icount;
  1836. set_current_state(TASK_INTERRUPTIBLE);
  1837. spin_unlock_irqrestore(&info->lock,flags);
  1838. /* if no change, wait aborted for some reason */
  1839. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  1840. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  1841. rc = -EIO;
  1842. break;
  1843. }
  1844. /* check for change in caller specified modem input */
  1845. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  1846. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  1847. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  1848. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  1849. rc = 0;
  1850. break;
  1851. }
  1852. cprev = cnow;
  1853. }
  1854. remove_wait_queue(&info->status_event_wait_q, &wait);
  1855. set_current_state(TASK_RUNNING);
  1856. return rc;
  1857. }
  1858. /* return the state of the serial control and status signals
  1859. */
  1860. static int tiocmget(struct tty_struct *tty, struct file *file)
  1861. {
  1862. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1863. unsigned int result;
  1864. unsigned long flags;
  1865. spin_lock_irqsave(&info->lock,flags);
  1866. get_signals(info);
  1867. spin_unlock_irqrestore(&info->lock,flags);
  1868. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  1869. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  1870. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  1871. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  1872. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  1873. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  1874. if (debug_level >= DEBUG_LEVEL_INFO)
  1875. printk("%s(%d):%s tiocmget() value=%08X\n",
  1876. __FILE__,__LINE__, info->device_name, result );
  1877. return result;
  1878. }
  1879. /* set modem control signals (DTR/RTS)
  1880. */
  1881. static int tiocmset(struct tty_struct *tty, struct file *file,
  1882. unsigned int set, unsigned int clear)
  1883. {
  1884. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1885. unsigned long flags;
  1886. if (debug_level >= DEBUG_LEVEL_INFO)
  1887. printk("%s(%d):%s tiocmset(%x,%x)\n",
  1888. __FILE__,__LINE__,info->device_name, set, clear);
  1889. if (set & TIOCM_RTS)
  1890. info->serial_signals |= SerialSignal_RTS;
  1891. if (set & TIOCM_DTR)
  1892. info->serial_signals |= SerialSignal_DTR;
  1893. if (clear & TIOCM_RTS)
  1894. info->serial_signals &= ~SerialSignal_RTS;
  1895. if (clear & TIOCM_DTR)
  1896. info->serial_signals &= ~SerialSignal_DTR;
  1897. spin_lock_irqsave(&info->lock,flags);
  1898. set_signals(info);
  1899. spin_unlock_irqrestore(&info->lock,flags);
  1900. return 0;
  1901. }
  1902. /* Set or clear transmit break condition
  1903. *
  1904. * Arguments: tty pointer to tty instance data
  1905. * break_state -1=set break condition, 0=clear
  1906. */
  1907. static void mgslpc_break(struct tty_struct *tty, int break_state)
  1908. {
  1909. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1910. unsigned long flags;
  1911. if (debug_level >= DEBUG_LEVEL_INFO)
  1912. printk("%s(%d):mgslpc_break(%s,%d)\n",
  1913. __FILE__,__LINE__, info->device_name, break_state);
  1914. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
  1915. return;
  1916. spin_lock_irqsave(&info->lock,flags);
  1917. if (break_state == -1)
  1918. set_reg_bits(info, CHA+DAFO, BIT6);
  1919. else
  1920. clear_reg_bits(info, CHA+DAFO, BIT6);
  1921. spin_unlock_irqrestore(&info->lock,flags);
  1922. }
  1923. /* Service an IOCTL request
  1924. *
  1925. * Arguments:
  1926. *
  1927. * tty pointer to tty instance data
  1928. * file pointer to associated file object for device
  1929. * cmd IOCTL command code
  1930. * arg command argument/context
  1931. *
  1932. * Return Value: 0 if success, otherwise error code
  1933. */
  1934. static int mgslpc_ioctl(struct tty_struct *tty, struct file * file,
  1935. unsigned int cmd, unsigned long arg)
  1936. {
  1937. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1938. if (debug_level >= DEBUG_LEVEL_INFO)
  1939. printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
  1940. info->device_name, cmd );
  1941. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
  1942. return -ENODEV;
  1943. if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
  1944. (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
  1945. if (tty->flags & (1 << TTY_IO_ERROR))
  1946. return -EIO;
  1947. }
  1948. return ioctl_common(info, cmd, arg);
  1949. }
  1950. int ioctl_common(MGSLPC_INFO *info, unsigned int cmd, unsigned long arg)
  1951. {
  1952. int error;
  1953. struct mgsl_icount cnow; /* kernel counter temps */
  1954. struct serial_icounter_struct __user *p_cuser; /* user space */
  1955. void __user *argp = (void __user *)arg;
  1956. unsigned long flags;
  1957. switch (cmd) {
  1958. case MGSL_IOCGPARAMS:
  1959. return get_params(info, argp);
  1960. case MGSL_IOCSPARAMS:
  1961. return set_params(info, argp);
  1962. case MGSL_IOCGTXIDLE:
  1963. return get_txidle(info, argp);
  1964. case MGSL_IOCSTXIDLE:
  1965. return set_txidle(info, (int)arg);
  1966. case MGSL_IOCGIF:
  1967. return get_interface(info, argp);
  1968. case MGSL_IOCSIF:
  1969. return set_interface(info,(int)arg);
  1970. case MGSL_IOCTXENABLE:
  1971. return set_txenable(info,(int)arg);
  1972. case MGSL_IOCRXENABLE:
  1973. return set_rxenable(info,(int)arg);
  1974. case MGSL_IOCTXABORT:
  1975. return tx_abort(info);
  1976. case MGSL_IOCGSTATS:
  1977. return get_stats(info, argp);
  1978. case MGSL_IOCWAITEVENT:
  1979. return wait_events(info, argp);
  1980. case TIOCMIWAIT:
  1981. return modem_input_wait(info,(int)arg);
  1982. case TIOCGICOUNT:
  1983. spin_lock_irqsave(&info->lock,flags);
  1984. cnow = info->icount;
  1985. spin_unlock_irqrestore(&info->lock,flags);
  1986. p_cuser = argp;
  1987. PUT_USER(error,cnow.cts, &p_cuser->cts);
  1988. if (error) return error;
  1989. PUT_USER(error,cnow.dsr, &p_cuser->dsr);
  1990. if (error) return error;
  1991. PUT_USER(error,cnow.rng, &p_cuser->rng);
  1992. if (error) return error;
  1993. PUT_USER(error,cnow.dcd, &p_cuser->dcd);
  1994. if (error) return error;
  1995. PUT_USER(error,cnow.rx, &p_cuser->rx);
  1996. if (error) return error;
  1997. PUT_USER(error,cnow.tx, &p_cuser->tx);
  1998. if (error) return error;
  1999. PUT_USER(error,cnow.frame, &p_cuser->frame);
  2000. if (error) return error;
  2001. PUT_USER(error,cnow.overrun, &p_cuser->overrun);
  2002. if (error) return error;
  2003. PUT_USER(error,cnow.parity, &p_cuser->parity);
  2004. if (error) return error;
  2005. PUT_USER(error,cnow.brk, &p_cuser->brk);
  2006. if (error) return error;
  2007. PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
  2008. if (error) return error;
  2009. return 0;
  2010. default:
  2011. return -ENOIOCTLCMD;
  2012. }
  2013. return 0;
  2014. }
  2015. /* Set new termios settings
  2016. *
  2017. * Arguments:
  2018. *
  2019. * tty pointer to tty structure
  2020. * termios pointer to buffer to hold returned old termios
  2021. */
  2022. static void mgslpc_set_termios(struct tty_struct *tty, struct termios *old_termios)
  2023. {
  2024. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  2025. unsigned long flags;
  2026. if (debug_level >= DEBUG_LEVEL_INFO)
  2027. printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
  2028. tty->driver->name );
  2029. /* just return if nothing has changed */
  2030. if ((tty->termios->c_cflag == old_termios->c_cflag)
  2031. && (RELEVANT_IFLAG(tty->termios->c_iflag)
  2032. == RELEVANT_IFLAG(old_termios->c_iflag)))
  2033. return;
  2034. mgslpc_change_params(info);
  2035. /* Handle transition to B0 status */
  2036. if (old_termios->c_cflag & CBAUD &&
  2037. !(tty->termios->c_cflag & CBAUD)) {
  2038. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  2039. spin_lock_irqsave(&info->lock,flags);
  2040. set_signals(info);
  2041. spin_unlock_irqrestore(&info->lock,flags);
  2042. }
  2043. /* Handle transition away from B0 status */
  2044. if (!(old_termios->c_cflag & CBAUD) &&
  2045. tty->termios->c_cflag & CBAUD) {
  2046. info->serial_signals |= SerialSignal_DTR;
  2047. if (!(tty->termios->c_cflag & CRTSCTS) ||
  2048. !test_bit(TTY_THROTTLED, &tty->flags)) {
  2049. info->serial_signals |= SerialSignal_RTS;
  2050. }
  2051. spin_lock_irqsave(&info->lock,flags);
  2052. set_signals(info);
  2053. spin_unlock_irqrestore(&info->lock,flags);
  2054. }
  2055. /* Handle turning off CRTSCTS */
  2056. if (old_termios->c_cflag & CRTSCTS &&
  2057. !(tty->termios->c_cflag & CRTSCTS)) {
  2058. tty->hw_stopped = 0;
  2059. tx_release(tty);
  2060. }
  2061. }
  2062. static void mgslpc_close(struct tty_struct *tty, struct file * filp)
  2063. {
  2064. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2065. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
  2066. return;
  2067. if (debug_level >= DEBUG_LEVEL_INFO)
  2068. printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
  2069. __FILE__,__LINE__, info->device_name, info->count);
  2070. if (!info->count)
  2071. return;
  2072. if (tty_hung_up_p(filp))
  2073. goto cleanup;
  2074. if ((tty->count == 1) && (info->count != 1)) {
  2075. /*
  2076. * tty->count is 1 and the tty structure will be freed.
  2077. * info->count should be one in this case.
  2078. * if it's not, correct it so that the port is shutdown.
  2079. */
  2080. printk("mgslpc_close: bad refcount; tty->count is 1, "
  2081. "info->count is %d\n", info->count);
  2082. info->count = 1;
  2083. }
  2084. info->count--;
  2085. /* if at least one open remaining, leave hardware active */
  2086. if (info->count)
  2087. goto cleanup;
  2088. info->flags |= ASYNC_CLOSING;
  2089. /* set tty->closing to notify line discipline to
  2090. * only process XON/XOFF characters. Only the N_TTY
  2091. * discipline appears to use this (ppp does not).
  2092. */
  2093. tty->closing = 1;
  2094. /* wait for transmit data to clear all layers */
  2095. if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
  2096. if (debug_level >= DEBUG_LEVEL_INFO)
  2097. printk("%s(%d):mgslpc_close(%s) calling tty_wait_until_sent\n",
  2098. __FILE__,__LINE__, info->device_name );
  2099. tty_wait_until_sent(tty, info->closing_wait);
  2100. }
  2101. if (info->flags & ASYNC_INITIALIZED)
  2102. mgslpc_wait_until_sent(tty, info->timeout);
  2103. if (tty->driver->flush_buffer)
  2104. tty->driver->flush_buffer(tty);
  2105. ldisc_flush_buffer(tty);
  2106. shutdown(info);
  2107. tty->closing = 0;
  2108. info->tty = NULL;
  2109. if (info->blocked_open) {
  2110. if (info->close_delay) {
  2111. msleep_interruptible(jiffies_to_msecs(info->close_delay));
  2112. }
  2113. wake_up_interruptible(&info->open_wait);
  2114. }
  2115. info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
  2116. wake_up_interruptible(&info->close_wait);
  2117. cleanup:
  2118. if (debug_level >= DEBUG_LEVEL_INFO)
  2119. printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
  2120. tty->driver->name, info->count);
  2121. }
  2122. /* Wait until the transmitter is empty.
  2123. */
  2124. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
  2125. {
  2126. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2127. unsigned long orig_jiffies, char_time;
  2128. if (!info )
  2129. return;
  2130. if (debug_level >= DEBUG_LEVEL_INFO)
  2131. printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
  2132. __FILE__,__LINE__, info->device_name );
  2133. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
  2134. return;
  2135. if (!(info->flags & ASYNC_INITIALIZED))
  2136. goto exit;
  2137. orig_jiffies = jiffies;
  2138. /* Set check interval to 1/5 of estimated time to
  2139. * send a character, and make it at least 1. The check
  2140. * interval should also be less than the timeout.
  2141. * Note: use tight timings here to satisfy the NIST-PCTS.
  2142. */
  2143. if ( info->params.data_rate ) {
  2144. char_time = info->timeout/(32 * 5);
  2145. if (!char_time)
  2146. char_time++;
  2147. } else
  2148. char_time = 1;
  2149. if (timeout)
  2150. char_time = min_t(unsigned long, char_time, timeout);
  2151. if (info->params.mode == MGSL_MODE_HDLC) {
  2152. while (info->tx_active) {
  2153. msleep_interruptible(jiffies_to_msecs(char_time));
  2154. if (signal_pending(current))
  2155. break;
  2156. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2157. break;
  2158. }
  2159. } else {
  2160. while ((info->tx_count || info->tx_active) &&
  2161. info->tx_enabled) {
  2162. msleep_interruptible(jiffies_to_msecs(char_time));
  2163. if (signal_pending(current))
  2164. break;
  2165. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2166. break;
  2167. }
  2168. }
  2169. exit:
  2170. if (debug_level >= DEBUG_LEVEL_INFO)
  2171. printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
  2172. __FILE__,__LINE__, info->device_name );
  2173. }
  2174. /* Called by tty_hangup() when a hangup is signaled.
  2175. * This is the same as closing all open files for the port.
  2176. */
  2177. static void mgslpc_hangup(struct tty_struct *tty)
  2178. {
  2179. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2180. if (debug_level >= DEBUG_LEVEL_INFO)
  2181. printk("%s(%d):mgslpc_hangup(%s)\n",
  2182. __FILE__,__LINE__, info->device_name );
  2183. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
  2184. return;
  2185. mgslpc_flush_buffer(tty);
  2186. shutdown(info);
  2187. info->count = 0;
  2188. info->flags &= ~ASYNC_NORMAL_ACTIVE;
  2189. info->tty = NULL;
  2190. wake_up_interruptible(&info->open_wait);
  2191. }
  2192. /* Block the current process until the specified port
  2193. * is ready to be opened.
  2194. */
  2195. static int block_til_ready(struct tty_struct *tty, struct file *filp,
  2196. MGSLPC_INFO *info)
  2197. {
  2198. DECLARE_WAITQUEUE(wait, current);
  2199. int retval;
  2200. int do_clocal = 0, extra_count = 0;
  2201. unsigned long flags;
  2202. if (debug_level >= DEBUG_LEVEL_INFO)
  2203. printk("%s(%d):block_til_ready on %s\n",
  2204. __FILE__,__LINE__, tty->driver->name );
  2205. if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
  2206. /* nonblock mode is set or port is not enabled */
  2207. /* just verify that callout device is not active */
  2208. info->flags |= ASYNC_NORMAL_ACTIVE;
  2209. return 0;
  2210. }
  2211. if (tty->termios->c_cflag & CLOCAL)
  2212. do_clocal = 1;
  2213. /* Wait for carrier detect and the line to become
  2214. * free (i.e., not in use by the callout). While we are in
  2215. * this loop, info->count is dropped by one, so that
  2216. * mgslpc_close() knows when to free things. We restore it upon
  2217. * exit, either normal or abnormal.
  2218. */
  2219. retval = 0;
  2220. add_wait_queue(&info->open_wait, &wait);
  2221. if (debug_level >= DEBUG_LEVEL_INFO)
  2222. printk("%s(%d):block_til_ready before block on %s count=%d\n",
  2223. __FILE__,__LINE__, tty->driver->name, info->count );
  2224. spin_lock_irqsave(&info->lock, flags);
  2225. if (!tty_hung_up_p(filp)) {
  2226. extra_count = 1;
  2227. info->count--;
  2228. }
  2229. spin_unlock_irqrestore(&info->lock, flags);
  2230. info->blocked_open++;
  2231. while (1) {
  2232. if ((tty->termios->c_cflag & CBAUD)) {
  2233. spin_lock_irqsave(&info->lock,flags);
  2234. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  2235. set_signals(info);
  2236. spin_unlock_irqrestore(&info->lock,flags);
  2237. }
  2238. set_current_state(TASK_INTERRUPTIBLE);
  2239. if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
  2240. retval = (info->flags & ASYNC_HUP_NOTIFY) ?
  2241. -EAGAIN : -ERESTARTSYS;
  2242. break;
  2243. }
  2244. spin_lock_irqsave(&info->lock,flags);
  2245. get_signals(info);
  2246. spin_unlock_irqrestore(&info->lock,flags);
  2247. if (!(info->flags & ASYNC_CLOSING) &&
  2248. (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
  2249. break;
  2250. }
  2251. if (signal_pending(current)) {
  2252. retval = -ERESTARTSYS;
  2253. break;
  2254. }
  2255. if (debug_level >= DEBUG_LEVEL_INFO)
  2256. printk("%s(%d):block_til_ready blocking on %s count=%d\n",
  2257. __FILE__,__LINE__, tty->driver->name, info->count );
  2258. schedule();
  2259. }
  2260. set_current_state(TASK_RUNNING);
  2261. remove_wait_queue(&info->open_wait, &wait);
  2262. if (extra_count)
  2263. info->count++;
  2264. info->blocked_open--;
  2265. if (debug_level >= DEBUG_LEVEL_INFO)
  2266. printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
  2267. __FILE__,__LINE__, tty->driver->name, info->count );
  2268. if (!retval)
  2269. info->flags |= ASYNC_NORMAL_ACTIVE;
  2270. return retval;
  2271. }
  2272. static int mgslpc_open(struct tty_struct *tty, struct file * filp)
  2273. {
  2274. MGSLPC_INFO *info;
  2275. int retval, line;
  2276. unsigned long flags;
  2277. /* verify range of specified line number */
  2278. line = tty->index;
  2279. if ((line < 0) || (line >= mgslpc_device_count)) {
  2280. printk("%s(%d):mgslpc_open with invalid line #%d.\n",
  2281. __FILE__,__LINE__,line);
  2282. return -ENODEV;
  2283. }
  2284. /* find the info structure for the specified line */
  2285. info = mgslpc_device_list;
  2286. while(info && info->line != line)
  2287. info = info->next_device;
  2288. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
  2289. return -ENODEV;
  2290. tty->driver_data = info;
  2291. info->tty = tty;
  2292. if (debug_level >= DEBUG_LEVEL_INFO)
  2293. printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
  2294. __FILE__,__LINE__,tty->driver->name, info->count);
  2295. /* If port is closing, signal caller to try again */
  2296. if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
  2297. if (info->flags & ASYNC_CLOSING)
  2298. interruptible_sleep_on(&info->close_wait);
  2299. retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
  2300. -EAGAIN : -ERESTARTSYS);
  2301. goto cleanup;
  2302. }
  2303. info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  2304. spin_lock_irqsave(&info->netlock, flags);
  2305. if (info->netcount) {
  2306. retval = -EBUSY;
  2307. spin_unlock_irqrestore(&info->netlock, flags);
  2308. goto cleanup;
  2309. }
  2310. info->count++;
  2311. spin_unlock_irqrestore(&info->netlock, flags);
  2312. if (info->count == 1) {
  2313. /* 1st open on this device, init hardware */
  2314. retval = startup(info);
  2315. if (retval < 0)
  2316. goto cleanup;
  2317. }
  2318. retval = block_til_ready(tty, filp, info);
  2319. if (retval) {
  2320. if (debug_level >= DEBUG_LEVEL_INFO)
  2321. printk("%s(%d):block_til_ready(%s) returned %d\n",
  2322. __FILE__,__LINE__, info->device_name, retval);
  2323. goto cleanup;
  2324. }
  2325. if (debug_level >= DEBUG_LEVEL_INFO)
  2326. printk("%s(%d):mgslpc_open(%s) success\n",
  2327. __FILE__,__LINE__, info->device_name);
  2328. retval = 0;
  2329. cleanup:
  2330. if (retval) {
  2331. if (tty->count == 1)
  2332. info->tty = NULL; /* tty layer will release tty struct */
  2333. if(info->count)
  2334. info->count--;
  2335. }
  2336. return retval;
  2337. }
  2338. /*
  2339. * /proc fs routines....
  2340. */
  2341. static inline int line_info(char *buf, MGSLPC_INFO *info)
  2342. {
  2343. char stat_buf[30];
  2344. int ret;
  2345. unsigned long flags;
  2346. ret = sprintf(buf, "%s:io:%04X irq:%d",
  2347. info->device_name, info->io_base, info->irq_level);
  2348. /* output current serial signal states */
  2349. spin_lock_irqsave(&info->lock,flags);
  2350. get_signals(info);
  2351. spin_unlock_irqrestore(&info->lock,flags);
  2352. stat_buf[0] = 0;
  2353. stat_buf[1] = 0;
  2354. if (info->serial_signals & SerialSignal_RTS)
  2355. strcat(stat_buf, "|RTS");
  2356. if (info->serial_signals & SerialSignal_CTS)
  2357. strcat(stat_buf, "|CTS");
  2358. if (info->serial_signals & SerialSignal_DTR)
  2359. strcat(stat_buf, "|DTR");
  2360. if (info->serial_signals & SerialSignal_DSR)
  2361. strcat(stat_buf, "|DSR");
  2362. if (info->serial_signals & SerialSignal_DCD)
  2363. strcat(stat_buf, "|CD");
  2364. if (info->serial_signals & SerialSignal_RI)
  2365. strcat(stat_buf, "|RI");
  2366. if (info->params.mode == MGSL_MODE_HDLC) {
  2367. ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
  2368. info->icount.txok, info->icount.rxok);
  2369. if (info->icount.txunder)
  2370. ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
  2371. if (info->icount.txabort)
  2372. ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
  2373. if (info->icount.rxshort)
  2374. ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
  2375. if (info->icount.rxlong)
  2376. ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
  2377. if (info->icount.rxover)
  2378. ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
  2379. if (info->icount.rxcrc)
  2380. ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
  2381. } else {
  2382. ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
  2383. info->icount.tx, info->icount.rx);
  2384. if (info->icount.frame)
  2385. ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
  2386. if (info->icount.parity)
  2387. ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
  2388. if (info->icount.brk)
  2389. ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
  2390. if (info->icount.overrun)
  2391. ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
  2392. }
  2393. /* Append serial signal status to end */
  2394. ret += sprintf(buf+ret, " %s\n", stat_buf+1);
  2395. ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  2396. info->tx_active,info->bh_requested,info->bh_running,
  2397. info->pending_bh);
  2398. return ret;
  2399. }
  2400. /* Called to print information about devices
  2401. */
  2402. static int mgslpc_read_proc(char *page, char **start, off_t off, int count,
  2403. int *eof, void *data)
  2404. {
  2405. int len = 0, l;
  2406. off_t begin = 0;
  2407. MGSLPC_INFO *info;
  2408. len += sprintf(page, "synclink driver:%s\n", driver_version);
  2409. info = mgslpc_device_list;
  2410. while( info ) {
  2411. l = line_info(page + len, info);
  2412. len += l;
  2413. if (len+begin > off+count)
  2414. goto done;
  2415. if (len+begin < off) {
  2416. begin += len;
  2417. len = 0;
  2418. }
  2419. info = info->next_device;
  2420. }
  2421. *eof = 1;
  2422. done:
  2423. if (off >= len+begin)
  2424. return 0;
  2425. *start = page + (off-begin);
  2426. return ((count < begin+len-off) ? count : begin+len-off);
  2427. }
  2428. int rx_alloc_buffers(MGSLPC_INFO *info)
  2429. {
  2430. /* each buffer has header and data */
  2431. info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
  2432. /* calculate total allocation size for 8 buffers */
  2433. info->rx_buf_total_size = info->rx_buf_size * 8;
  2434. /* limit total allocated memory */
  2435. if (info->rx_buf_total_size > 0x10000)
  2436. info->rx_buf_total_size = 0x10000;
  2437. /* calculate number of buffers */
  2438. info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
  2439. info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
  2440. if (info->rx_buf == NULL)
  2441. return -ENOMEM;
  2442. rx_reset_buffers(info);
  2443. return 0;
  2444. }
  2445. void rx_free_buffers(MGSLPC_INFO *info)
  2446. {
  2447. kfree(info->rx_buf);
  2448. info->rx_buf = NULL;
  2449. }
  2450. int claim_resources(MGSLPC_INFO *info)
  2451. {
  2452. if (rx_alloc_buffers(info) < 0 ) {
  2453. printk( "Cant allocate rx buffer %s\n", info->device_name);
  2454. release_resources(info);
  2455. return -ENODEV;
  2456. }
  2457. return 0;
  2458. }
  2459. void release_resources(MGSLPC_INFO *info)
  2460. {
  2461. if (debug_level >= DEBUG_LEVEL_INFO)
  2462. printk("release_resources(%s)\n", info->device_name);
  2463. rx_free_buffers(info);
  2464. }
  2465. /* Add the specified device instance data structure to the
  2466. * global linked list of devices and increment the device count.
  2467. *
  2468. * Arguments: info pointer to device instance data
  2469. */
  2470. void mgslpc_add_device(MGSLPC_INFO *info)
  2471. {
  2472. info->next_device = NULL;
  2473. info->line = mgslpc_device_count;
  2474. sprintf(info->device_name,"ttySLP%d",info->line);
  2475. if (info->line < MAX_DEVICE_COUNT) {
  2476. if (maxframe[info->line])
  2477. info->max_frame_size = maxframe[info->line];
  2478. info->dosyncppp = dosyncppp[info->line];
  2479. }
  2480. mgslpc_device_count++;
  2481. if (!mgslpc_device_list)
  2482. mgslpc_device_list = info;
  2483. else {
  2484. MGSLPC_INFO *current_dev = mgslpc_device_list;
  2485. while( current_dev->next_device )
  2486. current_dev = current_dev->next_device;
  2487. current_dev->next_device = info;
  2488. }
  2489. if (info->max_frame_size < 4096)
  2490. info->max_frame_size = 4096;
  2491. else if (info->max_frame_size > 65535)
  2492. info->max_frame_size = 65535;
  2493. printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
  2494. info->device_name, info->io_base, info->irq_level);
  2495. #ifdef CONFIG_HDLC
  2496. hdlcdev_init(info);
  2497. #endif
  2498. }
  2499. void mgslpc_remove_device(MGSLPC_INFO *remove_info)
  2500. {
  2501. MGSLPC_INFO *info = mgslpc_device_list;
  2502. MGSLPC_INFO *last = NULL;
  2503. while(info) {
  2504. if (info == remove_info) {
  2505. if (last)
  2506. last->next_device = info->next_device;
  2507. else
  2508. mgslpc_device_list = info->next_device;
  2509. #ifdef CONFIG_HDLC
  2510. hdlcdev_exit(info);
  2511. #endif
  2512. release_resources(info);
  2513. kfree(info);
  2514. mgslpc_device_count--;
  2515. return;
  2516. }
  2517. last = info;
  2518. info = info->next_device;
  2519. }
  2520. }
  2521. static struct pcmcia_device_id mgslpc_ids[] = {
  2522. PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
  2523. PCMCIA_DEVICE_NULL
  2524. };
  2525. MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
  2526. static struct pcmcia_driver mgslpc_driver = {
  2527. .owner = THIS_MODULE,
  2528. .drv = {
  2529. .name = "synclink_cs",
  2530. },
  2531. .probe = mgslpc_attach,
  2532. .remove = mgslpc_detach,
  2533. .id_table = mgslpc_ids,
  2534. .suspend = mgslpc_suspend,
  2535. .resume = mgslpc_resume,
  2536. };
  2537. static struct tty_operations mgslpc_ops = {
  2538. .open = mgslpc_open,
  2539. .close = mgslpc_close,
  2540. .write = mgslpc_write,
  2541. .put_char = mgslpc_put_char,
  2542. .flush_chars = mgslpc_flush_chars,
  2543. .write_room = mgslpc_write_room,
  2544. .chars_in_buffer = mgslpc_chars_in_buffer,
  2545. .flush_buffer = mgslpc_flush_buffer,
  2546. .ioctl = mgslpc_ioctl,
  2547. .throttle = mgslpc_throttle,
  2548. .unthrottle = mgslpc_unthrottle,
  2549. .send_xchar = mgslpc_send_xchar,
  2550. .break_ctl = mgslpc_break,
  2551. .wait_until_sent = mgslpc_wait_until_sent,
  2552. .read_proc = mgslpc_read_proc,
  2553. .set_termios = mgslpc_set_termios,
  2554. .stop = tx_pause,
  2555. .start = tx_release,
  2556. .hangup = mgslpc_hangup,
  2557. .tiocmget = tiocmget,
  2558. .tiocmset = tiocmset,
  2559. };
  2560. static void synclink_cs_cleanup(void)
  2561. {
  2562. int rc;
  2563. printk("Unloading %s: version %s\n", driver_name, driver_version);
  2564. while(mgslpc_device_list)
  2565. mgslpc_remove_device(mgslpc_device_list);
  2566. if (serial_driver) {
  2567. if ((rc = tty_unregister_driver(serial_driver)))
  2568. printk("%s(%d) failed to unregister tty driver err=%d\n",
  2569. __FILE__,__LINE__,rc);
  2570. put_tty_driver(serial_driver);
  2571. }
  2572. pcmcia_unregister_driver(&mgslpc_driver);
  2573. }
  2574. static int __init synclink_cs_init(void)
  2575. {
  2576. int rc;
  2577. if (break_on_load) {
  2578. mgslpc_get_text_ptr();
  2579. BREAKPOINT();
  2580. }
  2581. printk("%s %s\n", driver_name, driver_version);
  2582. if ((rc = pcmcia_register_driver(&mgslpc_driver)) < 0)
  2583. return rc;
  2584. serial_driver = alloc_tty_driver(MAX_DEVICE_COUNT);
  2585. if (!serial_driver) {
  2586. rc = -ENOMEM;
  2587. goto error;
  2588. }
  2589. /* Initialize the tty_driver structure */
  2590. serial_driver->owner = THIS_MODULE;
  2591. serial_driver->driver_name = "synclink_cs";
  2592. serial_driver->name = "ttySLP";
  2593. serial_driver->major = ttymajor;
  2594. serial_driver->minor_start = 64;
  2595. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  2596. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  2597. serial_driver->init_termios = tty_std_termios;
  2598. serial_driver->init_termios.c_cflag =
  2599. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  2600. serial_driver->flags = TTY_DRIVER_REAL_RAW;
  2601. tty_set_operations(serial_driver, &mgslpc_ops);
  2602. if ((rc = tty_register_driver(serial_driver)) < 0) {
  2603. printk("%s(%d):Couldn't register serial driver\n",
  2604. __FILE__,__LINE__);
  2605. put_tty_driver(serial_driver);
  2606. serial_driver = NULL;
  2607. goto error;
  2608. }
  2609. printk("%s %s, tty major#%d\n",
  2610. driver_name, driver_version,
  2611. serial_driver->major);
  2612. return 0;
  2613. error:
  2614. synclink_cs_cleanup();
  2615. return rc;
  2616. }
  2617. static void __exit synclink_cs_exit(void)
  2618. {
  2619. synclink_cs_cleanup();
  2620. }
  2621. module_init(synclink_cs_init);
  2622. module_exit(synclink_cs_exit);
  2623. static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
  2624. {
  2625. unsigned int M, N;
  2626. unsigned char val;
  2627. /* note:standard BRG mode is broken in V3.2 chip
  2628. * so enhanced mode is always used
  2629. */
  2630. if (rate) {
  2631. N = 3686400 / rate;
  2632. if (!N)
  2633. N = 1;
  2634. N >>= 1;
  2635. for (M = 1; N > 64 && M < 16; M++)
  2636. N >>= 1;
  2637. N--;
  2638. /* BGR[5..0] = N
  2639. * BGR[9..6] = M
  2640. * BGR[7..0] contained in BGR register
  2641. * BGR[9..8] contained in CCR2[7..6]
  2642. * divisor = (N+1)*2^M
  2643. *
  2644. * Note: M *must* not be zero (causes asymetric duty cycle)
  2645. */
  2646. write_reg(info, (unsigned char) (channel + BGR),
  2647. (unsigned char) ((M << 6) + N));
  2648. val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
  2649. val |= ((M << 4) & 0xc0);
  2650. write_reg(info, (unsigned char) (channel + CCR2), val);
  2651. }
  2652. }
  2653. /* Enabled the AUX clock output at the specified frequency.
  2654. */
  2655. static void enable_auxclk(MGSLPC_INFO *info)
  2656. {
  2657. unsigned char val;
  2658. /* MODE
  2659. *
  2660. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2661. * 05 ADM Address Mode, 0 = no addr recognition
  2662. * 04 TMD Timer Mode, 0 = external
  2663. * 03 RAC Receiver Active, 0 = inactive
  2664. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2665. * 01 TRS Timer Resolution, 1=512
  2666. * 00 TLP Test Loop, 0 = no loop
  2667. *
  2668. * 1000 0010
  2669. */
  2670. val = 0x82;
  2671. /* channel B RTS is used to enable AUXCLK driver on SP505 */
  2672. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2673. val |= BIT2;
  2674. write_reg(info, CHB + MODE, val);
  2675. /* CCR0
  2676. *
  2677. * 07 PU Power Up, 1=active, 0=power down
  2678. * 06 MCE Master Clock Enable, 1=enabled
  2679. * 05 Reserved, 0
  2680. * 04..02 SC[2..0] Encoding
  2681. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2682. *
  2683. * 11000000
  2684. */
  2685. write_reg(info, CHB + CCR0, 0xc0);
  2686. /* CCR1
  2687. *
  2688. * 07 SFLG Shared Flag, 0 = disable shared flags
  2689. * 06 GALP Go Active On Loop, 0 = not used
  2690. * 05 GLP Go On Loop, 0 = not used
  2691. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2692. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2693. * 02..00 CM[2..0] Clock Mode
  2694. *
  2695. * 0001 0111
  2696. */
  2697. write_reg(info, CHB + CCR1, 0x17);
  2698. /* CCR2 (Channel B)
  2699. *
  2700. * 07..06 BGR[9..8] Baud rate bits 9..8
  2701. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2702. * 04 SSEL Clock source select, 1=submode b
  2703. * 03 TOE 0=TxCLK is input, 1=TxCLK is output
  2704. * 02 RWX Read/Write Exchange 0=disabled
  2705. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2706. * 00 DIV, data inversion 0=disabled, 1=enabled
  2707. *
  2708. * 0011 1000
  2709. */
  2710. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2711. write_reg(info, CHB + CCR2, 0x38);
  2712. else
  2713. write_reg(info, CHB + CCR2, 0x30);
  2714. /* CCR4
  2715. *
  2716. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2717. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2718. * 05 TST1 Test Pin, 0=normal operation
  2719. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2720. * 03..02 Reserved, must be 0
  2721. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2722. *
  2723. * 0101 0000
  2724. */
  2725. write_reg(info, CHB + CCR4, 0x50);
  2726. /* if auxclk not enabled, set internal BRG so
  2727. * CTS transitions can be detected (requires TxC)
  2728. */
  2729. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2730. mgslpc_set_rate(info, CHB, info->params.clock_speed);
  2731. else
  2732. mgslpc_set_rate(info, CHB, 921600);
  2733. }
  2734. static void loopback_enable(MGSLPC_INFO *info)
  2735. {
  2736. unsigned char val;
  2737. /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
  2738. val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
  2739. write_reg(info, CHA + CCR1, val);
  2740. /* CCR2:04 SSEL Clock source select, 1=submode b */
  2741. val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
  2742. write_reg(info, CHA + CCR2, val);
  2743. /* set LinkSpeed if available, otherwise default to 2Mbps */
  2744. if (info->params.clock_speed)
  2745. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2746. else
  2747. mgslpc_set_rate(info, CHA, 1843200);
  2748. /* MODE:00 TLP Test Loop, 1=loopback enabled */
  2749. val = read_reg(info, CHA + MODE) | BIT0;
  2750. write_reg(info, CHA + MODE, val);
  2751. }
  2752. void hdlc_mode(MGSLPC_INFO *info)
  2753. {
  2754. unsigned char val;
  2755. unsigned char clkmode, clksubmode;
  2756. /* disable all interrupts */
  2757. irq_disable(info, CHA, 0xffff);
  2758. irq_disable(info, CHB, 0xffff);
  2759. port_irq_disable(info, 0xff);
  2760. /* assume clock mode 0a, rcv=RxC xmt=TxC */
  2761. clkmode = clksubmode = 0;
  2762. if (info->params.flags & HDLC_FLAG_RXC_DPLL
  2763. && info->params.flags & HDLC_FLAG_TXC_DPLL) {
  2764. /* clock mode 7a, rcv = DPLL, xmt = DPLL */
  2765. clkmode = 7;
  2766. } else if (info->params.flags & HDLC_FLAG_RXC_BRG
  2767. && info->params.flags & HDLC_FLAG_TXC_BRG) {
  2768. /* clock mode 7b, rcv = BRG, xmt = BRG */
  2769. clkmode = 7;
  2770. clksubmode = 1;
  2771. } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
  2772. if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2773. /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
  2774. clkmode = 6;
  2775. clksubmode = 1;
  2776. } else {
  2777. /* clock mode 6a, rcv = DPLL, xmt = TxC */
  2778. clkmode = 6;
  2779. }
  2780. } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2781. /* clock mode 0b, rcv = RxC, xmt = BRG */
  2782. clksubmode = 1;
  2783. }
  2784. /* MODE
  2785. *
  2786. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2787. * 05 ADM Address Mode, 0 = no addr recognition
  2788. * 04 TMD Timer Mode, 0 = external
  2789. * 03 RAC Receiver Active, 0 = inactive
  2790. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2791. * 01 TRS Timer Resolution, 1=512
  2792. * 00 TLP Test Loop, 0 = no loop
  2793. *
  2794. * 1000 0010
  2795. */
  2796. val = 0x82;
  2797. if (info->params.loopback)
  2798. val |= BIT0;
  2799. /* preserve RTS state */
  2800. if (info->serial_signals & SerialSignal_RTS)
  2801. val |= BIT2;
  2802. write_reg(info, CHA + MODE, val);
  2803. /* CCR0
  2804. *
  2805. * 07 PU Power Up, 1=active, 0=power down
  2806. * 06 MCE Master Clock Enable, 1=enabled
  2807. * 05 Reserved, 0
  2808. * 04..02 SC[2..0] Encoding
  2809. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2810. *
  2811. * 11000000
  2812. */
  2813. val = 0xc0;
  2814. switch (info->params.encoding)
  2815. {
  2816. case HDLC_ENCODING_NRZI:
  2817. val |= BIT3;
  2818. break;
  2819. case HDLC_ENCODING_BIPHASE_SPACE:
  2820. val |= BIT4;
  2821. break; // FM0
  2822. case HDLC_ENCODING_BIPHASE_MARK:
  2823. val |= BIT4 + BIT2;
  2824. break; // FM1
  2825. case HDLC_ENCODING_BIPHASE_LEVEL:
  2826. val |= BIT4 + BIT3;
  2827. break; // Manchester
  2828. }
  2829. write_reg(info, CHA + CCR0, val);
  2830. /* CCR1
  2831. *
  2832. * 07 SFLG Shared Flag, 0 = disable shared flags
  2833. * 06 GALP Go Active On Loop, 0 = not used
  2834. * 05 GLP Go On Loop, 0 = not used
  2835. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2836. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2837. * 02..00 CM[2..0] Clock Mode
  2838. *
  2839. * 0001 0000
  2840. */
  2841. val = 0x10 + clkmode;
  2842. write_reg(info, CHA + CCR1, val);
  2843. /* CCR2
  2844. *
  2845. * 07..06 BGR[9..8] Baud rate bits 9..8
  2846. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2847. * 04 SSEL Clock source select, 1=submode b
  2848. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2849. * 02 RWX Read/Write Exchange 0=disabled
  2850. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2851. * 00 DIV, data inversion 0=disabled, 1=enabled
  2852. *
  2853. * 0000 0000
  2854. */
  2855. val = 0x00;
  2856. if (clkmode == 2 || clkmode == 3 || clkmode == 6
  2857. || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
  2858. val |= BIT5;
  2859. if (clksubmode)
  2860. val |= BIT4;
  2861. if (info->params.crc_type == HDLC_CRC_32_CCITT)
  2862. val |= BIT1;
  2863. if (info->params.encoding == HDLC_ENCODING_NRZB)
  2864. val |= BIT0;
  2865. write_reg(info, CHA + CCR2, val);
  2866. /* CCR3
  2867. *
  2868. * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
  2869. * 05 EPT Enable preamble transmission, 1=enabled
  2870. * 04 RADD Receive address pushed to FIFO, 0=disabled
  2871. * 03 CRL CRC Reset Level, 0=FFFF
  2872. * 02 RCRC Rx CRC 0=On 1=Off
  2873. * 01 TCRC Tx CRC 0=On 1=Off
  2874. * 00 PSD DPLL Phase Shift Disable
  2875. *
  2876. * 0000 0000
  2877. */
  2878. val = 0x00;
  2879. if (info->params.crc_type == HDLC_CRC_NONE)
  2880. val |= BIT2 + BIT1;
  2881. if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
  2882. val |= BIT5;
  2883. switch (info->params.preamble_length)
  2884. {
  2885. case HDLC_PREAMBLE_LENGTH_16BITS:
  2886. val |= BIT6;
  2887. break;
  2888. case HDLC_PREAMBLE_LENGTH_32BITS:
  2889. val |= BIT6;
  2890. break;
  2891. case HDLC_PREAMBLE_LENGTH_64BITS:
  2892. val |= BIT7 + BIT6;
  2893. break;
  2894. }
  2895. write_reg(info, CHA + CCR3, val);
  2896. /* PRE - Preamble pattern */
  2897. val = 0;
  2898. switch (info->params.preamble)
  2899. {
  2900. case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
  2901. case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
  2902. case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
  2903. case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
  2904. }
  2905. write_reg(info, CHA + PRE, val);
  2906. /* CCR4
  2907. *
  2908. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2909. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2910. * 05 TST1 Test Pin, 0=normal operation
  2911. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2912. * 03..02 Reserved, must be 0
  2913. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2914. *
  2915. * 0101 0000
  2916. */
  2917. val = 0x50;
  2918. write_reg(info, CHA + CCR4, val);
  2919. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  2920. mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
  2921. else
  2922. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2923. /* RLCR Receive length check register
  2924. *
  2925. * 7 1=enable receive length check
  2926. * 6..0 Max frame length = (RL + 1) * 32
  2927. */
  2928. write_reg(info, CHA + RLCR, 0);
  2929. /* XBCH Transmit Byte Count High
  2930. *
  2931. * 07 DMA mode, 0 = interrupt driven
  2932. * 06 NRM, 0=ABM (ignored)
  2933. * 05 CAS Carrier Auto Start
  2934. * 04 XC Transmit Continuously (ignored)
  2935. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  2936. *
  2937. * 0000 0000
  2938. */
  2939. val = 0x00;
  2940. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  2941. val |= BIT5;
  2942. write_reg(info, CHA + XBCH, val);
  2943. enable_auxclk(info);
  2944. if (info->params.loopback || info->testing_irq)
  2945. loopback_enable(info);
  2946. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  2947. {
  2948. irq_enable(info, CHB, IRQ_CTS);
  2949. /* PVR[3] 1=AUTO CTS active */
  2950. set_reg_bits(info, CHA + PVR, BIT3);
  2951. } else
  2952. clear_reg_bits(info, CHA + PVR, BIT3);
  2953. irq_enable(info, CHA,
  2954. IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
  2955. IRQ_UNDERRUN + IRQ_TXFIFO);
  2956. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  2957. wait_command_complete(info, CHA);
  2958. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  2959. /* Master clock mode enabled above to allow reset commands
  2960. * to complete even if no data clocks are present.
  2961. *
  2962. * Disable master clock mode for normal communications because
  2963. * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
  2964. * IRQ when in master clock mode.
  2965. *
  2966. * Leave master clock mode enabled for IRQ test because the
  2967. * timer IRQ used by the test can only happen in master clock mode.
  2968. */
  2969. if (!info->testing_irq)
  2970. clear_reg_bits(info, CHA + CCR0, BIT6);
  2971. tx_set_idle(info);
  2972. tx_stop(info);
  2973. rx_stop(info);
  2974. }
  2975. void rx_stop(MGSLPC_INFO *info)
  2976. {
  2977. if (debug_level >= DEBUG_LEVEL_ISR)
  2978. printk("%s(%d):rx_stop(%s)\n",
  2979. __FILE__,__LINE__, info->device_name );
  2980. /* MODE:03 RAC Receiver Active, 0=inactive */
  2981. clear_reg_bits(info, CHA + MODE, BIT3);
  2982. info->rx_enabled = 0;
  2983. info->rx_overflow = 0;
  2984. }
  2985. void rx_start(MGSLPC_INFO *info)
  2986. {
  2987. if (debug_level >= DEBUG_LEVEL_ISR)
  2988. printk("%s(%d):rx_start(%s)\n",
  2989. __FILE__,__LINE__, info->device_name );
  2990. rx_reset_buffers(info);
  2991. info->rx_enabled = 0;
  2992. info->rx_overflow = 0;
  2993. /* MODE:03 RAC Receiver Active, 1=active */
  2994. set_reg_bits(info, CHA + MODE, BIT3);
  2995. info->rx_enabled = 1;
  2996. }
  2997. void tx_start(MGSLPC_INFO *info)
  2998. {
  2999. if (debug_level >= DEBUG_LEVEL_ISR)
  3000. printk("%s(%d):tx_start(%s)\n",
  3001. __FILE__,__LINE__, info->device_name );
  3002. if (info->tx_count) {
  3003. /* If auto RTS enabled and RTS is inactive, then assert */
  3004. /* RTS and set a flag indicating that the driver should */
  3005. /* negate RTS when the transmission completes. */
  3006. info->drop_rts_on_tx_done = 0;
  3007. if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
  3008. get_signals(info);
  3009. if (!(info->serial_signals & SerialSignal_RTS)) {
  3010. info->serial_signals |= SerialSignal_RTS;
  3011. set_signals(info);
  3012. info->drop_rts_on_tx_done = 1;
  3013. }
  3014. }
  3015. if (info->params.mode == MGSL_MODE_ASYNC) {
  3016. if (!info->tx_active) {
  3017. info->tx_active = 1;
  3018. tx_ready(info);
  3019. }
  3020. } else {
  3021. info->tx_active = 1;
  3022. tx_ready(info);
  3023. info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
  3024. add_timer(&info->tx_timer);
  3025. }
  3026. }
  3027. if (!info->tx_enabled)
  3028. info->tx_enabled = 1;
  3029. }
  3030. void tx_stop(MGSLPC_INFO *info)
  3031. {
  3032. if (debug_level >= DEBUG_LEVEL_ISR)
  3033. printk("%s(%d):tx_stop(%s)\n",
  3034. __FILE__,__LINE__, info->device_name );
  3035. del_timer(&info->tx_timer);
  3036. info->tx_enabled = 0;
  3037. info->tx_active = 0;
  3038. }
  3039. /* Reset the adapter to a known state and prepare it for further use.
  3040. */
  3041. void reset_device(MGSLPC_INFO *info)
  3042. {
  3043. /* power up both channels (set BIT7) */
  3044. write_reg(info, CHA + CCR0, 0x80);
  3045. write_reg(info, CHB + CCR0, 0x80);
  3046. write_reg(info, CHA + MODE, 0);
  3047. write_reg(info, CHB + MODE, 0);
  3048. /* disable all interrupts */
  3049. irq_disable(info, CHA, 0xffff);
  3050. irq_disable(info, CHB, 0xffff);
  3051. port_irq_disable(info, 0xff);
  3052. /* PCR Port Configuration Register
  3053. *
  3054. * 07..04 DEC[3..0] Serial I/F select outputs
  3055. * 03 output, 1=AUTO CTS control enabled
  3056. * 02 RI Ring Indicator input 0=active
  3057. * 01 DSR input 0=active
  3058. * 00 DTR output 0=active
  3059. *
  3060. * 0000 0110
  3061. */
  3062. write_reg(info, PCR, 0x06);
  3063. /* PVR Port Value Register
  3064. *
  3065. * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
  3066. * 03 AUTO CTS output 1=enabled
  3067. * 02 RI Ring Indicator input
  3068. * 01 DSR input
  3069. * 00 DTR output (1=inactive)
  3070. *
  3071. * 0000 0001
  3072. */
  3073. // write_reg(info, PVR, PVR_DTR);
  3074. /* IPC Interrupt Port Configuration
  3075. *
  3076. * 07 VIS 1=Masked interrupts visible
  3077. * 06..05 Reserved, 0
  3078. * 04..03 SLA Slave address, 00 ignored
  3079. * 02 CASM Cascading Mode, 1=daisy chain
  3080. * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
  3081. *
  3082. * 0000 0101
  3083. */
  3084. write_reg(info, IPC, 0x05);
  3085. }
  3086. void async_mode(MGSLPC_INFO *info)
  3087. {
  3088. unsigned char val;
  3089. /* disable all interrupts */
  3090. irq_disable(info, CHA, 0xffff);
  3091. irq_disable(info, CHB, 0xffff);
  3092. port_irq_disable(info, 0xff);
  3093. /* MODE
  3094. *
  3095. * 07 Reserved, 0
  3096. * 06 FRTS RTS State, 0=active
  3097. * 05 FCTS Flow Control on CTS
  3098. * 04 FLON Flow Control Enable
  3099. * 03 RAC Receiver Active, 0 = inactive
  3100. * 02 RTS 0=Auto RTS, 1=manual RTS
  3101. * 01 TRS Timer Resolution, 1=512
  3102. * 00 TLP Test Loop, 0 = no loop
  3103. *
  3104. * 0000 0110
  3105. */
  3106. val = 0x06;
  3107. if (info->params.loopback)
  3108. val |= BIT0;
  3109. /* preserve RTS state */
  3110. if (!(info->serial_signals & SerialSignal_RTS))
  3111. val |= BIT6;
  3112. write_reg(info, CHA + MODE, val);
  3113. /* CCR0
  3114. *
  3115. * 07 PU Power Up, 1=active, 0=power down
  3116. * 06 MCE Master Clock Enable, 1=enabled
  3117. * 05 Reserved, 0
  3118. * 04..02 SC[2..0] Encoding, 000=NRZ
  3119. * 01..00 SM[1..0] Serial Mode, 11=Async
  3120. *
  3121. * 1000 0011
  3122. */
  3123. write_reg(info, CHA + CCR0, 0x83);
  3124. /* CCR1
  3125. *
  3126. * 07..05 Reserved, 0
  3127. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  3128. * 03 BCR Bit Clock Rate, 1=16x
  3129. * 02..00 CM[2..0] Clock Mode, 111=BRG
  3130. *
  3131. * 0001 1111
  3132. */
  3133. write_reg(info, CHA + CCR1, 0x1f);
  3134. /* CCR2 (channel A)
  3135. *
  3136. * 07..06 BGR[9..8] Baud rate bits 9..8
  3137. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  3138. * 04 SSEL Clock source select, 1=submode b
  3139. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  3140. * 02 RWX Read/Write Exchange 0=disabled
  3141. * 01 Reserved, 0
  3142. * 00 DIV, data inversion 0=disabled, 1=enabled
  3143. *
  3144. * 0001 0000
  3145. */
  3146. write_reg(info, CHA + CCR2, 0x10);
  3147. /* CCR3
  3148. *
  3149. * 07..01 Reserved, 0
  3150. * 00 PSD DPLL Phase Shift Disable
  3151. *
  3152. * 0000 0000
  3153. */
  3154. write_reg(info, CHA + CCR3, 0);
  3155. /* CCR4
  3156. *
  3157. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  3158. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  3159. * 05 TST1 Test Pin, 0=normal operation
  3160. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  3161. * 03..00 Reserved, must be 0
  3162. *
  3163. * 0101 0000
  3164. */
  3165. write_reg(info, CHA + CCR4, 0x50);
  3166. mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
  3167. /* DAFO Data Format
  3168. *
  3169. * 07 Reserved, 0
  3170. * 06 XBRK transmit break, 0=normal operation
  3171. * 05 Stop bits (0=1, 1=2)
  3172. * 04..03 PAR[1..0] Parity (01=odd, 10=even)
  3173. * 02 PAREN Parity Enable
  3174. * 01..00 CHL[1..0] Character Length (00=8, 01=7)
  3175. *
  3176. */
  3177. val = 0x00;
  3178. if (info->params.data_bits != 8)
  3179. val |= BIT0; /* 7 bits */
  3180. if (info->params.stop_bits != 1)
  3181. val |= BIT5;
  3182. if (info->params.parity != ASYNC_PARITY_NONE)
  3183. {
  3184. val |= BIT2; /* Parity enable */
  3185. if (info->params.parity == ASYNC_PARITY_ODD)
  3186. val |= BIT3;
  3187. else
  3188. val |= BIT4;
  3189. }
  3190. write_reg(info, CHA + DAFO, val);
  3191. /* RFC Rx FIFO Control
  3192. *
  3193. * 07 Reserved, 0
  3194. * 06 DPS, 1=parity bit not stored in data byte
  3195. * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
  3196. * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
  3197. * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
  3198. * 01 Reserved, 0
  3199. * 00 TCDE Terminate Char Detect Enable, 0=disabled
  3200. *
  3201. * 0101 1100
  3202. */
  3203. write_reg(info, CHA + RFC, 0x5c);
  3204. /* RLCR Receive length check register
  3205. *
  3206. * Max frame length = (RL + 1) * 32
  3207. */
  3208. write_reg(info, CHA + RLCR, 0);
  3209. /* XBCH Transmit Byte Count High
  3210. *
  3211. * 07 DMA mode, 0 = interrupt driven
  3212. * 06 NRM, 0=ABM (ignored)
  3213. * 05 CAS Carrier Auto Start
  3214. * 04 XC Transmit Continuously (ignored)
  3215. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  3216. *
  3217. * 0000 0000
  3218. */
  3219. val = 0x00;
  3220. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3221. val |= BIT5;
  3222. write_reg(info, CHA + XBCH, val);
  3223. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3224. irq_enable(info, CHA, IRQ_CTS);
  3225. /* MODE:03 RAC Receiver Active, 1=active */
  3226. set_reg_bits(info, CHA + MODE, BIT3);
  3227. enable_auxclk(info);
  3228. if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
  3229. irq_enable(info, CHB, IRQ_CTS);
  3230. /* PVR[3] 1=AUTO CTS active */
  3231. set_reg_bits(info, CHA + PVR, BIT3);
  3232. } else
  3233. clear_reg_bits(info, CHA + PVR, BIT3);
  3234. irq_enable(info, CHA,
  3235. IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
  3236. IRQ_ALLSENT + IRQ_TXFIFO);
  3237. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  3238. wait_command_complete(info, CHA);
  3239. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  3240. }
  3241. /* Set the HDLC idle mode for the transmitter.
  3242. */
  3243. void tx_set_idle(MGSLPC_INFO *info)
  3244. {
  3245. /* Note: ESCC2 only supports flags and one idle modes */
  3246. if (info->idle_mode == HDLC_TXIDLE_FLAGS)
  3247. set_reg_bits(info, CHA + CCR1, BIT3);
  3248. else
  3249. clear_reg_bits(info, CHA + CCR1, BIT3);
  3250. }
  3251. /* get state of the V24 status (input) signals.
  3252. */
  3253. void get_signals(MGSLPC_INFO *info)
  3254. {
  3255. unsigned char status = 0;
  3256. /* preserve DTR and RTS */
  3257. info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
  3258. if (read_reg(info, CHB + VSTR) & BIT7)
  3259. info->serial_signals |= SerialSignal_DCD;
  3260. if (read_reg(info, CHB + STAR) & BIT1)
  3261. info->serial_signals |= SerialSignal_CTS;
  3262. status = read_reg(info, CHA + PVR);
  3263. if (!(status & PVR_RI))
  3264. info->serial_signals |= SerialSignal_RI;
  3265. if (!(status & PVR_DSR))
  3266. info->serial_signals |= SerialSignal_DSR;
  3267. }
  3268. /* Set the state of DTR and RTS based on contents of
  3269. * serial_signals member of device extension.
  3270. */
  3271. void set_signals(MGSLPC_INFO *info)
  3272. {
  3273. unsigned char val;
  3274. val = read_reg(info, CHA + MODE);
  3275. if (info->params.mode == MGSL_MODE_ASYNC) {
  3276. if (info->serial_signals & SerialSignal_RTS)
  3277. val &= ~BIT6;
  3278. else
  3279. val |= BIT6;
  3280. } else {
  3281. if (info->serial_signals & SerialSignal_RTS)
  3282. val |= BIT2;
  3283. else
  3284. val &= ~BIT2;
  3285. }
  3286. write_reg(info, CHA + MODE, val);
  3287. if (info->serial_signals & SerialSignal_DTR)
  3288. clear_reg_bits(info, CHA + PVR, PVR_DTR);
  3289. else
  3290. set_reg_bits(info, CHA + PVR, PVR_DTR);
  3291. }
  3292. void rx_reset_buffers(MGSLPC_INFO *info)
  3293. {
  3294. RXBUF *buf;
  3295. int i;
  3296. info->rx_put = 0;
  3297. info->rx_get = 0;
  3298. info->rx_frame_count = 0;
  3299. for (i=0 ; i < info->rx_buf_count ; i++) {
  3300. buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
  3301. buf->status = buf->count = 0;
  3302. }
  3303. }
  3304. /* Attempt to return a received HDLC frame
  3305. * Only frames received without errors are returned.
  3306. *
  3307. * Returns 1 if frame returned, otherwise 0
  3308. */
  3309. int rx_get_frame(MGSLPC_INFO *info)
  3310. {
  3311. unsigned short status;
  3312. RXBUF *buf;
  3313. unsigned int framesize = 0;
  3314. unsigned long flags;
  3315. struct tty_struct *tty = info->tty;
  3316. int return_frame = 0;
  3317. if (info->rx_frame_count == 0)
  3318. return 0;
  3319. buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
  3320. status = buf->status;
  3321. /* 07 VFR 1=valid frame
  3322. * 06 RDO 1=data overrun
  3323. * 05 CRC 1=OK, 0=error
  3324. * 04 RAB 1=frame aborted
  3325. */
  3326. if ((status & 0xf0) != 0xA0) {
  3327. if (!(status & BIT7) || (status & BIT4))
  3328. info->icount.rxabort++;
  3329. else if (status & BIT6)
  3330. info->icount.rxover++;
  3331. else if (!(status & BIT5)) {
  3332. info->icount.rxcrc++;
  3333. if (info->params.crc_type & HDLC_CRC_RETURN_EX)
  3334. return_frame = 1;
  3335. }
  3336. framesize = 0;
  3337. #ifdef CONFIG_HDLC
  3338. {
  3339. struct net_device_stats *stats = hdlc_stats(info->netdev);
  3340. stats->rx_errors++;
  3341. stats->rx_frame_errors++;
  3342. }
  3343. #endif
  3344. } else
  3345. return_frame = 1;
  3346. if (return_frame)
  3347. framesize = buf->count;
  3348. if (debug_level >= DEBUG_LEVEL_BH)
  3349. printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
  3350. __FILE__,__LINE__,info->device_name,status,framesize);
  3351. if (debug_level >= DEBUG_LEVEL_DATA)
  3352. trace_block(info, buf->data, framesize, 0);
  3353. if (framesize) {
  3354. if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
  3355. framesize+1 > info->max_frame_size) ||
  3356. framesize > info->max_frame_size)
  3357. info->icount.rxlong++;
  3358. else {
  3359. if (status & BIT5)
  3360. info->icount.rxok++;
  3361. if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
  3362. *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
  3363. ++framesize;
  3364. }
  3365. #ifdef CONFIG_HDLC
  3366. if (info->netcount)
  3367. hdlcdev_rx(info, buf->data, framesize);
  3368. else
  3369. #endif
  3370. ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
  3371. }
  3372. }
  3373. spin_lock_irqsave(&info->lock,flags);
  3374. buf->status = buf->count = 0;
  3375. info->rx_frame_count--;
  3376. info->rx_get++;
  3377. if (info->rx_get >= info->rx_buf_count)
  3378. info->rx_get = 0;
  3379. spin_unlock_irqrestore(&info->lock,flags);
  3380. return 1;
  3381. }
  3382. BOOLEAN register_test(MGSLPC_INFO *info)
  3383. {
  3384. static unsigned char patterns[] =
  3385. { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
  3386. static unsigned int count = sizeof(patterns) / sizeof(patterns[0]);
  3387. unsigned int i;
  3388. BOOLEAN rc = TRUE;
  3389. unsigned long flags;
  3390. spin_lock_irqsave(&info->lock,flags);
  3391. reset_device(info);
  3392. for (i = 0; i < count; i++) {
  3393. write_reg(info, XAD1, patterns[i]);
  3394. write_reg(info, XAD2, patterns[(i + 1) % count]);
  3395. if ((read_reg(info, XAD1) != patterns[i]) ||
  3396. (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
  3397. rc = FALSE;
  3398. break;
  3399. }
  3400. }
  3401. spin_unlock_irqrestore(&info->lock,flags);
  3402. return rc;
  3403. }
  3404. BOOLEAN irq_test(MGSLPC_INFO *info)
  3405. {
  3406. unsigned long end_time;
  3407. unsigned long flags;
  3408. spin_lock_irqsave(&info->lock,flags);
  3409. reset_device(info);
  3410. info->testing_irq = TRUE;
  3411. hdlc_mode(info);
  3412. info->irq_occurred = FALSE;
  3413. /* init hdlc mode */
  3414. irq_enable(info, CHA, IRQ_TIMER);
  3415. write_reg(info, CHA + TIMR, 0); /* 512 cycles */
  3416. issue_command(info, CHA, CMD_START_TIMER);
  3417. spin_unlock_irqrestore(&info->lock,flags);
  3418. end_time=100;
  3419. while(end_time-- && !info->irq_occurred) {
  3420. msleep_interruptible(10);
  3421. }
  3422. info->testing_irq = FALSE;
  3423. spin_lock_irqsave(&info->lock,flags);
  3424. reset_device(info);
  3425. spin_unlock_irqrestore(&info->lock,flags);
  3426. return info->irq_occurred ? TRUE : FALSE;
  3427. }
  3428. int adapter_test(MGSLPC_INFO *info)
  3429. {
  3430. if (!register_test(info)) {
  3431. info->init_error = DiagStatus_AddressFailure;
  3432. printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
  3433. __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
  3434. return -ENODEV;
  3435. }
  3436. if (!irq_test(info)) {
  3437. info->init_error = DiagStatus_IrqFailure;
  3438. printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  3439. __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
  3440. return -ENODEV;
  3441. }
  3442. if (debug_level >= DEBUG_LEVEL_INFO)
  3443. printk("%s(%d):device %s passed diagnostics\n",
  3444. __FILE__,__LINE__,info->device_name);
  3445. return 0;
  3446. }
  3447. void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
  3448. {
  3449. int i;
  3450. int linecount;
  3451. if (xmit)
  3452. printk("%s tx data:\n",info->device_name);
  3453. else
  3454. printk("%s rx data:\n",info->device_name);
  3455. while(count) {
  3456. if (count > 16)
  3457. linecount = 16;
  3458. else
  3459. linecount = count;
  3460. for(i=0;i<linecount;i++)
  3461. printk("%02X ",(unsigned char)data[i]);
  3462. for(;i<17;i++)
  3463. printk(" ");
  3464. for(i=0;i<linecount;i++) {
  3465. if (data[i]>=040 && data[i]<=0176)
  3466. printk("%c",data[i]);
  3467. else
  3468. printk(".");
  3469. }
  3470. printk("\n");
  3471. data += linecount;
  3472. count -= linecount;
  3473. }
  3474. }
  3475. /* HDLC frame time out
  3476. * update stats and do tx completion processing
  3477. */
  3478. void tx_timeout(unsigned long context)
  3479. {
  3480. MGSLPC_INFO *info = (MGSLPC_INFO*)context;
  3481. unsigned long flags;
  3482. if ( debug_level >= DEBUG_LEVEL_INFO )
  3483. printk( "%s(%d):tx_timeout(%s)\n",
  3484. __FILE__,__LINE__,info->device_name);
  3485. if(info->tx_active &&
  3486. info->params.mode == MGSL_MODE_HDLC) {
  3487. info->icount.txtimeout++;
  3488. }
  3489. spin_lock_irqsave(&info->lock,flags);
  3490. info->tx_active = 0;
  3491. info->tx_count = info->tx_put = info->tx_get = 0;
  3492. spin_unlock_irqrestore(&info->lock,flags);
  3493. #ifdef CONFIG_HDLC
  3494. if (info->netcount)
  3495. hdlcdev_tx_done(info);
  3496. else
  3497. #endif
  3498. bh_transmit(info);
  3499. }
  3500. #ifdef CONFIG_HDLC
  3501. /**
  3502. * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  3503. * set encoding and frame check sequence (FCS) options
  3504. *
  3505. * dev pointer to network device structure
  3506. * encoding serial encoding setting
  3507. * parity FCS setting
  3508. *
  3509. * returns 0 if success, otherwise error code
  3510. */
  3511. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  3512. unsigned short parity)
  3513. {
  3514. MGSLPC_INFO *info = dev_to_port(dev);
  3515. unsigned char new_encoding;
  3516. unsigned short new_crctype;
  3517. /* return error if TTY interface open */
  3518. if (info->count)
  3519. return -EBUSY;
  3520. switch (encoding)
  3521. {
  3522. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  3523. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  3524. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  3525. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  3526. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  3527. default: return -EINVAL;
  3528. }
  3529. switch (parity)
  3530. {
  3531. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  3532. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  3533. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  3534. default: return -EINVAL;
  3535. }
  3536. info->params.encoding = new_encoding;
  3537. info->params.crc_type = new_crctype;;
  3538. /* if network interface up, reprogram hardware */
  3539. if (info->netcount)
  3540. mgslpc_program_hw(info);
  3541. return 0;
  3542. }
  3543. /**
  3544. * called by generic HDLC layer to send frame
  3545. *
  3546. * skb socket buffer containing HDLC frame
  3547. * dev pointer to network device structure
  3548. *
  3549. * returns 0 if success, otherwise error code
  3550. */
  3551. static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
  3552. {
  3553. MGSLPC_INFO *info = dev_to_port(dev);
  3554. struct net_device_stats *stats = hdlc_stats(dev);
  3555. unsigned long flags;
  3556. if (debug_level >= DEBUG_LEVEL_INFO)
  3557. printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
  3558. /* stop sending until this frame completes */
  3559. netif_stop_queue(dev);
  3560. /* copy data to device buffers */
  3561. memcpy(info->tx_buf, skb->data, skb->len);
  3562. info->tx_get = 0;
  3563. info->tx_put = info->tx_count = skb->len;
  3564. /* update network statistics */
  3565. stats->tx_packets++;
  3566. stats->tx_bytes += skb->len;
  3567. /* done with socket buffer, so free it */
  3568. dev_kfree_skb(skb);
  3569. /* save start time for transmit timeout detection */
  3570. dev->trans_start = jiffies;
  3571. /* start hardware transmitter if necessary */
  3572. spin_lock_irqsave(&info->lock,flags);
  3573. if (!info->tx_active)
  3574. tx_start(info);
  3575. spin_unlock_irqrestore(&info->lock,flags);
  3576. return 0;
  3577. }
  3578. /**
  3579. * called by network layer when interface enabled
  3580. * claim resources and initialize hardware
  3581. *
  3582. * dev pointer to network device structure
  3583. *
  3584. * returns 0 if success, otherwise error code
  3585. */
  3586. static int hdlcdev_open(struct net_device *dev)
  3587. {
  3588. MGSLPC_INFO *info = dev_to_port(dev);
  3589. int rc;
  3590. unsigned long flags;
  3591. if (debug_level >= DEBUG_LEVEL_INFO)
  3592. printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
  3593. /* generic HDLC layer open processing */
  3594. if ((rc = hdlc_open(dev)))
  3595. return rc;
  3596. /* arbitrate between network and tty opens */
  3597. spin_lock_irqsave(&info->netlock, flags);
  3598. if (info->count != 0 || info->netcount != 0) {
  3599. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  3600. spin_unlock_irqrestore(&info->netlock, flags);
  3601. return -EBUSY;
  3602. }
  3603. info->netcount=1;
  3604. spin_unlock_irqrestore(&info->netlock, flags);
  3605. /* claim resources and init adapter */
  3606. if ((rc = startup(info)) != 0) {
  3607. spin_lock_irqsave(&info->netlock, flags);
  3608. info->netcount=0;
  3609. spin_unlock_irqrestore(&info->netlock, flags);
  3610. return rc;
  3611. }
  3612. /* assert DTR and RTS, apply hardware settings */
  3613. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  3614. mgslpc_program_hw(info);
  3615. /* enable network layer transmit */
  3616. dev->trans_start = jiffies;
  3617. netif_start_queue(dev);
  3618. /* inform generic HDLC layer of current DCD status */
  3619. spin_lock_irqsave(&info->lock, flags);
  3620. get_signals(info);
  3621. spin_unlock_irqrestore(&info->lock, flags);
  3622. hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
  3623. return 0;
  3624. }
  3625. /**
  3626. * called by network layer when interface is disabled
  3627. * shutdown hardware and release resources
  3628. *
  3629. * dev pointer to network device structure
  3630. *
  3631. * returns 0 if success, otherwise error code
  3632. */
  3633. static int hdlcdev_close(struct net_device *dev)
  3634. {
  3635. MGSLPC_INFO *info = dev_to_port(dev);
  3636. unsigned long flags;
  3637. if (debug_level >= DEBUG_LEVEL_INFO)
  3638. printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
  3639. netif_stop_queue(dev);
  3640. /* shutdown adapter and release resources */
  3641. shutdown(info);
  3642. hdlc_close(dev);
  3643. spin_lock_irqsave(&info->netlock, flags);
  3644. info->netcount=0;
  3645. spin_unlock_irqrestore(&info->netlock, flags);
  3646. return 0;
  3647. }
  3648. /**
  3649. * called by network layer to process IOCTL call to network device
  3650. *
  3651. * dev pointer to network device structure
  3652. * ifr pointer to network interface request structure
  3653. * cmd IOCTL command code
  3654. *
  3655. * returns 0 if success, otherwise error code
  3656. */
  3657. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3658. {
  3659. const size_t size = sizeof(sync_serial_settings);
  3660. sync_serial_settings new_line;
  3661. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  3662. MGSLPC_INFO *info = dev_to_port(dev);
  3663. unsigned int flags;
  3664. if (debug_level >= DEBUG_LEVEL_INFO)
  3665. printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
  3666. /* return error if TTY interface open */
  3667. if (info->count)
  3668. return -EBUSY;
  3669. if (cmd != SIOCWANDEV)
  3670. return hdlc_ioctl(dev, ifr, cmd);
  3671. switch(ifr->ifr_settings.type) {
  3672. case IF_GET_IFACE: /* return current sync_serial_settings */
  3673. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  3674. if (ifr->ifr_settings.size < size) {
  3675. ifr->ifr_settings.size = size; /* data size wanted */
  3676. return -ENOBUFS;
  3677. }
  3678. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3679. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3680. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3681. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3682. switch (flags){
  3683. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  3684. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  3685. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  3686. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  3687. default: new_line.clock_type = CLOCK_DEFAULT;
  3688. }
  3689. new_line.clock_rate = info->params.clock_speed;
  3690. new_line.loopback = info->params.loopback ? 1:0;
  3691. if (copy_to_user(line, &new_line, size))
  3692. return -EFAULT;
  3693. return 0;
  3694. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  3695. if(!capable(CAP_NET_ADMIN))
  3696. return -EPERM;
  3697. if (copy_from_user(&new_line, line, size))
  3698. return -EFAULT;
  3699. switch (new_line.clock_type)
  3700. {
  3701. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  3702. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  3703. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  3704. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  3705. case CLOCK_DEFAULT: flags = info->params.flags &
  3706. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3707. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3708. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3709. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  3710. default: return -EINVAL;
  3711. }
  3712. if (new_line.loopback != 0 && new_line.loopback != 1)
  3713. return -EINVAL;
  3714. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3715. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3716. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3717. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3718. info->params.flags |= flags;
  3719. info->params.loopback = new_line.loopback;
  3720. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  3721. info->params.clock_speed = new_line.clock_rate;
  3722. else
  3723. info->params.clock_speed = 0;
  3724. /* if network interface up, reprogram hardware */
  3725. if (info->netcount)
  3726. mgslpc_program_hw(info);
  3727. return 0;
  3728. default:
  3729. return hdlc_ioctl(dev, ifr, cmd);
  3730. }
  3731. }
  3732. /**
  3733. * called by network layer when transmit timeout is detected
  3734. *
  3735. * dev pointer to network device structure
  3736. */
  3737. static void hdlcdev_tx_timeout(struct net_device *dev)
  3738. {
  3739. MGSLPC_INFO *info = dev_to_port(dev);
  3740. struct net_device_stats *stats = hdlc_stats(dev);
  3741. unsigned long flags;
  3742. if (debug_level >= DEBUG_LEVEL_INFO)
  3743. printk("hdlcdev_tx_timeout(%s)\n",dev->name);
  3744. stats->tx_errors++;
  3745. stats->tx_aborted_errors++;
  3746. spin_lock_irqsave(&info->lock,flags);
  3747. tx_stop(info);
  3748. spin_unlock_irqrestore(&info->lock,flags);
  3749. netif_wake_queue(dev);
  3750. }
  3751. /**
  3752. * called by device driver when transmit completes
  3753. * reenable network layer transmit if stopped
  3754. *
  3755. * info pointer to device instance information
  3756. */
  3757. static void hdlcdev_tx_done(MGSLPC_INFO *info)
  3758. {
  3759. if (netif_queue_stopped(info->netdev))
  3760. netif_wake_queue(info->netdev);
  3761. }
  3762. /**
  3763. * called by device driver when frame received
  3764. * pass frame to network layer
  3765. *
  3766. * info pointer to device instance information
  3767. * buf pointer to buffer contianing frame data
  3768. * size count of data bytes in buf
  3769. */
  3770. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
  3771. {
  3772. struct sk_buff *skb = dev_alloc_skb(size);
  3773. struct net_device *dev = info->netdev;
  3774. struct net_device_stats *stats = hdlc_stats(dev);
  3775. if (debug_level >= DEBUG_LEVEL_INFO)
  3776. printk("hdlcdev_rx(%s)\n",dev->name);
  3777. if (skb == NULL) {
  3778. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
  3779. stats->rx_dropped++;
  3780. return;
  3781. }
  3782. memcpy(skb_put(skb, size),buf,size);
  3783. skb->protocol = hdlc_type_trans(skb, info->netdev);
  3784. stats->rx_packets++;
  3785. stats->rx_bytes += size;
  3786. netif_rx(skb);
  3787. info->netdev->last_rx = jiffies;
  3788. }
  3789. /**
  3790. * called by device driver when adding device instance
  3791. * do generic HDLC initialization
  3792. *
  3793. * info pointer to device instance information
  3794. *
  3795. * returns 0 if success, otherwise error code
  3796. */
  3797. static int hdlcdev_init(MGSLPC_INFO *info)
  3798. {
  3799. int rc;
  3800. struct net_device *dev;
  3801. hdlc_device *hdlc;
  3802. /* allocate and initialize network and HDLC layer objects */
  3803. if (!(dev = alloc_hdlcdev(info))) {
  3804. printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
  3805. return -ENOMEM;
  3806. }
  3807. /* for network layer reporting purposes only */
  3808. dev->base_addr = info->io_base;
  3809. dev->irq = info->irq_level;
  3810. /* network layer callbacks and settings */
  3811. dev->do_ioctl = hdlcdev_ioctl;
  3812. dev->open = hdlcdev_open;
  3813. dev->stop = hdlcdev_close;
  3814. dev->tx_timeout = hdlcdev_tx_timeout;
  3815. dev->watchdog_timeo = 10*HZ;
  3816. dev->tx_queue_len = 50;
  3817. /* generic HDLC layer callbacks and settings */
  3818. hdlc = dev_to_hdlc(dev);
  3819. hdlc->attach = hdlcdev_attach;
  3820. hdlc->xmit = hdlcdev_xmit;
  3821. /* register objects with HDLC layer */
  3822. if ((rc = register_hdlc_device(dev))) {
  3823. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  3824. free_netdev(dev);
  3825. return rc;
  3826. }
  3827. info->netdev = dev;
  3828. return 0;
  3829. }
  3830. /**
  3831. * called by device driver when removing device instance
  3832. * do generic HDLC cleanup
  3833. *
  3834. * info pointer to device instance information
  3835. */
  3836. static void hdlcdev_exit(MGSLPC_INFO *info)
  3837. {
  3838. unregister_hdlc_device(info->netdev);
  3839. free_netdev(info->netdev);
  3840. info->netdev = NULL;
  3841. }
  3842. #endif /* CONFIG_HDLC */