at91_ether.c 37 KB

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  1. /*
  2. * Ethernet driver for the Atmel AT91RM9200 (Thunder)
  3. *
  4. * Copyright (C) 2003 SAN People (Pty) Ltd
  5. *
  6. * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
  7. * Initial version by Rick Bronson 01/11/2003
  8. *
  9. * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
  10. * (Polaroid Corporation)
  11. *
  12. * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * as published by the Free Software Foundation; either version
  17. * 2 of the License, or (at your option) any later version.
  18. */
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/mii.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/skbuff.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/ethtool.h>
  28. #include <linux/platform_data/macb.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/clk.h>
  31. #include <linux/gfp.h>
  32. #include <linux/phy.h>
  33. #include <asm/io.h>
  34. #include <asm/uaccess.h>
  35. #include <asm/mach-types.h>
  36. #include <asm/gpio.h>
  37. #include <mach/board.h>
  38. #include "at91_ether.h"
  39. #include "macb.h"
  40. #define DRV_NAME "at91_ether"
  41. #define DRV_VERSION "1.0"
  42. #define LINK_POLL_INTERVAL (HZ)
  43. /* ........................... PHY INTERFACE ........................... */
  44. /*
  45. * Enable the MDIO bit in MAC control register
  46. * When not called from an interrupt-handler, access to the PHY must be
  47. * protected by a spinlock.
  48. */
  49. static void enable_mdi(struct at91_private *lp)
  50. {
  51. unsigned long ctl;
  52. ctl = macb_readl(lp, NCR);
  53. macb_writel(lp, NCR, ctl | MACB_BIT(MPE)); /* enable management port */
  54. }
  55. /*
  56. * Disable the MDIO bit in the MAC control register
  57. */
  58. static void disable_mdi(struct at91_private *lp)
  59. {
  60. unsigned long ctl;
  61. ctl = macb_readl(lp, NCR);
  62. macb_writel(lp, NCR, ctl & ~MACB_BIT(MPE)); /* disable management port */
  63. }
  64. /*
  65. * Wait until the PHY operation is complete.
  66. */
  67. static inline void at91_phy_wait(struct at91_private *lp)
  68. {
  69. unsigned long timeout = jiffies + 2;
  70. while (!(macb_readl(lp, NSR) & MACB_BIT(IDLE))) {
  71. if (time_after(jiffies, timeout)) {
  72. printk("at91_ether: MIO timeout\n");
  73. break;
  74. }
  75. cpu_relax();
  76. }
  77. }
  78. /*
  79. * Write value to the a PHY register
  80. * Note: MDI interface is assumed to already have been enabled.
  81. */
  82. static void write_phy(struct at91_private *lp, unsigned char phy_addr, unsigned char address, unsigned int value)
  83. {
  84. macb_writel(lp, MAN, MACB_BF(SOF, MACB_MAN_SOF) | MACB_BF(CODE, MACB_MAN_CODE)
  85. | MACB_BF(RW, MACB_MAN_WRITE) | ((phy_addr & 0x1f) << 23)
  86. | (address << 18) | (value & ((1<<MACB_DATA_SIZE) - 1)));
  87. /* Wait until IDLE bit in Network Status register is cleared */
  88. at91_phy_wait(lp);
  89. }
  90. /*
  91. * Read value stored in a PHY register.
  92. * Note: MDI interface is assumed to already have been enabled.
  93. */
  94. static void read_phy(struct at91_private *lp, unsigned char phy_addr, unsigned char address, unsigned int *value)
  95. {
  96. macb_writel(lp, MAN, MACB_BF(SOF, MACB_MAN_SOF) | MACB_BF(CODE, MACB_MAN_CODE)
  97. | MACB_BF(RW, MACB_MAN_READ) | ((phy_addr & 0x1f) << 23)
  98. | (address << 18));
  99. /* Wait until IDLE bit in Network Status register is cleared */
  100. at91_phy_wait(lp);
  101. *value = macb_readl(lp, MAN) & ((1<<MACB_DATA_SIZE) - 1);
  102. }
  103. /* ........................... PHY MANAGEMENT .......................... */
  104. /*
  105. * Access the PHY to determine the current link speed and mode, and update the
  106. * MAC accordingly.
  107. * If no link or auto-negotiation is busy, then no changes are made.
  108. */
  109. static void update_linkspeed(struct net_device *dev, int silent)
  110. {
  111. struct at91_private *lp = netdev_priv(dev);
  112. unsigned int bmsr, bmcr, lpa, mac_cfg;
  113. unsigned int speed, duplex;
  114. if (!mii_link_ok(&lp->mii)) { /* no link */
  115. netif_carrier_off(dev);
  116. if (!silent)
  117. printk(KERN_INFO "%s: Link down.\n", dev->name);
  118. return;
  119. }
  120. /* Link up, or auto-negotiation still in progress */
  121. read_phy(lp, lp->phy_address, MII_BMSR, &bmsr);
  122. read_phy(lp, lp->phy_address, MII_BMCR, &bmcr);
  123. if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */
  124. if (!(bmsr & BMSR_ANEGCOMPLETE))
  125. return; /* Do nothing - another interrupt generated when negotiation complete */
  126. read_phy(lp, lp->phy_address, MII_LPA, &lpa);
  127. if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
  128. else speed = SPEED_10;
  129. if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
  130. else duplex = DUPLEX_HALF;
  131. } else {
  132. speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
  133. duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
  134. }
  135. /* Update the MAC */
  136. mac_cfg = macb_readl(lp, NCFGR) & ~(MACB_BIT(SPD) | MACB_BIT(FD));
  137. if (speed == SPEED_100) {
  138. if (duplex == DUPLEX_FULL) /* 100 Full Duplex */
  139. mac_cfg |= MACB_BIT(SPD) | MACB_BIT(FD);
  140. else /* 100 Half Duplex */
  141. mac_cfg |= MACB_BIT(SPD);
  142. } else {
  143. if (duplex == DUPLEX_FULL) /* 10 Full Duplex */
  144. mac_cfg |= MACB_BIT(FD);
  145. else {} /* 10 Half Duplex */
  146. }
  147. macb_writel(lp, NCFGR, mac_cfg);
  148. if (!silent)
  149. printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
  150. netif_carrier_on(dev);
  151. }
  152. /*
  153. * Handle interrupts from the PHY
  154. */
  155. static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
  156. {
  157. struct net_device *dev = (struct net_device *) dev_id;
  158. struct at91_private *lp = netdev_priv(dev);
  159. unsigned int phy;
  160. /*
  161. * This hander is triggered on both edges, but the PHY chips expect
  162. * level-triggering. We therefore have to check if the PHY actually has
  163. * an IRQ pending.
  164. */
  165. enable_mdi(lp);
  166. if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
  167. read_phy(lp, lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */
  168. if (!(phy & (1 << 0)))
  169. goto done;
  170. }
  171. else if (lp->phy_type == MII_LXT971A_ID) {
  172. read_phy(lp, lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */
  173. if (!(phy & (1 << 2)))
  174. goto done;
  175. }
  176. else if (lp->phy_type == MII_BCM5221_ID) {
  177. read_phy(lp, lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */
  178. if (!(phy & (1 << 0)))
  179. goto done;
  180. }
  181. else if (lp->phy_type == MII_KS8721_ID) {
  182. read_phy(lp, lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */
  183. if (!(phy & ((1 << 2) | 1)))
  184. goto done;
  185. }
  186. else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */
  187. read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &phy);
  188. if (!(phy & ((1 << 2) | 1)))
  189. goto done;
  190. }
  191. else if (lp->phy_type == MII_DP83848_ID) {
  192. read_phy(lp, lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */
  193. if (!(phy & (1 << 7)))
  194. goto done;
  195. }
  196. update_linkspeed(dev, 0);
  197. done:
  198. disable_mdi(lp);
  199. return IRQ_HANDLED;
  200. }
  201. /*
  202. * Initialize and enable the PHY interrupt for link-state changes
  203. */
  204. static void enable_phyirq(struct net_device *dev)
  205. {
  206. struct at91_private *lp = netdev_priv(dev);
  207. unsigned int dsintr, irq_number;
  208. int status;
  209. if (!gpio_is_valid(lp->board_data.phy_irq_pin)) {
  210. /*
  211. * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
  212. * or board does not have it connected.
  213. */
  214. mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
  215. return;
  216. }
  217. irq_number = gpio_to_irq(lp->board_data.phy_irq_pin);
  218. status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev);
  219. if (status) {
  220. printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status);
  221. return;
  222. }
  223. spin_lock_irq(&lp->lock);
  224. enable_mdi(lp);
  225. if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
  226. read_phy(lp, lp->phy_address, MII_DSINTR_REG, &dsintr);
  227. dsintr = dsintr & ~0xf00; /* clear bits 8..11 */
  228. write_phy(lp, lp->phy_address, MII_DSINTR_REG, dsintr);
  229. }
  230. else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
  231. read_phy(lp, lp->phy_address, MII_ISINTE_REG, &dsintr);
  232. dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */
  233. write_phy(lp, lp->phy_address, MII_ISINTE_REG, dsintr);
  234. }
  235. else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
  236. dsintr = (1 << 15) | ( 1 << 14);
  237. write_phy(lp, lp->phy_address, MII_BCMINTR_REG, dsintr);
  238. }
  239. else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
  240. dsintr = (1 << 10) | ( 1 << 8);
  241. write_phy(lp, lp->phy_address, MII_TPISTATUS, dsintr);
  242. }
  243. else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
  244. read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &dsintr);
  245. dsintr = dsintr | 0x500; /* set bits 8, 10 */
  246. write_phy(lp, lp->phy_address, MII_T78Q21INT_REG, dsintr);
  247. }
  248. else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
  249. read_phy(lp, lp->phy_address, MII_DPMISR_REG, &dsintr);
  250. dsintr = dsintr | 0x3c; /* set bits 2..5 */
  251. write_phy(lp, lp->phy_address, MII_DPMISR_REG, dsintr);
  252. read_phy(lp, lp->phy_address, MII_DPMICR_REG, &dsintr);
  253. dsintr = dsintr | 0x3; /* set bits 0,1 */
  254. write_phy(lp, lp->phy_address, MII_DPMICR_REG, dsintr);
  255. }
  256. disable_mdi(lp);
  257. spin_unlock_irq(&lp->lock);
  258. }
  259. /*
  260. * Disable the PHY interrupt
  261. */
  262. static void disable_phyirq(struct net_device *dev)
  263. {
  264. struct at91_private *lp = netdev_priv(dev);
  265. unsigned int dsintr;
  266. unsigned int irq_number;
  267. if (!gpio_is_valid(lp->board_data.phy_irq_pin)) {
  268. del_timer_sync(&lp->check_timer);
  269. return;
  270. }
  271. spin_lock_irq(&lp->lock);
  272. enable_mdi(lp);
  273. if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
  274. read_phy(lp, lp->phy_address, MII_DSINTR_REG, &dsintr);
  275. dsintr = dsintr | 0xf00; /* set bits 8..11 */
  276. write_phy(lp, lp->phy_address, MII_DSINTR_REG, dsintr);
  277. }
  278. else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
  279. read_phy(lp, lp->phy_address, MII_ISINTE_REG, &dsintr);
  280. dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */
  281. write_phy(lp, lp->phy_address, MII_ISINTE_REG, dsintr);
  282. }
  283. else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
  284. read_phy(lp, lp->phy_address, MII_BCMINTR_REG, &dsintr);
  285. dsintr = ~(1 << 14);
  286. write_phy(lp, lp->phy_address, MII_BCMINTR_REG, dsintr);
  287. }
  288. else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
  289. read_phy(lp, lp->phy_address, MII_TPISTATUS, &dsintr);
  290. dsintr = ~((1 << 10) | (1 << 8));
  291. write_phy(lp, lp->phy_address, MII_TPISTATUS, dsintr);
  292. }
  293. else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
  294. read_phy(lp, lp->phy_address, MII_T78Q21INT_REG, &dsintr);
  295. dsintr = dsintr & ~0x500; /* clear bits 8, 10 */
  296. write_phy(lp, lp->phy_address, MII_T78Q21INT_REG, dsintr);
  297. }
  298. else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
  299. read_phy(lp, lp->phy_address, MII_DPMICR_REG, &dsintr);
  300. dsintr = dsintr & ~0x3; /* clear bits 0, 1 */
  301. write_phy(lp, lp->phy_address, MII_DPMICR_REG, dsintr);
  302. read_phy(lp, lp->phy_address, MII_DPMISR_REG, &dsintr);
  303. dsintr = dsintr & ~0x3c; /* clear bits 2..5 */
  304. write_phy(lp, lp->phy_address, MII_DPMISR_REG, dsintr);
  305. }
  306. disable_mdi(lp);
  307. spin_unlock_irq(&lp->lock);
  308. irq_number = gpio_to_irq(lp->board_data.phy_irq_pin);
  309. free_irq(irq_number, dev); /* Free interrupt handler */
  310. }
  311. /*
  312. * Perform a software reset of the PHY.
  313. */
  314. #if 0
  315. static void reset_phy(struct net_device *dev)
  316. {
  317. struct at91_private *lp = netdev_priv(dev);
  318. unsigned int bmcr;
  319. spin_lock_irq(&lp->lock);
  320. enable_mdi(lp);
  321. /* Perform PHY reset */
  322. write_phy(lp, lp->phy_address, MII_BMCR, BMCR_RESET);
  323. /* Wait until PHY reset is complete */
  324. do {
  325. read_phy(lp, lp->phy_address, MII_BMCR, &bmcr);
  326. } while (!(bmcr & BMCR_RESET));
  327. disable_mdi(lp);
  328. spin_unlock_irq(&lp->lock);
  329. }
  330. #endif
  331. static void at91ether_check_link(unsigned long dev_id)
  332. {
  333. struct net_device *dev = (struct net_device *) dev_id;
  334. struct at91_private *lp = netdev_priv(dev);
  335. enable_mdi(lp);
  336. update_linkspeed(dev, 1);
  337. disable_mdi(lp);
  338. mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
  339. }
  340. /*
  341. * Perform any PHY-specific initialization.
  342. */
  343. static void __init initialize_phy(struct at91_private *lp)
  344. {
  345. unsigned int val;
  346. spin_lock_irq(&lp->lock);
  347. enable_mdi(lp);
  348. if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
  349. read_phy(lp, lp->phy_address, MII_DSCR_REG, &val);
  350. if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */
  351. lp->phy_media = PORT_FIBRE;
  352. } else if (machine_is_csb337()) {
  353. /* mix link activity status into LED2 link state */
  354. write_phy(lp, lp->phy_address, MII_LEDCTRL_REG, 0x0d22);
  355. } else if (machine_is_ecbat91())
  356. write_phy(lp, lp->phy_address, MII_LEDCTRL_REG, 0x156A);
  357. disable_mdi(lp);
  358. spin_unlock_irq(&lp->lock);
  359. }
  360. /* ......................... ADDRESS MANAGEMENT ........................ */
  361. /*
  362. * NOTE: Your bootloader must always set the MAC address correctly before
  363. * booting into Linux.
  364. *
  365. * - It must always set the MAC address after reset, even if it doesn't
  366. * happen to access the Ethernet while it's booting. Some versions of
  367. * U-Boot on the AT91RM9200-DK do not do this.
  368. *
  369. * - Likewise it must store the addresses in the correct byte order.
  370. * MicroMonitor (uMon) on the CSB337 does this incorrectly (and
  371. * continues to do so, for bug-compatibility).
  372. */
  373. static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo)
  374. {
  375. char addr[6];
  376. if (machine_is_csb337()) {
  377. addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */
  378. addr[4] = (lo & 0xff00) >> 8;
  379. addr[3] = (lo & 0xff0000) >> 16;
  380. addr[2] = (lo & 0xff000000) >> 24;
  381. addr[1] = (hi & 0xff);
  382. addr[0] = (hi & 0xff00) >> 8;
  383. }
  384. else {
  385. addr[0] = (lo & 0xff);
  386. addr[1] = (lo & 0xff00) >> 8;
  387. addr[2] = (lo & 0xff0000) >> 16;
  388. addr[3] = (lo & 0xff000000) >> 24;
  389. addr[4] = (hi & 0xff);
  390. addr[5] = (hi & 0xff00) >> 8;
  391. }
  392. if (is_valid_ether_addr(addr)) {
  393. memcpy(dev->dev_addr, &addr, 6);
  394. return 1;
  395. }
  396. return 0;
  397. }
  398. /*
  399. * Set the ethernet MAC address in dev->dev_addr
  400. */
  401. static void __init get_mac_address(struct net_device *dev)
  402. {
  403. struct at91_private *lp = netdev_priv(dev);
  404. /* Check Specific-Address 1 */
  405. if (unpack_mac_address(dev, macb_readl(lp, SA1T), macb_readl(lp, SA1B)))
  406. return;
  407. /* Check Specific-Address 2 */
  408. if (unpack_mac_address(dev, macb_readl(lp, SA2T), macb_readl(lp, SA2B)))
  409. return;
  410. /* Check Specific-Address 3 */
  411. if (unpack_mac_address(dev, macb_readl(lp, SA3T), macb_readl(lp, SA3B)))
  412. return;
  413. /* Check Specific-Address 4 */
  414. if (unpack_mac_address(dev, macb_readl(lp, SA4T), macb_readl(lp, SA4B)))
  415. return;
  416. printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
  417. }
  418. /*
  419. * Program the hardware MAC address from dev->dev_addr.
  420. */
  421. static void update_mac_address(struct net_device *dev)
  422. {
  423. struct at91_private *lp = netdev_priv(dev);
  424. macb_writel(lp, SA1B, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16)
  425. | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
  426. macb_writel(lp, SA1T, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
  427. macb_writel(lp, SA2B, 0);
  428. macb_writel(lp, SA2T, 0);
  429. }
  430. /*
  431. * Store the new hardware address in dev->dev_addr, and update the MAC.
  432. */
  433. static int set_mac_address(struct net_device *dev, void* addr)
  434. {
  435. struct sockaddr *address = addr;
  436. if (!is_valid_ether_addr(address->sa_data))
  437. return -EADDRNOTAVAIL;
  438. memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
  439. update_mac_address(dev);
  440. printk("%s: Setting MAC address to %pM\n", dev->name,
  441. dev->dev_addr);
  442. return 0;
  443. }
  444. static int inline hash_bit_value(int bitnr, __u8 *addr)
  445. {
  446. if (addr[bitnr / 8] & (1 << (bitnr % 8)))
  447. return 1;
  448. return 0;
  449. }
  450. /*
  451. * The hash address register is 64 bits long and takes up two locations in the memory map.
  452. * The least significant bits are stored in EMAC_HSL and the most significant
  453. * bits in EMAC_HSH.
  454. *
  455. * The unicast hash enable and the multicast hash enable bits in the network configuration
  456. * register enable the reception of hash matched frames. The destination address is
  457. * reduced to a 6 bit index into the 64 bit hash register using the following hash function.
  458. * The hash function is an exclusive or of every sixth bit of the destination address.
  459. * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
  460. * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
  461. * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
  462. * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
  463. * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
  464. * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
  465. * da[0] represents the least significant bit of the first byte received, that is, the multicast/
  466. * unicast indicator, and da[47] represents the most significant bit of the last byte
  467. * received.
  468. * If the hash index points to a bit that is set in the hash register then the frame will be
  469. * matched according to whether the frame is multicast or unicast.
  470. * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
  471. * the hash index points to a bit set in the hash register.
  472. * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
  473. * hash index points to a bit set in the hash register.
  474. * To receive all multicast frames, the hash register should be set with all ones and the
  475. * multicast hash enable bit should be set in the network configuration register.
  476. */
  477. /*
  478. * Return the hash index value for the specified address.
  479. */
  480. static int hash_get_index(__u8 *addr)
  481. {
  482. int i, j, bitval;
  483. int hash_index = 0;
  484. for (j = 0; j < 6; j++) {
  485. for (i = 0, bitval = 0; i < 8; i++)
  486. bitval ^= hash_bit_value(i*6 + j, addr);
  487. hash_index |= (bitval << j);
  488. }
  489. return hash_index;
  490. }
  491. /*
  492. * Add multicast addresses to the internal multicast-hash table.
  493. */
  494. static void at91ether_sethashtable(struct net_device *dev)
  495. {
  496. struct at91_private *lp = netdev_priv(dev);
  497. struct netdev_hw_addr *ha;
  498. unsigned long mc_filter[2];
  499. unsigned int bitnr;
  500. mc_filter[0] = mc_filter[1] = 0;
  501. netdev_for_each_mc_addr(ha, dev) {
  502. bitnr = hash_get_index(ha->addr);
  503. mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
  504. }
  505. macb_writel(lp, HRB, mc_filter[0]);
  506. macb_writel(lp, HRT, mc_filter[1]);
  507. }
  508. /*
  509. * Enable/Disable promiscuous and multicast modes.
  510. */
  511. static void at91ether_set_multicast_list(struct net_device *dev)
  512. {
  513. struct at91_private *lp = netdev_priv(dev);
  514. unsigned long cfg;
  515. cfg = macb_readl(lp, NCFGR);
  516. if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */
  517. cfg |= MACB_BIT(CAF);
  518. else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */
  519. cfg &= ~MACB_BIT(CAF);
  520. if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */
  521. macb_writel(lp, HRT, -1);
  522. macb_writel(lp, HRB, -1);
  523. cfg |= MACB_BIT(NCFGR_MTI);
  524. } else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */
  525. at91ether_sethashtable(dev);
  526. cfg |= MACB_BIT(NCFGR_MTI);
  527. } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */
  528. macb_writel(lp, HRT, 0);
  529. macb_writel(lp, HRB, 0);
  530. cfg &= ~MACB_BIT(NCFGR_MTI);
  531. }
  532. macb_writel(lp, NCFGR, cfg);
  533. }
  534. /* ......................... ETHTOOL SUPPORT ........................... */
  535. static int mdio_read(struct net_device *dev, int phy_id, int location)
  536. {
  537. struct at91_private *lp = netdev_priv(dev);
  538. unsigned int value;
  539. read_phy(lp, phy_id, location, &value);
  540. return value;
  541. }
  542. static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
  543. {
  544. struct at91_private *lp = netdev_priv(dev);
  545. write_phy(lp, phy_id, location, value);
  546. }
  547. static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  548. {
  549. struct at91_private *lp = netdev_priv(dev);
  550. int ret;
  551. spin_lock_irq(&lp->lock);
  552. enable_mdi(lp);
  553. ret = mii_ethtool_gset(&lp->mii, cmd);
  554. disable_mdi(lp);
  555. spin_unlock_irq(&lp->lock);
  556. if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */
  557. cmd->supported = SUPPORTED_FIBRE;
  558. cmd->port = PORT_FIBRE;
  559. }
  560. return ret;
  561. }
  562. static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  563. {
  564. struct at91_private *lp = netdev_priv(dev);
  565. int ret;
  566. spin_lock_irq(&lp->lock);
  567. enable_mdi(lp);
  568. ret = mii_ethtool_sset(&lp->mii, cmd);
  569. disable_mdi(lp);
  570. spin_unlock_irq(&lp->lock);
  571. return ret;
  572. }
  573. static int at91ether_nwayreset(struct net_device *dev)
  574. {
  575. struct at91_private *lp = netdev_priv(dev);
  576. int ret;
  577. spin_lock_irq(&lp->lock);
  578. enable_mdi(lp);
  579. ret = mii_nway_restart(&lp->mii);
  580. disable_mdi(lp);
  581. spin_unlock_irq(&lp->lock);
  582. return ret;
  583. }
  584. static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  585. {
  586. strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
  587. strlcpy(info->version, DRV_VERSION, sizeof(info->version));
  588. strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
  589. }
  590. static const struct ethtool_ops at91ether_ethtool_ops = {
  591. .get_settings = at91ether_get_settings,
  592. .set_settings = at91ether_set_settings,
  593. .get_drvinfo = at91ether_get_drvinfo,
  594. .nway_reset = at91ether_nwayreset,
  595. .get_link = ethtool_op_get_link,
  596. };
  597. static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  598. {
  599. struct at91_private *lp = netdev_priv(dev);
  600. int res;
  601. if (!netif_running(dev))
  602. return -EINVAL;
  603. spin_lock_irq(&lp->lock);
  604. enable_mdi(lp);
  605. res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
  606. disable_mdi(lp);
  607. spin_unlock_irq(&lp->lock);
  608. return res;
  609. }
  610. /* ................................ MAC ................................ */
  611. /*
  612. * Initialize and start the Receiver and Transmit subsystems
  613. */
  614. static void at91ether_start(struct net_device *dev)
  615. {
  616. struct at91_private *lp = netdev_priv(dev);
  617. struct recv_desc_bufs *dlist, *dlist_phys;
  618. int i;
  619. unsigned long ctl;
  620. dlist = lp->dlist;
  621. dlist_phys = lp->dlist_phys;
  622. for (i = 0; i < MAX_RX_DESCR; i++) {
  623. dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
  624. dlist->descriptors[i].size = 0;
  625. }
  626. /* Set the Wrap bit on the last descriptor */
  627. dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP;
  628. /* Reset buffer index */
  629. lp->rxBuffIndex = 0;
  630. /* Program address of descriptor list in Rx Buffer Queue register */
  631. macb_writel(lp, RBQP, (unsigned long) dlist_phys);
  632. /* Enable Receive and Transmit */
  633. ctl = macb_readl(lp, NCR);
  634. macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
  635. }
  636. /*
  637. * Open the ethernet interface
  638. */
  639. static int at91ether_open(struct net_device *dev)
  640. {
  641. struct at91_private *lp = netdev_priv(dev);
  642. unsigned long ctl;
  643. if (!is_valid_ether_addr(dev->dev_addr))
  644. return -EADDRNOTAVAIL;
  645. clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */
  646. /* Clear internal statistics */
  647. ctl = macb_readl(lp, NCR);
  648. macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
  649. /* Update the MAC address (incase user has changed it) */
  650. update_mac_address(dev);
  651. /* Enable PHY interrupt */
  652. enable_phyirq(dev);
  653. /* Enable MAC interrupts */
  654. macb_writel(lp, IER, MACB_BIT(RCOMP) | MACB_BIT(RXUBR)
  655. | MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE) | MACB_BIT(TCOMP)
  656. | MACB_BIT(ISR_ROVR) | MACB_BIT(HRESP));
  657. /* Determine current link speed */
  658. spin_lock_irq(&lp->lock);
  659. enable_mdi(lp);
  660. update_linkspeed(dev, 0);
  661. disable_mdi(lp);
  662. spin_unlock_irq(&lp->lock);
  663. at91ether_start(dev);
  664. netif_start_queue(dev);
  665. return 0;
  666. }
  667. /*
  668. * Close the interface
  669. */
  670. static int at91ether_close(struct net_device *dev)
  671. {
  672. struct at91_private *lp = netdev_priv(dev);
  673. unsigned long ctl;
  674. /* Disable Receiver and Transmitter */
  675. ctl = macb_readl(lp, NCR);
  676. macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
  677. /* Disable PHY interrupt */
  678. disable_phyirq(dev);
  679. /* Disable MAC interrupts */
  680. macb_writel(lp, IDR, MACB_BIT(RCOMP) | MACB_BIT(RXUBR)
  681. | MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)
  682. | MACB_BIT(TCOMP) | MACB_BIT(ISR_ROVR)
  683. | MACB_BIT(HRESP));
  684. netif_stop_queue(dev);
  685. clk_disable(lp->ether_clk); /* Disable Peripheral clock */
  686. return 0;
  687. }
  688. /*
  689. * Transmit packet.
  690. */
  691. static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
  692. {
  693. struct at91_private *lp = netdev_priv(dev);
  694. if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
  695. netif_stop_queue(dev);
  696. /* Store packet information (to free when Tx completed) */
  697. lp->skb = skb;
  698. lp->skb_length = skb->len;
  699. lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
  700. dev->stats.tx_bytes += skb->len;
  701. /* Set address of the data in the Transmit Address register */
  702. macb_writel(lp, TAR, lp->skb_physaddr);
  703. /* Set length of the packet in the Transmit Control register */
  704. macb_writel(lp, TCR, skb->len);
  705. } else {
  706. printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n");
  707. return NETDEV_TX_BUSY; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
  708. on this skb, he also reports -ENETDOWN and printk's, so either
  709. we free and return(0) or don't free and return 1 */
  710. }
  711. return NETDEV_TX_OK;
  712. }
  713. /*
  714. * Update the current statistics from the internal statistics registers.
  715. */
  716. static struct net_device_stats *at91ether_stats(struct net_device *dev)
  717. {
  718. struct at91_private *lp = netdev_priv(dev);
  719. int ale, lenerr, seqe, lcol, ecol;
  720. if (netif_running(dev)) {
  721. dev->stats.rx_packets += macb_readl(lp, FRO); /* Good frames received */
  722. ale = macb_readl(lp, ALE);
  723. dev->stats.rx_frame_errors += ale; /* Alignment errors */
  724. lenerr = macb_readl(lp, ELE) + macb_readl(lp, USF);
  725. dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
  726. seqe = macb_readl(lp, FCSE);
  727. dev->stats.rx_crc_errors += seqe; /* CRC error */
  728. dev->stats.rx_fifo_errors += macb_readl(lp, RRE);/* Receive buffer not available */
  729. dev->stats.rx_errors += (ale + lenerr + seqe
  730. + macb_readl(lp, RSE) + macb_readl(lp, RJA));
  731. dev->stats.tx_packets += macb_readl(lp, FTO); /* Frames successfully transmitted */
  732. dev->stats.tx_fifo_errors += macb_readl(lp, TUND); /* Transmit FIFO underruns */
  733. dev->stats.tx_carrier_errors += macb_readl(lp, CSE); /* Carrier Sense errors */
  734. dev->stats.tx_heartbeat_errors += macb_readl(lp, STE);/* Heartbeat error */
  735. lcol = macb_readl(lp, LCOL);
  736. ecol = macb_readl(lp, EXCOL);
  737. dev->stats.tx_window_errors += lcol; /* Late collisions */
  738. dev->stats.tx_aborted_errors += ecol; /* 16 collisions */
  739. dev->stats.collisions += (macb_readl(lp, SCF) + macb_readl(lp, MCF) + lcol + ecol);
  740. }
  741. return &dev->stats;
  742. }
  743. /*
  744. * Extract received frame from buffer descriptors and sent to upper layers.
  745. * (Called from interrupt context)
  746. */
  747. static void at91ether_rx(struct net_device *dev)
  748. {
  749. struct at91_private *lp = netdev_priv(dev);
  750. struct recv_desc_bufs *dlist;
  751. unsigned char *p_recv;
  752. struct sk_buff *skb;
  753. unsigned int pktlen;
  754. dlist = lp->dlist;
  755. while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
  756. p_recv = dlist->recv_buf[lp->rxBuffIndex];
  757. pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */
  758. skb = netdev_alloc_skb(dev, pktlen + 2);
  759. if (skb != NULL) {
  760. skb_reserve(skb, 2);
  761. memcpy(skb_put(skb, pktlen), p_recv, pktlen);
  762. skb->protocol = eth_type_trans(skb, dev);
  763. dev->stats.rx_bytes += pktlen;
  764. netif_rx(skb);
  765. }
  766. else {
  767. dev->stats.rx_dropped += 1;
  768. printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
  769. }
  770. if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
  771. dev->stats.multicast++;
  772. dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */
  773. if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */
  774. lp->rxBuffIndex = 0;
  775. else
  776. lp->rxBuffIndex++;
  777. }
  778. }
  779. /*
  780. * MAC interrupt handler
  781. */
  782. static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
  783. {
  784. struct net_device *dev = (struct net_device *) dev_id;
  785. struct at91_private *lp = netdev_priv(dev);
  786. unsigned long intstatus, ctl;
  787. /* MAC Interrupt Status register indicates what interrupts are pending.
  788. It is automatically cleared once read. */
  789. intstatus = macb_readl(lp, ISR);
  790. if (intstatus & MACB_BIT(RCOMP)) /* Receive complete */
  791. at91ether_rx(dev);
  792. if (intstatus & MACB_BIT(TCOMP)) { /* Transmit complete */
  793. /* The TCOM bit is set even if the transmission failed. */
  794. if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
  795. dev->stats.tx_errors += 1;
  796. if (lp->skb) {
  797. dev_kfree_skb_irq(lp->skb);
  798. lp->skb = NULL;
  799. dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
  800. }
  801. netif_wake_queue(dev);
  802. }
  803. /* Work-around for Errata #11 */
  804. if (intstatus & MACB_BIT(RXUBR)) {
  805. ctl = macb_readl(lp, NCR);
  806. macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
  807. macb_writel(lp, NCR, ctl | MACB_BIT(RE));
  808. }
  809. if (intstatus & MACB_BIT(ISR_ROVR))
  810. printk("%s: ROVR error\n", dev->name);
  811. return IRQ_HANDLED;
  812. }
  813. #ifdef CONFIG_NET_POLL_CONTROLLER
  814. static void at91ether_poll_controller(struct net_device *dev)
  815. {
  816. unsigned long flags;
  817. local_irq_save(flags);
  818. at91ether_interrupt(dev->irq, dev);
  819. local_irq_restore(flags);
  820. }
  821. #endif
  822. static const struct net_device_ops at91ether_netdev_ops = {
  823. .ndo_open = at91ether_open,
  824. .ndo_stop = at91ether_close,
  825. .ndo_start_xmit = at91ether_start_xmit,
  826. .ndo_get_stats = at91ether_stats,
  827. .ndo_set_rx_mode = at91ether_set_multicast_list,
  828. .ndo_set_mac_address = set_mac_address,
  829. .ndo_do_ioctl = at91ether_ioctl,
  830. .ndo_validate_addr = eth_validate_addr,
  831. .ndo_change_mtu = eth_change_mtu,
  832. #ifdef CONFIG_NET_POLL_CONTROLLER
  833. .ndo_poll_controller = at91ether_poll_controller,
  834. #endif
  835. };
  836. /*
  837. * Detect the PHY type, and its address.
  838. */
  839. static int __init at91ether_phy_detect(struct at91_private *lp)
  840. {
  841. unsigned int phyid1, phyid2;
  842. unsigned long phy_id;
  843. unsigned short phy_address = 0;
  844. while (phy_address < PHY_MAX_ADDR) {
  845. /* Read the PHY ID registers */
  846. enable_mdi(lp);
  847. read_phy(lp, phy_address, MII_PHYSID1, &phyid1);
  848. read_phy(lp, phy_address, MII_PHYSID2, &phyid2);
  849. disable_mdi(lp);
  850. phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
  851. switch (phy_id) {
  852. case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
  853. case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
  854. case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
  855. case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
  856. case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
  857. case MII_DP83847_ID: /* National Semiconductor DP83847: */
  858. case MII_DP83848_ID: /* National Semiconductor DP83848: */
  859. case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
  860. case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
  861. case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
  862. case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
  863. /* store detected values */
  864. lp->phy_type = phy_id; /* Type of PHY connected */
  865. lp->phy_address = phy_address; /* MDI address of PHY */
  866. return 1;
  867. }
  868. phy_address++;
  869. }
  870. return 0; /* not detected */
  871. }
  872. /*
  873. * Detect MAC & PHY and perform ethernet interface initialization
  874. */
  875. static int __init at91ether_probe(struct platform_device *pdev)
  876. {
  877. struct macb_platform_data *board_data = pdev->dev.platform_data;
  878. struct resource *regs;
  879. struct net_device *dev;
  880. struct at91_private *lp;
  881. int res;
  882. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  883. if (!regs)
  884. return -ENOENT;
  885. dev = alloc_etherdev(sizeof(struct at91_private));
  886. if (!dev)
  887. return -ENOMEM;
  888. lp = netdev_priv(dev);
  889. lp->board_data = *board_data;
  890. spin_lock_init(&lp->lock);
  891. dev->base_addr = regs->start; /* physical base address */
  892. lp->regs = ioremap(regs->start, regs->end - regs->start + 1);
  893. if (!lp->regs) {
  894. res = -ENOMEM;
  895. goto err_free_dev;
  896. }
  897. /* Clock */
  898. lp->ether_clk = clk_get(&pdev->dev, "ether_clk");
  899. if (IS_ERR(lp->ether_clk)) {
  900. res = PTR_ERR(lp->ether_clk);
  901. goto err_ioumap;
  902. }
  903. clk_enable(lp->ether_clk);
  904. /* Install the interrupt handler */
  905. dev->irq = platform_get_irq(pdev, 0);
  906. if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
  907. res = -EBUSY;
  908. goto err_disable_clock;
  909. }
  910. /* Allocate memory for DMA Receive descriptors */
  911. lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
  912. if (lp->dlist == NULL) {
  913. res = -ENOMEM;
  914. goto err_free_irq;
  915. }
  916. ether_setup(dev);
  917. dev->netdev_ops = &at91ether_netdev_ops;
  918. dev->ethtool_ops = &at91ether_ethtool_ops;
  919. platform_set_drvdata(pdev, dev);
  920. SET_NETDEV_DEV(dev, &pdev->dev);
  921. get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
  922. update_mac_address(dev); /* Program ethernet address into MAC */
  923. macb_writel(lp, NCR, 0);
  924. if (board_data->is_rmii)
  925. macb_writel(lp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG) | MACB_BIT(RM9200_RMII));
  926. else
  927. macb_writel(lp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
  928. /* Detect PHY */
  929. if (!at91ether_phy_detect(lp)) {
  930. printk(KERN_ERR "at91_ether: Could not detect ethernet PHY\n");
  931. res = -ENODEV;
  932. goto err_free_dmamem;
  933. }
  934. initialize_phy(lp);
  935. lp->mii.dev = dev; /* Support for ethtool */
  936. lp->mii.mdio_read = mdio_read;
  937. lp->mii.mdio_write = mdio_write;
  938. lp->mii.phy_id = lp->phy_address;
  939. lp->mii.phy_id_mask = 0x1f;
  940. lp->mii.reg_num_mask = 0x1f;
  941. /* Register the network interface */
  942. res = register_netdev(dev);
  943. if (res)
  944. goto err_free_dmamem;
  945. /* Determine current link speed */
  946. spin_lock_irq(&lp->lock);
  947. enable_mdi(lp);
  948. update_linkspeed(dev, 0);
  949. disable_mdi(lp);
  950. spin_unlock_irq(&lp->lock);
  951. netif_carrier_off(dev); /* will be enabled in open() */
  952. /* If board has no PHY IRQ, use a timer to poll the PHY */
  953. if (gpio_is_valid(lp->board_data.phy_irq_pin)) {
  954. gpio_request(board_data->phy_irq_pin, "ethernet_phy");
  955. } else {
  956. /* If board has no PHY IRQ, use a timer to poll the PHY */
  957. init_timer(&lp->check_timer);
  958. lp->check_timer.data = (unsigned long)dev;
  959. lp->check_timer.function = at91ether_check_link;
  960. }
  961. /* Display ethernet banner */
  962. printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n",
  963. dev->name, (uint) dev->base_addr, dev->irq,
  964. macb_readl(lp, NCFGR) & MACB_BIT(SPD) ? "100-" : "10-",
  965. macb_readl(lp, NCFGR) & MACB_BIT(FD) ? "FullDuplex" : "HalfDuplex",
  966. dev->dev_addr);
  967. if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
  968. printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
  969. else if (lp->phy_type == MII_LXT971A_ID)
  970. printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
  971. else if (lp->phy_type == MII_RTL8201_ID)
  972. printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
  973. else if (lp->phy_type == MII_BCM5221_ID)
  974. printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
  975. else if (lp->phy_type == MII_DP83847_ID)
  976. printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
  977. else if (lp->phy_type == MII_DP83848_ID)
  978. printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
  979. else if (lp->phy_type == MII_AC101L_ID)
  980. printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
  981. else if (lp->phy_type == MII_KS8721_ID)
  982. printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
  983. else if (lp->phy_type == MII_T78Q21x3_ID)
  984. printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
  985. else if (lp->phy_type == MII_LAN83C185_ID)
  986. printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
  987. clk_disable(lp->ether_clk); /* Disable Peripheral clock */
  988. return 0;
  989. err_free_dmamem:
  990. platform_set_drvdata(pdev, NULL);
  991. dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
  992. err_free_irq:
  993. free_irq(dev->irq, dev);
  994. err_disable_clock:
  995. clk_disable(lp->ether_clk);
  996. clk_put(lp->ether_clk);
  997. err_ioumap:
  998. iounmap(lp->regs);
  999. err_free_dev:
  1000. free_netdev(dev);
  1001. return res;
  1002. }
  1003. static int __devexit at91ether_remove(struct platform_device *pdev)
  1004. {
  1005. struct net_device *dev = platform_get_drvdata(pdev);
  1006. struct at91_private *lp = netdev_priv(dev);
  1007. if (gpio_is_valid(lp->board_data.phy_irq_pin))
  1008. gpio_free(lp->board_data.phy_irq_pin);
  1009. unregister_netdev(dev);
  1010. free_irq(dev->irq, dev);
  1011. dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
  1012. clk_put(lp->ether_clk);
  1013. platform_set_drvdata(pdev, NULL);
  1014. free_netdev(dev);
  1015. return 0;
  1016. }
  1017. #ifdef CONFIG_PM
  1018. static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
  1019. {
  1020. struct net_device *net_dev = platform_get_drvdata(pdev);
  1021. struct at91_private *lp = netdev_priv(net_dev);
  1022. if (netif_running(net_dev)) {
  1023. if (gpio_is_valid(lp->board_data.phy_irq_pin)) {
  1024. int phy_irq = gpio_to_irq(lp->board_data.phy_irq_pin);
  1025. disable_irq(phy_irq);
  1026. }
  1027. netif_stop_queue(net_dev);
  1028. netif_device_detach(net_dev);
  1029. clk_disable(lp->ether_clk);
  1030. }
  1031. return 0;
  1032. }
  1033. static int at91ether_resume(struct platform_device *pdev)
  1034. {
  1035. struct net_device *net_dev = platform_get_drvdata(pdev);
  1036. struct at91_private *lp = netdev_priv(net_dev);
  1037. if (netif_running(net_dev)) {
  1038. clk_enable(lp->ether_clk);
  1039. netif_device_attach(net_dev);
  1040. netif_start_queue(net_dev);
  1041. if (gpio_is_valid(lp->board_data.phy_irq_pin)) {
  1042. int phy_irq = gpio_to_irq(lp->board_data.phy_irq_pin);
  1043. enable_irq(phy_irq);
  1044. }
  1045. }
  1046. return 0;
  1047. }
  1048. #else
  1049. #define at91ether_suspend NULL
  1050. #define at91ether_resume NULL
  1051. #endif
  1052. static struct platform_driver at91ether_driver = {
  1053. .remove = __devexit_p(at91ether_remove),
  1054. .suspend = at91ether_suspend,
  1055. .resume = at91ether_resume,
  1056. .driver = {
  1057. .name = DRV_NAME,
  1058. .owner = THIS_MODULE,
  1059. },
  1060. };
  1061. static int __init at91ether_init(void)
  1062. {
  1063. return platform_driver_probe(&at91ether_driver, at91ether_probe);
  1064. }
  1065. static void __exit at91ether_exit(void)
  1066. {
  1067. platform_driver_unregister(&at91ether_driver);
  1068. }
  1069. module_init(at91ether_init)
  1070. module_exit(at91ether_exit)
  1071. MODULE_LICENSE("GPL");
  1072. MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
  1073. MODULE_AUTHOR("Andrew Victor");
  1074. MODULE_ALIAS("platform:" DRV_NAME);