intel_cacheinfo.c 27 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992
  1. /*
  2. * Routines to indentify caches on Intel CPU.
  3. *
  4. * Changes:
  5. * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
  6. * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
  7. * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
  8. */
  9. #include <linux/init.h>
  10. #include <linux/slab.h>
  11. #include <linux/device.h>
  12. #include <linux/compiler.h>
  13. #include <linux/cpu.h>
  14. #include <linux/sched.h>
  15. #include <linux/pci.h>
  16. #include <asm/processor.h>
  17. #include <asm/smp.h>
  18. #include <asm/k8.h>
  19. #define LVL_1_INST 1
  20. #define LVL_1_DATA 2
  21. #define LVL_2 3
  22. #define LVL_3 4
  23. #define LVL_TRACE 5
  24. struct _cache_table
  25. {
  26. unsigned char descriptor;
  27. char cache_type;
  28. short size;
  29. };
  30. /* all the cache descriptor types we care about (no TLB or trace cache entries) */
  31. static const struct _cache_table __cpuinitconst cache_table[] =
  32. {
  33. { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
  34. { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
  35. { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
  36. { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
  37. { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
  38. { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
  39. { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
  40. { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
  41. { 0x23, LVL_3, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */
  42. { 0x25, LVL_3, 2048 }, /* 8-way set assoc, sectored cache, 64 byte line size */
  43. { 0x29, LVL_3, 4096 }, /* 8-way set assoc, sectored cache, 64 byte line size */
  44. { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
  45. { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
  46. { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
  47. { 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
  48. { 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
  49. { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
  50. { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
  51. { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
  52. { 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */
  53. { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
  54. { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
  55. { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
  56. { 0x44, LVL_2, 1024 }, /* 4-way set assoc, 32 byte line size */
  57. { 0x45, LVL_2, 2048 }, /* 4-way set assoc, 32 byte line size */
  58. { 0x46, LVL_3, 4096 }, /* 4-way set assoc, 64 byte line size */
  59. { 0x47, LVL_3, 8192 }, /* 8-way set assoc, 64 byte line size */
  60. { 0x49, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
  61. { 0x4a, LVL_3, 6144 }, /* 12-way set assoc, 64 byte line size */
  62. { 0x4b, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
  63. { 0x4c, LVL_3, 12288 }, /* 12-way set assoc, 64 byte line size */
  64. { 0x4d, LVL_3, 16384 }, /* 16-way set assoc, 64 byte line size */
  65. { 0x4e, LVL_2, 6144 }, /* 24-way set assoc, 64 byte line size */
  66. { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
  67. { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
  68. { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
  69. { 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
  70. { 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
  71. { 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
  72. { 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
  73. { 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */
  74. { 0x78, LVL_2, 1024 }, /* 4-way set assoc, 64 byte line size */
  75. { 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
  76. { 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
  77. { 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
  78. { 0x7c, LVL_2, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */
  79. { 0x7d, LVL_2, 2048 }, /* 8-way set assoc, 64 byte line size */
  80. { 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */
  81. { 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */
  82. { 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */
  83. { 0x84, LVL_2, 1024 }, /* 8-way set assoc, 32 byte line size */
  84. { 0x85, LVL_2, 2048 }, /* 8-way set assoc, 32 byte line size */
  85. { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
  86. { 0x87, LVL_2, 1024 }, /* 8-way set assoc, 64 byte line size */
  87. { 0xd0, LVL_3, 512 }, /* 4-way set assoc, 64 byte line size */
  88. { 0xd1, LVL_3, 1024 }, /* 4-way set assoc, 64 byte line size */
  89. { 0xd2, LVL_3, 2048 }, /* 4-way set assoc, 64 byte line size */
  90. { 0xd6, LVL_3, 1024 }, /* 8-way set assoc, 64 byte line size */
  91. { 0xd7, LVL_3, 2038 }, /* 8-way set assoc, 64 byte line size */
  92. { 0xd8, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */
  93. { 0xdc, LVL_3, 2048 }, /* 12-way set assoc, 64 byte line size */
  94. { 0xdd, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */
  95. { 0xde, LVL_3, 8192 }, /* 12-way set assoc, 64 byte line size */
  96. { 0xe2, LVL_3, 2048 }, /* 16-way set assoc, 64 byte line size */
  97. { 0xe3, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
  98. { 0xe4, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
  99. { 0x00, 0, 0}
  100. };
  101. enum _cache_type
  102. {
  103. CACHE_TYPE_NULL = 0,
  104. CACHE_TYPE_DATA = 1,
  105. CACHE_TYPE_INST = 2,
  106. CACHE_TYPE_UNIFIED = 3
  107. };
  108. union _cpuid4_leaf_eax {
  109. struct {
  110. enum _cache_type type:5;
  111. unsigned int level:3;
  112. unsigned int is_self_initializing:1;
  113. unsigned int is_fully_associative:1;
  114. unsigned int reserved:4;
  115. unsigned int num_threads_sharing:12;
  116. unsigned int num_cores_on_die:6;
  117. } split;
  118. u32 full;
  119. };
  120. union _cpuid4_leaf_ebx {
  121. struct {
  122. unsigned int coherency_line_size:12;
  123. unsigned int physical_line_partition:10;
  124. unsigned int ways_of_associativity:10;
  125. } split;
  126. u32 full;
  127. };
  128. union _cpuid4_leaf_ecx {
  129. struct {
  130. unsigned int number_of_sets:32;
  131. } split;
  132. u32 full;
  133. };
  134. struct _cpuid4_info {
  135. union _cpuid4_leaf_eax eax;
  136. union _cpuid4_leaf_ebx ebx;
  137. union _cpuid4_leaf_ecx ecx;
  138. unsigned long size;
  139. unsigned long can_disable;
  140. DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
  141. };
  142. /* subset of above _cpuid4_info w/o shared_cpu_map */
  143. struct _cpuid4_info_regs {
  144. union _cpuid4_leaf_eax eax;
  145. union _cpuid4_leaf_ebx ebx;
  146. union _cpuid4_leaf_ecx ecx;
  147. unsigned long size;
  148. unsigned long can_disable;
  149. };
  150. unsigned short num_cache_leaves;
  151. /* AMD doesn't have CPUID4. Emulate it here to report the same
  152. information to the user. This makes some assumptions about the machine:
  153. L2 not shared, no SMT etc. that is currently true on AMD CPUs.
  154. In theory the TLBs could be reported as fake type (they are in "dummy").
  155. Maybe later */
  156. union l1_cache {
  157. struct {
  158. unsigned line_size : 8;
  159. unsigned lines_per_tag : 8;
  160. unsigned assoc : 8;
  161. unsigned size_in_kb : 8;
  162. };
  163. unsigned val;
  164. };
  165. union l2_cache {
  166. struct {
  167. unsigned line_size : 8;
  168. unsigned lines_per_tag : 4;
  169. unsigned assoc : 4;
  170. unsigned size_in_kb : 16;
  171. };
  172. unsigned val;
  173. };
  174. union l3_cache {
  175. struct {
  176. unsigned line_size : 8;
  177. unsigned lines_per_tag : 4;
  178. unsigned assoc : 4;
  179. unsigned res : 2;
  180. unsigned size_encoded : 14;
  181. };
  182. unsigned val;
  183. };
  184. static const unsigned short __cpuinitconst assocs[] = {
  185. [1] = 1, [2] = 2, [4] = 4, [6] = 8,
  186. [8] = 16, [0xa] = 32, [0xb] = 48,
  187. [0xc] = 64,
  188. [0xf] = 0xffff // ??
  189. };
  190. static const unsigned char __cpuinitconst levels[] = { 1, 1, 2, 3 };
  191. static const unsigned char __cpuinitconst types[] = { 1, 2, 3, 3 };
  192. static void __cpuinit
  193. amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
  194. union _cpuid4_leaf_ebx *ebx,
  195. union _cpuid4_leaf_ecx *ecx)
  196. {
  197. unsigned dummy;
  198. unsigned line_size, lines_per_tag, assoc, size_in_kb;
  199. union l1_cache l1i, l1d;
  200. union l2_cache l2;
  201. union l3_cache l3;
  202. union l1_cache *l1 = &l1d;
  203. eax->full = 0;
  204. ebx->full = 0;
  205. ecx->full = 0;
  206. cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
  207. cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val);
  208. switch (leaf) {
  209. case 1:
  210. l1 = &l1i;
  211. case 0:
  212. if (!l1->val)
  213. return;
  214. assoc = l1->assoc;
  215. line_size = l1->line_size;
  216. lines_per_tag = l1->lines_per_tag;
  217. size_in_kb = l1->size_in_kb;
  218. break;
  219. case 2:
  220. if (!l2.val)
  221. return;
  222. assoc = l2.assoc;
  223. line_size = l2.line_size;
  224. lines_per_tag = l2.lines_per_tag;
  225. /* cpu_data has errata corrections for K7 applied */
  226. size_in_kb = current_cpu_data.x86_cache_size;
  227. break;
  228. case 3:
  229. if (!l3.val)
  230. return;
  231. assoc = l3.assoc;
  232. line_size = l3.line_size;
  233. lines_per_tag = l3.lines_per_tag;
  234. size_in_kb = l3.size_encoded * 512;
  235. break;
  236. default:
  237. return;
  238. }
  239. eax->split.is_self_initializing = 1;
  240. eax->split.type = types[leaf];
  241. eax->split.level = levels[leaf];
  242. if (leaf == 3)
  243. eax->split.num_threads_sharing = current_cpu_data.x86_max_cores - 1;
  244. else
  245. eax->split.num_threads_sharing = 0;
  246. eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
  247. if (assoc == 0xf)
  248. eax->split.is_fully_associative = 1;
  249. ebx->split.coherency_line_size = line_size - 1;
  250. ebx->split.ways_of_associativity = assocs[assoc] - 1;
  251. ebx->split.physical_line_partition = lines_per_tag - 1;
  252. ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
  253. (ebx->split.ways_of_associativity + 1) - 1;
  254. }
  255. static void __cpuinit
  256. amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
  257. {
  258. if (index < 3)
  259. return;
  260. if (boot_cpu_data.x86 == 0x11)
  261. return;
  262. /* see erratum #382 */
  263. if ((boot_cpu_data.x86 == 0x10) && (boot_cpu_data.x86_model < 0x8))
  264. return;
  265. this_leaf->can_disable = 1;
  266. }
  267. static int
  268. __cpuinit cpuid4_cache_lookup_regs(int index,
  269. struct _cpuid4_info_regs *this_leaf)
  270. {
  271. union _cpuid4_leaf_eax eax;
  272. union _cpuid4_leaf_ebx ebx;
  273. union _cpuid4_leaf_ecx ecx;
  274. unsigned edx;
  275. if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
  276. amd_cpuid4(index, &eax, &ebx, &ecx);
  277. if (boot_cpu_data.x86 >= 0x10)
  278. amd_check_l3_disable(index, this_leaf);
  279. } else {
  280. cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
  281. }
  282. if (eax.split.type == CACHE_TYPE_NULL)
  283. return -EIO; /* better error ? */
  284. this_leaf->eax = eax;
  285. this_leaf->ebx = ebx;
  286. this_leaf->ecx = ecx;
  287. this_leaf->size = (ecx.split.number_of_sets + 1) *
  288. (ebx.split.coherency_line_size + 1) *
  289. (ebx.split.physical_line_partition + 1) *
  290. (ebx.split.ways_of_associativity + 1);
  291. return 0;
  292. }
  293. static int __cpuinit find_num_cache_leaves(void)
  294. {
  295. unsigned int eax, ebx, ecx, edx;
  296. union _cpuid4_leaf_eax cache_eax;
  297. int i = -1;
  298. do {
  299. ++i;
  300. /* Do cpuid(4) loop to find out num_cache_leaves */
  301. cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
  302. cache_eax.full = eax;
  303. } while (cache_eax.split.type != CACHE_TYPE_NULL);
  304. return i;
  305. }
  306. unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
  307. {
  308. unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
  309. unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
  310. unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
  311. unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
  312. #ifdef CONFIG_X86_HT
  313. unsigned int cpu = c->cpu_index;
  314. #endif
  315. if (c->cpuid_level > 3) {
  316. static int is_initialized;
  317. if (is_initialized == 0) {
  318. /* Init num_cache_leaves from boot CPU */
  319. num_cache_leaves = find_num_cache_leaves();
  320. is_initialized++;
  321. }
  322. /*
  323. * Whenever possible use cpuid(4), deterministic cache
  324. * parameters cpuid leaf to find the cache details
  325. */
  326. for (i = 0; i < num_cache_leaves; i++) {
  327. struct _cpuid4_info_regs this_leaf;
  328. int retval;
  329. retval = cpuid4_cache_lookup_regs(i, &this_leaf);
  330. if (retval >= 0) {
  331. switch(this_leaf.eax.split.level) {
  332. case 1:
  333. if (this_leaf.eax.split.type ==
  334. CACHE_TYPE_DATA)
  335. new_l1d = this_leaf.size/1024;
  336. else if (this_leaf.eax.split.type ==
  337. CACHE_TYPE_INST)
  338. new_l1i = this_leaf.size/1024;
  339. break;
  340. case 2:
  341. new_l2 = this_leaf.size/1024;
  342. num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
  343. index_msb = get_count_order(num_threads_sharing);
  344. l2_id = c->apicid >> index_msb;
  345. break;
  346. case 3:
  347. new_l3 = this_leaf.size/1024;
  348. num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
  349. index_msb = get_count_order(num_threads_sharing);
  350. l3_id = c->apicid >> index_msb;
  351. break;
  352. default:
  353. break;
  354. }
  355. }
  356. }
  357. }
  358. /*
  359. * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
  360. * trace cache
  361. */
  362. if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) {
  363. /* supports eax=2 call */
  364. int j, n;
  365. unsigned int regs[4];
  366. unsigned char *dp = (unsigned char *)regs;
  367. int only_trace = 0;
  368. if (num_cache_leaves != 0 && c->x86 == 15)
  369. only_trace = 1;
  370. /* Number of times to iterate */
  371. n = cpuid_eax(2) & 0xFF;
  372. for ( i = 0 ; i < n ; i++ ) {
  373. cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
  374. /* If bit 31 is set, this is an unknown format */
  375. for ( j = 0 ; j < 3 ; j++ ) {
  376. if (regs[j] & (1 << 31)) regs[j] = 0;
  377. }
  378. /* Byte 0 is level count, not a descriptor */
  379. for ( j = 1 ; j < 16 ; j++ ) {
  380. unsigned char des = dp[j];
  381. unsigned char k = 0;
  382. /* look up this descriptor in the table */
  383. while (cache_table[k].descriptor != 0)
  384. {
  385. if (cache_table[k].descriptor == des) {
  386. if (only_trace && cache_table[k].cache_type != LVL_TRACE)
  387. break;
  388. switch (cache_table[k].cache_type) {
  389. case LVL_1_INST:
  390. l1i += cache_table[k].size;
  391. break;
  392. case LVL_1_DATA:
  393. l1d += cache_table[k].size;
  394. break;
  395. case LVL_2:
  396. l2 += cache_table[k].size;
  397. break;
  398. case LVL_3:
  399. l3 += cache_table[k].size;
  400. break;
  401. case LVL_TRACE:
  402. trace += cache_table[k].size;
  403. break;
  404. }
  405. break;
  406. }
  407. k++;
  408. }
  409. }
  410. }
  411. }
  412. if (new_l1d)
  413. l1d = new_l1d;
  414. if (new_l1i)
  415. l1i = new_l1i;
  416. if (new_l2) {
  417. l2 = new_l2;
  418. #ifdef CONFIG_X86_HT
  419. per_cpu(cpu_llc_id, cpu) = l2_id;
  420. #endif
  421. }
  422. if (new_l3) {
  423. l3 = new_l3;
  424. #ifdef CONFIG_X86_HT
  425. per_cpu(cpu_llc_id, cpu) = l3_id;
  426. #endif
  427. }
  428. if (trace)
  429. printk (KERN_INFO "CPU: Trace cache: %dK uops", trace);
  430. else if ( l1i )
  431. printk (KERN_INFO "CPU: L1 I cache: %dK", l1i);
  432. if (l1d)
  433. printk(", L1 D cache: %dK\n", l1d);
  434. else
  435. printk("\n");
  436. if (l2)
  437. printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
  438. if (l3)
  439. printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
  440. c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
  441. return l2;
  442. }
  443. #ifdef CONFIG_SYSFS
  444. /* pointer to _cpuid4_info array (for each cache leaf) */
  445. static DEFINE_PER_CPU(struct _cpuid4_info *, cpuid4_info);
  446. #define CPUID4_INFO_IDX(x, y) (&((per_cpu(cpuid4_info, x))[y]))
  447. #ifdef CONFIG_SMP
  448. static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
  449. {
  450. struct _cpuid4_info *this_leaf, *sibling_leaf;
  451. unsigned long num_threads_sharing;
  452. int index_msb, i;
  453. struct cpuinfo_x86 *c = &cpu_data(cpu);
  454. this_leaf = CPUID4_INFO_IDX(cpu, index);
  455. num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;
  456. if (num_threads_sharing == 1)
  457. cpumask_set_cpu(cpu, to_cpumask(this_leaf->shared_cpu_map));
  458. else {
  459. index_msb = get_count_order(num_threads_sharing);
  460. for_each_online_cpu(i) {
  461. if (cpu_data(i).apicid >> index_msb ==
  462. c->apicid >> index_msb) {
  463. cpumask_set_cpu(i,
  464. to_cpumask(this_leaf->shared_cpu_map));
  465. if (i != cpu && per_cpu(cpuid4_info, i)) {
  466. sibling_leaf =
  467. CPUID4_INFO_IDX(i, index);
  468. cpumask_set_cpu(cpu, to_cpumask(
  469. sibling_leaf->shared_cpu_map));
  470. }
  471. }
  472. }
  473. }
  474. }
  475. static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
  476. {
  477. struct _cpuid4_info *this_leaf, *sibling_leaf;
  478. int sibling;
  479. this_leaf = CPUID4_INFO_IDX(cpu, index);
  480. for_each_cpu(sibling, to_cpumask(this_leaf->shared_cpu_map)) {
  481. sibling_leaf = CPUID4_INFO_IDX(sibling, index);
  482. cpumask_clear_cpu(cpu,
  483. to_cpumask(sibling_leaf->shared_cpu_map));
  484. }
  485. }
  486. #else
  487. static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index) {}
  488. static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index) {}
  489. #endif
  490. static void __cpuinit free_cache_attributes(unsigned int cpu)
  491. {
  492. int i;
  493. for (i = 0; i < num_cache_leaves; i++)
  494. cache_remove_shared_cpu_map(cpu, i);
  495. kfree(per_cpu(cpuid4_info, cpu));
  496. per_cpu(cpuid4_info, cpu) = NULL;
  497. }
  498. static int
  499. __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
  500. {
  501. struct _cpuid4_info_regs *leaf_regs =
  502. (struct _cpuid4_info_regs *)this_leaf;
  503. return cpuid4_cache_lookup_regs(index, leaf_regs);
  504. }
  505. static void __cpuinit get_cpu_leaves(void *_retval)
  506. {
  507. int j, *retval = _retval, cpu = smp_processor_id();
  508. /* Do cpuid and store the results */
  509. for (j = 0; j < num_cache_leaves; j++) {
  510. struct _cpuid4_info *this_leaf;
  511. this_leaf = CPUID4_INFO_IDX(cpu, j);
  512. *retval = cpuid4_cache_lookup(j, this_leaf);
  513. if (unlikely(*retval < 0)) {
  514. int i;
  515. for (i = 0; i < j; i++)
  516. cache_remove_shared_cpu_map(cpu, i);
  517. break;
  518. }
  519. cache_shared_cpu_map_setup(cpu, j);
  520. }
  521. }
  522. static int __cpuinit detect_cache_attributes(unsigned int cpu)
  523. {
  524. int retval;
  525. if (num_cache_leaves == 0)
  526. return -ENOENT;
  527. per_cpu(cpuid4_info, cpu) = kzalloc(
  528. sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
  529. if (per_cpu(cpuid4_info, cpu) == NULL)
  530. return -ENOMEM;
  531. smp_call_function_single(cpu, get_cpu_leaves, &retval, true);
  532. if (retval) {
  533. kfree(per_cpu(cpuid4_info, cpu));
  534. per_cpu(cpuid4_info, cpu) = NULL;
  535. }
  536. return retval;
  537. }
  538. #include <linux/kobject.h>
  539. #include <linux/sysfs.h>
  540. extern struct sysdev_class cpu_sysdev_class; /* from drivers/base/cpu.c */
  541. /* pointer to kobject for cpuX/cache */
  542. static DEFINE_PER_CPU(struct kobject *, cache_kobject);
  543. struct _index_kobject {
  544. struct kobject kobj;
  545. unsigned int cpu;
  546. unsigned short index;
  547. };
  548. /* pointer to array of kobjects for cpuX/cache/indexY */
  549. static DEFINE_PER_CPU(struct _index_kobject *, index_kobject);
  550. #define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(index_kobject, x))[y]))
  551. #define show_one_plus(file_name, object, val) \
  552. static ssize_t show_##file_name \
  553. (struct _cpuid4_info *this_leaf, char *buf) \
  554. { \
  555. return sprintf (buf, "%lu\n", (unsigned long)this_leaf->object + val); \
  556. }
  557. show_one_plus(level, eax.split.level, 0);
  558. show_one_plus(coherency_line_size, ebx.split.coherency_line_size, 1);
  559. show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1);
  560. show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1);
  561. show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);
  562. static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
  563. {
  564. return sprintf (buf, "%luK\n", this_leaf->size / 1024);
  565. }
  566. static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
  567. int type, char *buf)
  568. {
  569. ptrdiff_t len = PTR_ALIGN(buf + PAGE_SIZE - 1, PAGE_SIZE) - buf;
  570. int n = 0;
  571. if (len > 1) {
  572. const struct cpumask *mask;
  573. mask = to_cpumask(this_leaf->shared_cpu_map);
  574. n = type?
  575. cpulist_scnprintf(buf, len-2, mask) :
  576. cpumask_scnprintf(buf, len-2, mask);
  577. buf[n++] = '\n';
  578. buf[n] = '\0';
  579. }
  580. return n;
  581. }
  582. static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf)
  583. {
  584. return show_shared_cpu_map_func(leaf, 0, buf);
  585. }
  586. static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf)
  587. {
  588. return show_shared_cpu_map_func(leaf, 1, buf);
  589. }
  590. static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
  591. {
  592. switch (this_leaf->eax.split.type) {
  593. case CACHE_TYPE_DATA:
  594. return sprintf(buf, "Data\n");
  595. case CACHE_TYPE_INST:
  596. return sprintf(buf, "Instruction\n");
  597. case CACHE_TYPE_UNIFIED:
  598. return sprintf(buf, "Unified\n");
  599. default:
  600. return sprintf(buf, "Unknown\n");
  601. }
  602. }
  603. #define to_object(k) container_of(k, struct _index_kobject, kobj)
  604. #define to_attr(a) container_of(a, struct _cache_attr, attr)
  605. static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
  606. unsigned int index)
  607. {
  608. int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
  609. int node = cpu_to_node(cpu);
  610. struct pci_dev *dev = node_to_k8_nb_misc(node);
  611. unsigned int reg = 0;
  612. if (!this_leaf->can_disable)
  613. return -EINVAL;
  614. if (!dev)
  615. return -EINVAL;
  616. pci_read_config_dword(dev, 0x1BC + index * 4, &reg);
  617. return sprintf(buf, "%x\n", reg);
  618. }
  619. #define SHOW_CACHE_DISABLE(index) \
  620. static ssize_t \
  621. show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf) \
  622. { \
  623. return show_cache_disable(this_leaf, buf, index); \
  624. }
  625. SHOW_CACHE_DISABLE(0)
  626. SHOW_CACHE_DISABLE(1)
  627. static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
  628. const char *buf, size_t count, unsigned int index)
  629. {
  630. int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
  631. int node = cpu_to_node(cpu);
  632. struct pci_dev *dev = node_to_k8_nb_misc(node);
  633. unsigned long val = 0;
  634. if (!this_leaf->can_disable)
  635. return -EINVAL;
  636. if (!capable(CAP_SYS_ADMIN))
  637. return -EPERM;
  638. if (!dev)
  639. return -EINVAL;
  640. if (strict_strtoul(buf, 10, &val) < 0)
  641. return -EINVAL;
  642. val |= 0xc0000000;
  643. pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
  644. wbinvd();
  645. pci_write_config_dword(dev, 0x1BC + index * 4, val);
  646. return count;
  647. }
  648. #define STORE_CACHE_DISABLE(index) \
  649. static ssize_t \
  650. store_cache_disable_##index(struct _cpuid4_info *this_leaf, \
  651. const char *buf, size_t count) \
  652. { \
  653. return store_cache_disable(this_leaf, buf, count, index); \
  654. }
  655. STORE_CACHE_DISABLE(0)
  656. STORE_CACHE_DISABLE(1)
  657. struct _cache_attr {
  658. struct attribute attr;
  659. ssize_t (*show)(struct _cpuid4_info *, char *);
  660. ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
  661. };
  662. #define define_one_ro(_name) \
  663. static struct _cache_attr _name = \
  664. __ATTR(_name, 0444, show_##_name, NULL)
  665. define_one_ro(level);
  666. define_one_ro(type);
  667. define_one_ro(coherency_line_size);
  668. define_one_ro(physical_line_partition);
  669. define_one_ro(ways_of_associativity);
  670. define_one_ro(number_of_sets);
  671. define_one_ro(size);
  672. define_one_ro(shared_cpu_map);
  673. define_one_ro(shared_cpu_list);
  674. static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
  675. show_cache_disable_0, store_cache_disable_0);
  676. static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
  677. show_cache_disable_1, store_cache_disable_1);
  678. static struct attribute * default_attrs[] = {
  679. &type.attr,
  680. &level.attr,
  681. &coherency_line_size.attr,
  682. &physical_line_partition.attr,
  683. &ways_of_associativity.attr,
  684. &number_of_sets.attr,
  685. &size.attr,
  686. &shared_cpu_map.attr,
  687. &shared_cpu_list.attr,
  688. &cache_disable_0.attr,
  689. &cache_disable_1.attr,
  690. NULL
  691. };
  692. static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf)
  693. {
  694. struct _cache_attr *fattr = to_attr(attr);
  695. struct _index_kobject *this_leaf = to_object(kobj);
  696. ssize_t ret;
  697. ret = fattr->show ?
  698. fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
  699. buf) :
  700. 0;
  701. return ret;
  702. }
  703. static ssize_t store(struct kobject * kobj, struct attribute * attr,
  704. const char * buf, size_t count)
  705. {
  706. struct _cache_attr *fattr = to_attr(attr);
  707. struct _index_kobject *this_leaf = to_object(kobj);
  708. ssize_t ret;
  709. ret = fattr->store ?
  710. fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
  711. buf, count) :
  712. 0;
  713. return ret;
  714. }
  715. static struct sysfs_ops sysfs_ops = {
  716. .show = show,
  717. .store = store,
  718. };
  719. static struct kobj_type ktype_cache = {
  720. .sysfs_ops = &sysfs_ops,
  721. .default_attrs = default_attrs,
  722. };
  723. static struct kobj_type ktype_percpu_entry = {
  724. .sysfs_ops = &sysfs_ops,
  725. };
  726. static void __cpuinit cpuid4_cache_sysfs_exit(unsigned int cpu)
  727. {
  728. kfree(per_cpu(cache_kobject, cpu));
  729. kfree(per_cpu(index_kobject, cpu));
  730. per_cpu(cache_kobject, cpu) = NULL;
  731. per_cpu(index_kobject, cpu) = NULL;
  732. free_cache_attributes(cpu);
  733. }
  734. static int __cpuinit cpuid4_cache_sysfs_init(unsigned int cpu)
  735. {
  736. int err;
  737. if (num_cache_leaves == 0)
  738. return -ENOENT;
  739. err = detect_cache_attributes(cpu);
  740. if (err)
  741. return err;
  742. /* Allocate all required memory */
  743. per_cpu(cache_kobject, cpu) =
  744. kzalloc(sizeof(struct kobject), GFP_KERNEL);
  745. if (unlikely(per_cpu(cache_kobject, cpu) == NULL))
  746. goto err_out;
  747. per_cpu(index_kobject, cpu) = kzalloc(
  748. sizeof(struct _index_kobject ) * num_cache_leaves, GFP_KERNEL);
  749. if (unlikely(per_cpu(index_kobject, cpu) == NULL))
  750. goto err_out;
  751. return 0;
  752. err_out:
  753. cpuid4_cache_sysfs_exit(cpu);
  754. return -ENOMEM;
  755. }
  756. static DECLARE_BITMAP(cache_dev_map, NR_CPUS);
  757. /* Add/Remove cache interface for CPU device */
  758. static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
  759. {
  760. unsigned int cpu = sys_dev->id;
  761. unsigned long i, j;
  762. struct _index_kobject *this_object;
  763. int retval;
  764. retval = cpuid4_cache_sysfs_init(cpu);
  765. if (unlikely(retval < 0))
  766. return retval;
  767. retval = kobject_init_and_add(per_cpu(cache_kobject, cpu),
  768. &ktype_percpu_entry,
  769. &sys_dev->kobj, "%s", "cache");
  770. if (retval < 0) {
  771. cpuid4_cache_sysfs_exit(cpu);
  772. return retval;
  773. }
  774. for (i = 0; i < num_cache_leaves; i++) {
  775. this_object = INDEX_KOBJECT_PTR(cpu,i);
  776. this_object->cpu = cpu;
  777. this_object->index = i;
  778. retval = kobject_init_and_add(&(this_object->kobj),
  779. &ktype_cache,
  780. per_cpu(cache_kobject, cpu),
  781. "index%1lu", i);
  782. if (unlikely(retval)) {
  783. for (j = 0; j < i; j++) {
  784. kobject_put(&(INDEX_KOBJECT_PTR(cpu,j)->kobj));
  785. }
  786. kobject_put(per_cpu(cache_kobject, cpu));
  787. cpuid4_cache_sysfs_exit(cpu);
  788. return retval;
  789. }
  790. kobject_uevent(&(this_object->kobj), KOBJ_ADD);
  791. }
  792. cpumask_set_cpu(cpu, to_cpumask(cache_dev_map));
  793. kobject_uevent(per_cpu(cache_kobject, cpu), KOBJ_ADD);
  794. return 0;
  795. }
  796. static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
  797. {
  798. unsigned int cpu = sys_dev->id;
  799. unsigned long i;
  800. if (per_cpu(cpuid4_info, cpu) == NULL)
  801. return;
  802. if (!cpumask_test_cpu(cpu, to_cpumask(cache_dev_map)))
  803. return;
  804. cpumask_clear_cpu(cpu, to_cpumask(cache_dev_map));
  805. for (i = 0; i < num_cache_leaves; i++)
  806. kobject_put(&(INDEX_KOBJECT_PTR(cpu,i)->kobj));
  807. kobject_put(per_cpu(cache_kobject, cpu));
  808. cpuid4_cache_sysfs_exit(cpu);
  809. }
  810. static int __cpuinit cacheinfo_cpu_callback(struct notifier_block *nfb,
  811. unsigned long action, void *hcpu)
  812. {
  813. unsigned int cpu = (unsigned long)hcpu;
  814. struct sys_device *sys_dev;
  815. sys_dev = get_cpu_sysdev(cpu);
  816. switch (action) {
  817. case CPU_ONLINE:
  818. case CPU_ONLINE_FROZEN:
  819. cache_add_dev(sys_dev);
  820. break;
  821. case CPU_DEAD:
  822. case CPU_DEAD_FROZEN:
  823. cache_remove_dev(sys_dev);
  824. break;
  825. }
  826. return NOTIFY_OK;
  827. }
  828. static struct notifier_block __cpuinitdata cacheinfo_cpu_notifier =
  829. {
  830. .notifier_call = cacheinfo_cpu_callback,
  831. };
  832. static int __cpuinit cache_sysfs_init(void)
  833. {
  834. int i;
  835. if (num_cache_leaves == 0)
  836. return 0;
  837. for_each_online_cpu(i) {
  838. int err;
  839. struct sys_device *sys_dev = get_cpu_sysdev(i);
  840. err = cache_add_dev(sys_dev);
  841. if (err)
  842. return err;
  843. }
  844. register_hotcpu_notifier(&cacheinfo_cpu_notifier);
  845. return 0;
  846. }
  847. device_initcall(cache_sysfs_init);
  848. #endif