htc_drv_init.c 24 KB

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  1. /*
  2. * Copyright (c) 2010 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "htc.h"
  17. MODULE_AUTHOR("Atheros Communications");
  18. MODULE_LICENSE("Dual BSD/GPL");
  19. MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
  20. static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  21. module_param_named(debug, ath9k_debug, uint, 0);
  22. MODULE_PARM_DESC(debug, "Debugging mask");
  23. int htc_modparam_nohwcrypt;
  24. module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
  25. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  26. #define CHAN2G(_freq, _idx) { \
  27. .center_freq = (_freq), \
  28. .hw_value = (_idx), \
  29. .max_power = 20, \
  30. }
  31. #define CHAN5G(_freq, _idx) { \
  32. .band = IEEE80211_BAND_5GHZ, \
  33. .center_freq = (_freq), \
  34. .hw_value = (_idx), \
  35. .max_power = 20, \
  36. }
  37. #define ATH_HTC_BTCOEX_PRODUCT_ID "wb193"
  38. static struct ieee80211_channel ath9k_2ghz_channels[] = {
  39. CHAN2G(2412, 0), /* Channel 1 */
  40. CHAN2G(2417, 1), /* Channel 2 */
  41. CHAN2G(2422, 2), /* Channel 3 */
  42. CHAN2G(2427, 3), /* Channel 4 */
  43. CHAN2G(2432, 4), /* Channel 5 */
  44. CHAN2G(2437, 5), /* Channel 6 */
  45. CHAN2G(2442, 6), /* Channel 7 */
  46. CHAN2G(2447, 7), /* Channel 8 */
  47. CHAN2G(2452, 8), /* Channel 9 */
  48. CHAN2G(2457, 9), /* Channel 10 */
  49. CHAN2G(2462, 10), /* Channel 11 */
  50. CHAN2G(2467, 11), /* Channel 12 */
  51. CHAN2G(2472, 12), /* Channel 13 */
  52. CHAN2G(2484, 13), /* Channel 14 */
  53. };
  54. static struct ieee80211_channel ath9k_5ghz_channels[] = {
  55. /* _We_ call this UNII 1 */
  56. CHAN5G(5180, 14), /* Channel 36 */
  57. CHAN5G(5200, 15), /* Channel 40 */
  58. CHAN5G(5220, 16), /* Channel 44 */
  59. CHAN5G(5240, 17), /* Channel 48 */
  60. /* _We_ call this UNII 2 */
  61. CHAN5G(5260, 18), /* Channel 52 */
  62. CHAN5G(5280, 19), /* Channel 56 */
  63. CHAN5G(5300, 20), /* Channel 60 */
  64. CHAN5G(5320, 21), /* Channel 64 */
  65. /* _We_ call this "Middle band" */
  66. CHAN5G(5500, 22), /* Channel 100 */
  67. CHAN5G(5520, 23), /* Channel 104 */
  68. CHAN5G(5540, 24), /* Channel 108 */
  69. CHAN5G(5560, 25), /* Channel 112 */
  70. CHAN5G(5580, 26), /* Channel 116 */
  71. CHAN5G(5600, 27), /* Channel 120 */
  72. CHAN5G(5620, 28), /* Channel 124 */
  73. CHAN5G(5640, 29), /* Channel 128 */
  74. CHAN5G(5660, 30), /* Channel 132 */
  75. CHAN5G(5680, 31), /* Channel 136 */
  76. CHAN5G(5700, 32), /* Channel 140 */
  77. /* _We_ call this UNII 3 */
  78. CHAN5G(5745, 33), /* Channel 149 */
  79. CHAN5G(5765, 34), /* Channel 153 */
  80. CHAN5G(5785, 35), /* Channel 157 */
  81. CHAN5G(5805, 36), /* Channel 161 */
  82. CHAN5G(5825, 37), /* Channel 165 */
  83. };
  84. /* Atheros hardware rate code addition for short premble */
  85. #define SHPCHECK(__hw_rate, __flags) \
  86. ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
  87. #define RATE(_bitrate, _hw_rate, _flags) { \
  88. .bitrate = (_bitrate), \
  89. .flags = (_flags), \
  90. .hw_value = (_hw_rate), \
  91. .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
  92. }
  93. static struct ieee80211_rate ath9k_legacy_rates[] = {
  94. RATE(10, 0x1b, 0),
  95. RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
  96. RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
  97. RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
  98. RATE(60, 0x0b, 0),
  99. RATE(90, 0x0f, 0),
  100. RATE(120, 0x0a, 0),
  101. RATE(180, 0x0e, 0),
  102. RATE(240, 0x09, 0),
  103. RATE(360, 0x0d, 0),
  104. RATE(480, 0x08, 0),
  105. RATE(540, 0x0c, 0),
  106. };
  107. static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
  108. {
  109. int time_left;
  110. if (atomic_read(&priv->htc->tgt_ready) > 0) {
  111. atomic_dec(&priv->htc->tgt_ready);
  112. return 0;
  113. }
  114. /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
  115. time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
  116. if (!time_left) {
  117. dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
  118. return -ETIMEDOUT;
  119. }
  120. atomic_dec(&priv->htc->tgt_ready);
  121. return 0;
  122. }
  123. static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
  124. {
  125. ath9k_htc_exit_debug(priv->ah);
  126. ath9k_hw_deinit(priv->ah);
  127. tasklet_kill(&priv->wmi_tasklet);
  128. tasklet_kill(&priv->rx_tasklet);
  129. tasklet_kill(&priv->tx_tasklet);
  130. kfree(priv->ah);
  131. priv->ah = NULL;
  132. }
  133. static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
  134. {
  135. struct ieee80211_hw *hw = priv->hw;
  136. wiphy_rfkill_stop_polling(hw->wiphy);
  137. ath9k_deinit_leds(priv);
  138. ieee80211_unregister_hw(hw);
  139. ath9k_rx_cleanup(priv);
  140. ath9k_tx_cleanup(priv);
  141. ath9k_deinit_priv(priv);
  142. }
  143. static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
  144. u16 service_id,
  145. void (*tx) (void *,
  146. struct sk_buff *,
  147. enum htc_endpoint_id,
  148. bool txok),
  149. enum htc_endpoint_id *ep_id)
  150. {
  151. struct htc_service_connreq req;
  152. memset(&req, 0, sizeof(struct htc_service_connreq));
  153. req.service_id = service_id;
  154. req.ep_callbacks.priv = priv;
  155. req.ep_callbacks.rx = ath9k_htc_rxep;
  156. req.ep_callbacks.tx = tx;
  157. return htc_connect_service(priv->htc, &req, ep_id);
  158. }
  159. static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid)
  160. {
  161. int ret;
  162. /* WMI CMD*/
  163. ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
  164. if (ret)
  165. goto err;
  166. /* Beacon */
  167. ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
  168. &priv->beacon_ep);
  169. if (ret)
  170. goto err;
  171. /* CAB */
  172. ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
  173. &priv->cab_ep);
  174. if (ret)
  175. goto err;
  176. /* UAPSD */
  177. ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
  178. &priv->uapsd_ep);
  179. if (ret)
  180. goto err;
  181. /* MGMT */
  182. ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
  183. &priv->mgmt_ep);
  184. if (ret)
  185. goto err;
  186. /* DATA BE */
  187. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
  188. &priv->data_be_ep);
  189. if (ret)
  190. goto err;
  191. /* DATA BK */
  192. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
  193. &priv->data_bk_ep);
  194. if (ret)
  195. goto err;
  196. /* DATA VI */
  197. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
  198. &priv->data_vi_ep);
  199. if (ret)
  200. goto err;
  201. /* DATA VO */
  202. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
  203. &priv->data_vo_ep);
  204. if (ret)
  205. goto err;
  206. /*
  207. * Setup required credits before initializing HTC.
  208. * This is a bit hacky, but, since queuing is done in
  209. * the HIF layer, shouldn't matter much.
  210. */
  211. switch(devid) {
  212. case 0x7010:
  213. case 0x7015:
  214. case 0x9018:
  215. priv->htc->credits = 45;
  216. break;
  217. default:
  218. priv->htc->credits = 33;
  219. }
  220. ret = htc_init(priv->htc);
  221. if (ret)
  222. goto err;
  223. dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
  224. priv->htc->credits);
  225. return 0;
  226. err:
  227. dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
  228. return ret;
  229. }
  230. static int ath9k_reg_notifier(struct wiphy *wiphy,
  231. struct regulatory_request *request)
  232. {
  233. struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
  234. struct ath9k_htc_priv *priv = hw->priv;
  235. return ath_reg_notifier_apply(wiphy, request,
  236. ath9k_hw_regulatory(priv->ah));
  237. }
  238. static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
  239. {
  240. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  241. struct ath_common *common = ath9k_hw_common(ah);
  242. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  243. __be32 val, reg = cpu_to_be32(reg_offset);
  244. int r;
  245. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
  246. (u8 *) &reg, sizeof(reg),
  247. (u8 *) &val, sizeof(val),
  248. 100);
  249. if (unlikely(r)) {
  250. ath_print(common, ATH_DBG_WMI,
  251. "REGISTER READ FAILED: (0x%04x, %d)\n",
  252. reg_offset, r);
  253. return -EIO;
  254. }
  255. return be32_to_cpu(val);
  256. }
  257. static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
  258. {
  259. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  260. struct ath_common *common = ath9k_hw_common(ah);
  261. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  262. const __be32 buf[2] = {
  263. cpu_to_be32(reg_offset),
  264. cpu_to_be32(val),
  265. };
  266. int r;
  267. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  268. (u8 *) &buf, sizeof(buf),
  269. (u8 *) &val, sizeof(val),
  270. 100);
  271. if (unlikely(r)) {
  272. ath_print(common, ATH_DBG_WMI,
  273. "REGISTER WRITE FAILED:(0x%04x, %d)\n",
  274. reg_offset, r);
  275. }
  276. }
  277. static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
  278. {
  279. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  280. struct ath_common *common = ath9k_hw_common(ah);
  281. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  282. u32 rsp_status;
  283. int r;
  284. mutex_lock(&priv->wmi->multi_write_mutex);
  285. /* Store the register/value */
  286. priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
  287. cpu_to_be32(reg_offset);
  288. priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
  289. cpu_to_be32(val);
  290. priv->wmi->multi_write_idx++;
  291. /* If the buffer is full, send it out. */
  292. if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
  293. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  294. (u8 *) &priv->wmi->multi_write,
  295. sizeof(struct register_write) * priv->wmi->multi_write_idx,
  296. (u8 *) &rsp_status, sizeof(rsp_status),
  297. 100);
  298. if (unlikely(r)) {
  299. ath_print(common, ATH_DBG_WMI,
  300. "REGISTER WRITE FAILED, multi len: %d\n",
  301. priv->wmi->multi_write_idx);
  302. }
  303. priv->wmi->multi_write_idx = 0;
  304. }
  305. mutex_unlock(&priv->wmi->multi_write_mutex);
  306. }
  307. static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
  308. {
  309. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  310. struct ath_common *common = ath9k_hw_common(ah);
  311. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  312. if (atomic_read(&priv->wmi->mwrite_cnt))
  313. ath9k_regwrite_buffer(hw_priv, val, reg_offset);
  314. else
  315. ath9k_regwrite_single(hw_priv, val, reg_offset);
  316. }
  317. static void ath9k_enable_regwrite_buffer(void *hw_priv)
  318. {
  319. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  320. struct ath_common *common = ath9k_hw_common(ah);
  321. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  322. atomic_inc(&priv->wmi->mwrite_cnt);
  323. }
  324. static void ath9k_regwrite_flush(void *hw_priv)
  325. {
  326. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  327. struct ath_common *common = ath9k_hw_common(ah);
  328. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  329. u32 rsp_status;
  330. int r;
  331. atomic_dec(&priv->wmi->mwrite_cnt);
  332. mutex_lock(&priv->wmi->multi_write_mutex);
  333. if (priv->wmi->multi_write_idx) {
  334. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  335. (u8 *) &priv->wmi->multi_write,
  336. sizeof(struct register_write) * priv->wmi->multi_write_idx,
  337. (u8 *) &rsp_status, sizeof(rsp_status),
  338. 100);
  339. if (unlikely(r)) {
  340. ath_print(common, ATH_DBG_WMI,
  341. "REGISTER WRITE FAILED, multi len: %d\n",
  342. priv->wmi->multi_write_idx);
  343. }
  344. priv->wmi->multi_write_idx = 0;
  345. }
  346. mutex_unlock(&priv->wmi->multi_write_mutex);
  347. }
  348. static const struct ath_ops ath9k_common_ops = {
  349. .read = ath9k_regread,
  350. .write = ath9k_regwrite,
  351. .enable_write_buffer = ath9k_enable_regwrite_buffer,
  352. .write_flush = ath9k_regwrite_flush,
  353. };
  354. static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
  355. {
  356. *csz = L1_CACHE_BYTES >> 2;
  357. }
  358. static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
  359. {
  360. struct ath_hw *ah = (struct ath_hw *) common->ah;
  361. (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
  362. if (!ath9k_hw_wait(ah,
  363. AR_EEPROM_STATUS_DATA,
  364. AR_EEPROM_STATUS_DATA_BUSY |
  365. AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
  366. AH_WAIT_TIMEOUT))
  367. return false;
  368. *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
  369. AR_EEPROM_STATUS_DATA_VAL);
  370. return true;
  371. }
  372. static const struct ath_bus_ops ath9k_usb_bus_ops = {
  373. .ath_bus_type = ATH_USB,
  374. .read_cachesize = ath_usb_read_cachesize,
  375. .eeprom_read = ath_usb_eeprom_read,
  376. };
  377. static void setup_ht_cap(struct ath9k_htc_priv *priv,
  378. struct ieee80211_sta_ht_cap *ht_info)
  379. {
  380. struct ath_common *common = ath9k_hw_common(priv->ah);
  381. u8 tx_streams, rx_streams;
  382. int i;
  383. ht_info->ht_supported = true;
  384. ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  385. IEEE80211_HT_CAP_SM_PS |
  386. IEEE80211_HT_CAP_SGI_40 |
  387. IEEE80211_HT_CAP_DSSSCCK40;
  388. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
  389. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  390. ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
  391. ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  392. ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
  393. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  394. /* ath9k_htc supports only 1 or 2 stream devices */
  395. tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2);
  396. rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2);
  397. ath_print(common, ATH_DBG_CONFIG,
  398. "TX streams %d, RX streams: %d\n",
  399. tx_streams, rx_streams);
  400. if (tx_streams != rx_streams) {
  401. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  402. ht_info->mcs.tx_params |= ((tx_streams - 1) <<
  403. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  404. }
  405. for (i = 0; i < rx_streams; i++)
  406. ht_info->mcs.rx_mask[i] = 0xff;
  407. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
  408. }
  409. static int ath9k_init_queues(struct ath9k_htc_priv *priv)
  410. {
  411. struct ath_common *common = ath9k_hw_common(priv->ah);
  412. int i;
  413. for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
  414. priv->hwq_map[i] = -1;
  415. priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
  416. if (priv->beaconq == -1) {
  417. ath_print(common, ATH_DBG_FATAL,
  418. "Unable to setup BEACON xmit queue\n");
  419. goto err;
  420. }
  421. priv->cabq = ath9k_htc_cabq_setup(priv);
  422. if (priv->cabq == -1) {
  423. ath_print(common, ATH_DBG_FATAL,
  424. "Unable to setup CAB xmit queue\n");
  425. goto err;
  426. }
  427. if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
  428. ath_print(common, ATH_DBG_FATAL,
  429. "Unable to setup xmit queue for BE traffic\n");
  430. goto err;
  431. }
  432. if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
  433. ath_print(common, ATH_DBG_FATAL,
  434. "Unable to setup xmit queue for BK traffic\n");
  435. goto err;
  436. }
  437. if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
  438. ath_print(common, ATH_DBG_FATAL,
  439. "Unable to setup xmit queue for VI traffic\n");
  440. goto err;
  441. }
  442. if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
  443. ath_print(common, ATH_DBG_FATAL,
  444. "Unable to setup xmit queue for VO traffic\n");
  445. goto err;
  446. }
  447. return 0;
  448. err:
  449. return -EINVAL;
  450. }
  451. static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
  452. {
  453. struct ath_common *common = ath9k_hw_common(priv->ah);
  454. int i = 0;
  455. /* Get the hardware key cache size. */
  456. common->keymax = priv->ah->caps.keycache_size;
  457. if (common->keymax > ATH_KEYMAX) {
  458. ath_print(common, ATH_DBG_ANY,
  459. "Warning, using only %u entries in %u key cache\n",
  460. ATH_KEYMAX, common->keymax);
  461. common->keymax = ATH_KEYMAX;
  462. }
  463. if (priv->ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
  464. common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
  465. /*
  466. * Reset the key cache since some parts do not
  467. * reset the contents on initial power up.
  468. */
  469. for (i = 0; i < common->keymax; i++)
  470. ath_hw_keyreset(common, (u16) i);
  471. }
  472. static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
  473. {
  474. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
  475. priv->sbands[IEEE80211_BAND_2GHZ].channels =
  476. ath9k_2ghz_channels;
  477. priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
  478. priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
  479. ARRAY_SIZE(ath9k_2ghz_channels);
  480. priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
  481. priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
  482. ARRAY_SIZE(ath9k_legacy_rates);
  483. }
  484. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
  485. priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
  486. priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
  487. priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
  488. ARRAY_SIZE(ath9k_5ghz_channels);
  489. priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
  490. ath9k_legacy_rates + 4;
  491. priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
  492. ARRAY_SIZE(ath9k_legacy_rates) - 4;
  493. }
  494. }
  495. static void ath9k_init_misc(struct ath9k_htc_priv *priv)
  496. {
  497. struct ath_common *common = ath9k_hw_common(priv->ah);
  498. common->tx_chainmask = priv->ah->caps.tx_chainmask;
  499. common->rx_chainmask = priv->ah->caps.rx_chainmask;
  500. memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
  501. priv->ah->opmode = NL80211_IFTYPE_STATION;
  502. }
  503. static void ath9k_init_btcoex(struct ath9k_htc_priv *priv)
  504. {
  505. int qnum;
  506. switch (priv->ah->btcoex_hw.scheme) {
  507. case ATH_BTCOEX_CFG_NONE:
  508. break;
  509. case ATH_BTCOEX_CFG_3WIRE:
  510. priv->ah->btcoex_hw.btactive_gpio = 7;
  511. priv->ah->btcoex_hw.btpriority_gpio = 6;
  512. priv->ah->btcoex_hw.wlanactive_gpio = 8;
  513. priv->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
  514. ath9k_hw_btcoex_init_3wire(priv->ah);
  515. ath_htc_init_btcoex_work(priv);
  516. qnum = priv->hwq_map[WME_AC_BE];
  517. ath9k_hw_init_btcoex_hw(priv->ah, qnum);
  518. break;
  519. default:
  520. WARN_ON(1);
  521. break;
  522. }
  523. }
  524. static int ath9k_init_priv(struct ath9k_htc_priv *priv,
  525. u16 devid, char *product)
  526. {
  527. struct ath_hw *ah = NULL;
  528. struct ath_common *common;
  529. int ret = 0, csz = 0;
  530. priv->op_flags |= OP_INVALID;
  531. ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
  532. if (!ah)
  533. return -ENOMEM;
  534. ah->hw_version.devid = devid;
  535. ah->hw_version.subsysid = 0; /* FIXME */
  536. ah->ah_flags |= AH_USE_EEPROM;
  537. priv->ah = ah;
  538. common = ath9k_hw_common(ah);
  539. common->ops = &ath9k_common_ops;
  540. common->bus_ops = &ath9k_usb_bus_ops;
  541. common->ah = ah;
  542. common->hw = priv->hw;
  543. common->priv = priv;
  544. common->debug_mask = ath9k_debug;
  545. spin_lock_init(&priv->wmi->wmi_lock);
  546. spin_lock_init(&priv->beacon_lock);
  547. spin_lock_init(&priv->tx_lock);
  548. mutex_init(&priv->mutex);
  549. mutex_init(&priv->htc_pm_lock);
  550. tasklet_init(&priv->wmi_tasklet, ath9k_wmi_tasklet,
  551. (unsigned long)priv);
  552. tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
  553. (unsigned long)priv);
  554. tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, (unsigned long)priv);
  555. INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work);
  556. INIT_WORK(&priv->ps_work, ath9k_ps_work);
  557. /*
  558. * Cache line size is used to size and align various
  559. * structures used to communicate with the hardware.
  560. */
  561. ath_read_cachesize(common, &csz);
  562. common->cachelsz = csz << 2; /* convert to bytes */
  563. ret = ath9k_hw_init(ah);
  564. if (ret) {
  565. ath_print(common, ATH_DBG_FATAL,
  566. "Unable to initialize hardware; "
  567. "initialization status: %d\n", ret);
  568. goto err_hw;
  569. }
  570. ret = ath9k_htc_init_debug(ah);
  571. if (ret) {
  572. ath_print(common, ATH_DBG_FATAL,
  573. "Unable to create debugfs files\n");
  574. goto err_debug;
  575. }
  576. ret = ath9k_init_queues(priv);
  577. if (ret)
  578. goto err_queues;
  579. ath9k_init_crypto(priv);
  580. ath9k_init_channels_rates(priv);
  581. ath9k_init_misc(priv);
  582. if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) {
  583. ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE;
  584. ath9k_init_btcoex(priv);
  585. }
  586. return 0;
  587. err_queues:
  588. ath9k_htc_exit_debug(ah);
  589. err_debug:
  590. ath9k_hw_deinit(ah);
  591. err_hw:
  592. kfree(ah);
  593. priv->ah = NULL;
  594. return ret;
  595. }
  596. static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
  597. struct ieee80211_hw *hw)
  598. {
  599. struct ath_common *common = ath9k_hw_common(priv->ah);
  600. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  601. IEEE80211_HW_AMPDU_AGGREGATION |
  602. IEEE80211_HW_SPECTRUM_MGMT |
  603. IEEE80211_HW_HAS_RATE_CONTROL |
  604. IEEE80211_HW_RX_INCLUDES_FCS |
  605. IEEE80211_HW_SUPPORTS_PS |
  606. IEEE80211_HW_PS_NULLFUNC_STACK;
  607. hw->wiphy->interface_modes =
  608. BIT(NL80211_IFTYPE_STATION) |
  609. BIT(NL80211_IFTYPE_ADHOC);
  610. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  611. hw->queues = 4;
  612. hw->channel_change_time = 5000;
  613. hw->max_listen_interval = 10;
  614. hw->vif_data_size = sizeof(struct ath9k_htc_vif);
  615. hw->sta_data_size = sizeof(struct ath9k_htc_sta);
  616. /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
  617. hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
  618. sizeof(struct htc_frame_hdr) + 4;
  619. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
  620. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  621. &priv->sbands[IEEE80211_BAND_2GHZ];
  622. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
  623. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  624. &priv->sbands[IEEE80211_BAND_5GHZ];
  625. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  626. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
  627. setup_ht_cap(priv,
  628. &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
  629. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
  630. setup_ht_cap(priv,
  631. &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
  632. }
  633. SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
  634. }
  635. static int ath9k_init_device(struct ath9k_htc_priv *priv,
  636. u16 devid, char *product)
  637. {
  638. struct ieee80211_hw *hw = priv->hw;
  639. struct ath_common *common;
  640. struct ath_hw *ah;
  641. int error = 0;
  642. struct ath_regulatory *reg;
  643. /* Bring up device */
  644. error = ath9k_init_priv(priv, devid, product);
  645. if (error != 0)
  646. goto err_init;
  647. ah = priv->ah;
  648. common = ath9k_hw_common(ah);
  649. ath9k_set_hw_capab(priv, hw);
  650. /* Initialize regulatory */
  651. error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
  652. ath9k_reg_notifier);
  653. if (error)
  654. goto err_regd;
  655. reg = &common->regulatory;
  656. /* Setup TX */
  657. error = ath9k_tx_init(priv);
  658. if (error != 0)
  659. goto err_tx;
  660. /* Setup RX */
  661. error = ath9k_rx_init(priv);
  662. if (error != 0)
  663. goto err_rx;
  664. /* Register with mac80211 */
  665. error = ieee80211_register_hw(hw);
  666. if (error)
  667. goto err_register;
  668. /* Handle world regulatory */
  669. if (!ath_is_world_regd(reg)) {
  670. error = regulatory_hint(hw->wiphy, reg->alpha2);
  671. if (error)
  672. goto err_world;
  673. }
  674. ath9k_init_leds(priv);
  675. ath9k_start_rfkill_poll(priv);
  676. return 0;
  677. err_world:
  678. ieee80211_unregister_hw(hw);
  679. err_register:
  680. ath9k_rx_cleanup(priv);
  681. err_rx:
  682. ath9k_tx_cleanup(priv);
  683. err_tx:
  684. /* Nothing */
  685. err_regd:
  686. ath9k_deinit_priv(priv);
  687. err_init:
  688. return error;
  689. }
  690. int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
  691. u16 devid, char *product)
  692. {
  693. struct ieee80211_hw *hw;
  694. struct ath9k_htc_priv *priv;
  695. int ret;
  696. hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
  697. if (!hw)
  698. return -ENOMEM;
  699. priv = hw->priv;
  700. priv->hw = hw;
  701. priv->htc = htc_handle;
  702. priv->dev = dev;
  703. htc_handle->drv_priv = priv;
  704. SET_IEEE80211_DEV(hw, priv->dev);
  705. ret = ath9k_htc_wait_for_target(priv);
  706. if (ret)
  707. goto err_free;
  708. priv->wmi = ath9k_init_wmi(priv);
  709. if (!priv->wmi) {
  710. ret = -EINVAL;
  711. goto err_free;
  712. }
  713. ret = ath9k_init_htc_services(priv, devid);
  714. if (ret)
  715. goto err_init;
  716. /* The device may have been unplugged earlier. */
  717. priv->op_flags &= ~OP_UNPLUGGED;
  718. ret = ath9k_init_device(priv, devid, product);
  719. if (ret)
  720. goto err_init;
  721. return 0;
  722. err_init:
  723. ath9k_deinit_wmi(priv);
  724. err_free:
  725. ieee80211_free_hw(hw);
  726. return ret;
  727. }
  728. void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
  729. {
  730. if (htc_handle->drv_priv) {
  731. /* Check if the device has been yanked out. */
  732. if (hotunplug)
  733. htc_handle->drv_priv->op_flags |= OP_UNPLUGGED;
  734. ath9k_deinit_device(htc_handle->drv_priv);
  735. ath9k_deinit_wmi(htc_handle->drv_priv);
  736. ieee80211_free_hw(htc_handle->drv_priv->hw);
  737. }
  738. }
  739. #ifdef CONFIG_PM
  740. int ath9k_htc_resume(struct htc_target *htc_handle)
  741. {
  742. int ret;
  743. ret = ath9k_htc_wait_for_target(htc_handle->drv_priv);
  744. if (ret)
  745. return ret;
  746. ret = ath9k_init_htc_services(htc_handle->drv_priv,
  747. htc_handle->drv_priv->ah->hw_version.devid);
  748. return ret;
  749. }
  750. #endif
  751. static int __init ath9k_htc_init(void)
  752. {
  753. int error;
  754. error = ath9k_htc_debug_create_root();
  755. if (error < 0) {
  756. printk(KERN_ERR
  757. "ath9k_htc: Unable to create debugfs root: %d\n",
  758. error);
  759. goto err_dbg;
  760. }
  761. error = ath9k_hif_usb_init();
  762. if (error < 0) {
  763. printk(KERN_ERR
  764. "ath9k_htc: No USB devices found,"
  765. " driver not installed.\n");
  766. error = -ENODEV;
  767. goto err_usb;
  768. }
  769. return 0;
  770. err_usb:
  771. ath9k_htc_debug_remove_root();
  772. err_dbg:
  773. return error;
  774. }
  775. module_init(ath9k_htc_init);
  776. static void __exit ath9k_htc_exit(void)
  777. {
  778. ath9k_hif_usb_exit();
  779. ath9k_htc_debug_remove_root();
  780. printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
  781. }
  782. module_exit(ath9k_htc_exit);