at91sam9260.dtsi 17 KB

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  1. /*
  2. * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
  3. *
  4. * Copyright (C) 2011 Atmel,
  5. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
  6. * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  7. *
  8. * Licensed under GPLv2 or later.
  9. */
  10. #include "skeleton.dtsi"
  11. #include <dt-bindings/pinctrl/at91.h>
  12. #include <dt-bindings/interrupt-controller/irq.h>
  13. #include <dt-bindings/gpio/gpio.h>
  14. / {
  15. model = "Atmel AT91SAM9260 family SoC";
  16. compatible = "atmel,at91sam9260";
  17. interrupt-parent = <&aic>;
  18. aliases {
  19. serial0 = &dbgu;
  20. serial1 = &usart0;
  21. serial2 = &usart1;
  22. serial3 = &usart2;
  23. serial4 = &usart3;
  24. serial5 = &uart0;
  25. serial6 = &uart1;
  26. gpio0 = &pioA;
  27. gpio1 = &pioB;
  28. gpio2 = &pioC;
  29. tcb0 = &tcb0;
  30. tcb1 = &tcb1;
  31. i2c0 = &i2c0;
  32. ssc0 = &ssc0;
  33. };
  34. cpus {
  35. cpu@0 {
  36. compatible = "arm,arm926ejs";
  37. };
  38. };
  39. memory {
  40. reg = <0x20000000 0x04000000>;
  41. };
  42. ahb {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. apb {
  48. compatible = "simple-bus";
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. ranges;
  52. aic: interrupt-controller@fffff000 {
  53. #interrupt-cells = <3>;
  54. compatible = "atmel,at91rm9200-aic";
  55. interrupt-controller;
  56. reg = <0xfffff000 0x200>;
  57. atmel,external-irqs = <29 30 31>;
  58. };
  59. ramc0: ramc@ffffea00 {
  60. compatible = "atmel,at91sam9260-sdramc";
  61. reg = <0xffffea00 0x200>;
  62. };
  63. pmc: pmc@fffffc00 {
  64. compatible = "atmel,at91rm9200-pmc";
  65. reg = <0xfffffc00 0x100>;
  66. };
  67. rstc@fffffd00 {
  68. compatible = "atmel,at91sam9260-rstc";
  69. reg = <0xfffffd00 0x10>;
  70. };
  71. shdwc@fffffd10 {
  72. compatible = "atmel,at91sam9260-shdwc";
  73. reg = <0xfffffd10 0x10>;
  74. };
  75. pit: timer@fffffd30 {
  76. compatible = "atmel,at91sam9260-pit";
  77. reg = <0xfffffd30 0xf>;
  78. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  79. };
  80. tcb0: timer@fffa0000 {
  81. compatible = "atmel,at91rm9200-tcb";
  82. reg = <0xfffa0000 0x100>;
  83. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
  84. 18 IRQ_TYPE_LEVEL_HIGH 0
  85. 19 IRQ_TYPE_LEVEL_HIGH 0>;
  86. };
  87. tcb1: timer@fffdc000 {
  88. compatible = "atmel,at91rm9200-tcb";
  89. reg = <0xfffdc000 0x100>;
  90. interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
  91. 27 IRQ_TYPE_LEVEL_HIGH 0
  92. 28 IRQ_TYPE_LEVEL_HIGH 0>;
  93. };
  94. pinctrl@fffff400 {
  95. #address-cells = <1>;
  96. #size-cells = <1>;
  97. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  98. ranges = <0xfffff400 0xfffff400 0x600>;
  99. atmel,mux-mask = <
  100. /* A B */
  101. 0xffffffff 0xffc00c3b /* pioA */
  102. 0xffffffff 0x7fff3ccf /* pioB */
  103. 0xffffffff 0x007fffff /* pioC */
  104. >;
  105. /* shared pinctrl settings */
  106. dbgu {
  107. pinctrl_dbgu: dbgu-0 {
  108. atmel,pins =
  109. <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
  110. AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */
  111. };
  112. };
  113. usart0 {
  114. pinctrl_usart0: usart0-0 {
  115. atmel,pins =
  116. <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
  117. AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
  118. };
  119. pinctrl_usart0_rts: usart0_rts-0 {
  120. atmel,pins =
  121. <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
  122. };
  123. pinctrl_usart0_cts: usart0_cts-0 {
  124. atmel,pins =
  125. <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */
  126. };
  127. pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
  128. atmel,pins =
  129. <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A */
  130. AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */
  131. };
  132. pinctrl_usart0_dcd: usart0_dcd-0 {
  133. atmel,pins =
  134. <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
  135. };
  136. pinctrl_usart0_ri: usart0_ri-0 {
  137. atmel,pins =
  138. <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
  139. };
  140. };
  141. usart1 {
  142. pinctrl_usart1: usart1-0 {
  143. atmel,pins =
  144. <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
  145. AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
  146. };
  147. pinctrl_usart1_rts: usart1_rts-0 {
  148. atmel,pins =
  149. <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */
  150. };
  151. pinctrl_usart1_cts: usart1_cts-0 {
  152. atmel,pins =
  153. <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */
  154. };
  155. };
  156. usart2 {
  157. pinctrl_usart2: usart2-0 {
  158. atmel,pins =
  159. <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */
  160. AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB9 periph A */
  161. };
  162. pinctrl_usart2_rts: usart2_rts-0 {
  163. atmel,pins =
  164. <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */
  165. };
  166. pinctrl_usart2_cts: usart2_cts-0 {
  167. atmel,pins =
  168. <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
  169. };
  170. };
  171. usart3 {
  172. pinctrl_usart3: usart3-0 {
  173. atmel,pins =
  174. <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB10 periph A with pullup */
  175. AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
  176. };
  177. pinctrl_usart3_rts: usart3_rts-0 {
  178. atmel,pins =
  179. <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */
  180. };
  181. pinctrl_usart3_cts: usart3_cts-0 {
  182. atmel,pins =
  183. <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */
  184. };
  185. };
  186. uart0 {
  187. pinctrl_uart0: uart0-0 {
  188. atmel,pins =
  189. <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA31 periph B with pullup */
  190. AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
  191. };
  192. };
  193. uart1 {
  194. pinctrl_uart1: uart1-0 {
  195. atmel,pins =
  196. <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB12 periph A with pullup */
  197. AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
  198. };
  199. };
  200. nand {
  201. pinctrl_nand: nand-0 {
  202. atmel,pins =
  203. <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC13 gpio RDY pin pull_up */
  204. AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
  205. };
  206. };
  207. macb {
  208. pinctrl_macb_rmii: macb_rmii-0 {
  209. atmel,pins =
  210. <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
  211. AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
  212. AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
  213. AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
  214. AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
  215. AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
  216. AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
  217. AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA19 periph A */
  218. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA20 periph A */
  219. AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
  220. };
  221. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  222. atmel,pins =
  223. <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */
  224. AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA23 periph B */
  225. AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
  226. AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
  227. AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */
  228. AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
  229. AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
  230. AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
  231. };
  232. pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
  233. atmel,pins =
  234. <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */
  235. AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */
  236. AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
  237. AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
  238. AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */
  239. AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
  240. AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
  241. AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
  242. };
  243. };
  244. mmc0 {
  245. pinctrl_mmc0_clk: mmc0_clk-0 {
  246. atmel,pins =
  247. <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
  248. };
  249. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  250. atmel,pins =
  251. <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
  252. AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA6 periph A with pullup */
  253. };
  254. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  255. atmel,pins =
  256. <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
  257. AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */
  258. AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */
  259. };
  260. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  261. atmel,pins =
  262. <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */
  263. AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */
  264. };
  265. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  266. atmel,pins =
  267. <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
  268. AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */
  269. AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA3 periph B with pullup */
  270. };
  271. };
  272. ssc0 {
  273. pinctrl_ssc0_tx: ssc0_tx-0 {
  274. atmel,pins =
  275. <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
  276. AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A */
  277. AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
  278. };
  279. pinctrl_ssc0_rx: ssc0_rx-0 {
  280. atmel,pins =
  281. <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */
  282. AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB20 periph A */
  283. AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
  284. };
  285. };
  286. spi0 {
  287. pinctrl_spi0: spi0-0 {
  288. atmel,pins =
  289. <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
  290. AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */
  291. AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */
  292. };
  293. };
  294. spi1 {
  295. pinctrl_spi1: spi1-0 {
  296. atmel,pins =
  297. <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */
  298. AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI1_MOSI pin */
  299. AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI1_SPCK pin */
  300. };
  301. };
  302. i2c_gpio0 {
  303. pinctrl_i2c_gpio0: i2c_gpio0-0 {
  304. atmel,pins =
  305. <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE
  306. AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
  307. };
  308. };
  309. pioA: gpio@fffff400 {
  310. compatible = "atmel,at91rm9200-gpio";
  311. reg = <0xfffff400 0x200>;
  312. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  313. #gpio-cells = <2>;
  314. gpio-controller;
  315. interrupt-controller;
  316. #interrupt-cells = <2>;
  317. };
  318. pioB: gpio@fffff600 {
  319. compatible = "atmel,at91rm9200-gpio";
  320. reg = <0xfffff600 0x200>;
  321. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  322. #gpio-cells = <2>;
  323. gpio-controller;
  324. interrupt-controller;
  325. #interrupt-cells = <2>;
  326. };
  327. pioC: gpio@fffff800 {
  328. compatible = "atmel,at91rm9200-gpio";
  329. reg = <0xfffff800 0x200>;
  330. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  331. #gpio-cells = <2>;
  332. gpio-controller;
  333. interrupt-controller;
  334. #interrupt-cells = <2>;
  335. };
  336. };
  337. dbgu: serial@fffff200 {
  338. compatible = "atmel,at91sam9260-usart";
  339. reg = <0xfffff200 0x200>;
  340. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  341. pinctrl-names = "default";
  342. pinctrl-0 = <&pinctrl_dbgu>;
  343. status = "disabled";
  344. };
  345. usart0: serial@fffb0000 {
  346. compatible = "atmel,at91sam9260-usart";
  347. reg = <0xfffb0000 0x200>;
  348. interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
  349. atmel,use-dma-rx;
  350. atmel,use-dma-tx;
  351. pinctrl-names = "default";
  352. pinctrl-0 = <&pinctrl_usart0>;
  353. status = "disabled";
  354. };
  355. usart1: serial@fffb4000 {
  356. compatible = "atmel,at91sam9260-usart";
  357. reg = <0xfffb4000 0x200>;
  358. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  359. atmel,use-dma-rx;
  360. atmel,use-dma-tx;
  361. pinctrl-names = "default";
  362. pinctrl-0 = <&pinctrl_usart1>;
  363. status = "disabled";
  364. };
  365. usart2: serial@fffb8000 {
  366. compatible = "atmel,at91sam9260-usart";
  367. reg = <0xfffb8000 0x200>;
  368. interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
  369. atmel,use-dma-rx;
  370. atmel,use-dma-tx;
  371. pinctrl-names = "default";
  372. pinctrl-0 = <&pinctrl_usart2>;
  373. status = "disabled";
  374. };
  375. usart3: serial@fffd0000 {
  376. compatible = "atmel,at91sam9260-usart";
  377. reg = <0xfffd0000 0x200>;
  378. interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
  379. atmel,use-dma-rx;
  380. atmel,use-dma-tx;
  381. pinctrl-names = "default";
  382. pinctrl-0 = <&pinctrl_usart3>;
  383. status = "disabled";
  384. };
  385. uart0: serial@fffd4000 {
  386. compatible = "atmel,at91sam9260-usart";
  387. reg = <0xfffd4000 0x200>;
  388. interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>;
  389. atmel,use-dma-rx;
  390. atmel,use-dma-tx;
  391. pinctrl-names = "default";
  392. pinctrl-0 = <&pinctrl_uart0>;
  393. status = "disabled";
  394. };
  395. uart1: serial@fffd8000 {
  396. compatible = "atmel,at91sam9260-usart";
  397. reg = <0xfffd8000 0x200>;
  398. interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
  399. atmel,use-dma-rx;
  400. atmel,use-dma-tx;
  401. pinctrl-names = "default";
  402. pinctrl-0 = <&pinctrl_uart1>;
  403. status = "disabled";
  404. };
  405. macb0: ethernet@fffc4000 {
  406. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  407. reg = <0xfffc4000 0x100>;
  408. interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
  409. pinctrl-names = "default";
  410. pinctrl-0 = <&pinctrl_macb_rmii>;
  411. status = "disabled";
  412. };
  413. usb1: gadget@fffa4000 {
  414. compatible = "atmel,at91rm9200-udc";
  415. reg = <0xfffa4000 0x4000>;
  416. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
  417. status = "disabled";
  418. };
  419. i2c0: i2c@fffac000 {
  420. compatible = "atmel,at91sam9260-i2c";
  421. reg = <0xfffac000 0x100>;
  422. interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
  423. #address-cells = <1>;
  424. #size-cells = <0>;
  425. status = "disabled";
  426. };
  427. mmc0: mmc@fffa8000 {
  428. compatible = "atmel,hsmci";
  429. reg = <0xfffa8000 0x600>;
  430. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
  431. #address-cells = <1>;
  432. #size-cells = <0>;
  433. status = "disabled";
  434. };
  435. ssc0: ssc@fffbc000 {
  436. compatible = "atmel,at91rm9200-ssc";
  437. reg = <0xfffbc000 0x4000>;
  438. interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
  439. pinctrl-names = "default";
  440. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  441. status = "disabled";
  442. };
  443. spi0: spi@fffc8000 {
  444. #address-cells = <1>;
  445. #size-cells = <0>;
  446. compatible = "atmel,at91rm9200-spi";
  447. reg = <0xfffc8000 0x200>;
  448. interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
  449. pinctrl-names = "default";
  450. pinctrl-0 = <&pinctrl_spi0>;
  451. status = "disabled";
  452. };
  453. spi1: spi@fffcc000 {
  454. #address-cells = <1>;
  455. #size-cells = <0>;
  456. compatible = "atmel,at91rm9200-spi";
  457. reg = <0xfffcc000 0x200>;
  458. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
  459. pinctrl-names = "default";
  460. pinctrl-0 = <&pinctrl_spi1>;
  461. status = "disabled";
  462. };
  463. adc0: adc@fffe0000 {
  464. compatible = "atmel,at91sam9260-adc";
  465. reg = <0xfffe0000 0x100>;
  466. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
  467. atmel,adc-use-external-triggers;
  468. atmel,adc-channels-used = <0xf>;
  469. atmel,adc-vref = <3300>;
  470. atmel,adc-num-channels = <4>;
  471. atmel,adc-startup-time = <15>;
  472. atmel,adc-channel-base = <0x30>;
  473. atmel,adc-drdy-mask = <0x10000>;
  474. atmel,adc-status-register = <0x1c>;
  475. atmel,adc-trigger-register = <0x04>;
  476. atmel,adc-res = <8 10>;
  477. atmel,adc-res-names = "lowres", "highres";
  478. atmel,adc-use-res = "highres";
  479. trigger@0 {
  480. trigger-name = "timer-counter-0";
  481. trigger-value = <0x1>;
  482. };
  483. trigger@1 {
  484. trigger-name = "timer-counter-1";
  485. trigger-value = <0x3>;
  486. };
  487. trigger@2 {
  488. trigger-name = "timer-counter-2";
  489. trigger-value = <0x5>;
  490. };
  491. trigger@3 {
  492. trigger-name = "external";
  493. trigger-value = <0x13>;
  494. trigger-external;
  495. };
  496. };
  497. watchdog@fffffd40 {
  498. compatible = "atmel,at91sam9260-wdt";
  499. reg = <0xfffffd40 0x10>;
  500. status = "disabled";
  501. };
  502. };
  503. nand0: nand@40000000 {
  504. compatible = "atmel,at91rm9200-nand";
  505. #address-cells = <1>;
  506. #size-cells = <1>;
  507. reg = <0x40000000 0x10000000
  508. 0xffffe800 0x200
  509. >;
  510. atmel,nand-addr-offset = <21>;
  511. atmel,nand-cmd-offset = <22>;
  512. pinctrl-names = "default";
  513. pinctrl-0 = <&pinctrl_nand>;
  514. gpios = <&pioC 13 GPIO_ACTIVE_HIGH
  515. &pioC 14 GPIO_ACTIVE_HIGH
  516. 0
  517. >;
  518. status = "disabled";
  519. };
  520. usb0: ohci@00500000 {
  521. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  522. reg = <0x00500000 0x100000>;
  523. interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
  524. status = "disabled";
  525. };
  526. };
  527. i2c@0 {
  528. compatible = "i2c-gpio";
  529. gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
  530. &pioA 24 GPIO_ACTIVE_HIGH /* scl */
  531. >;
  532. i2c-gpio,sda-open-drain;
  533. i2c-gpio,scl-open-drain;
  534. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  535. #address-cells = <1>;
  536. #size-cells = <0>;
  537. pinctrl-names = "default";
  538. pinctrl-0 = <&pinctrl_i2c_gpio0>;
  539. status = "disabled";
  540. };
  541. };