clock.c 9.4 KB

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  1. /* linux/arch/arm/plat-s3c24xx/clock.c
  2. *
  3. * Copyright 2004-2005 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C24XX Core clock control support
  7. *
  8. * Based on, and code from linux/arch/arm/mach-versatile/clock.c
  9. **
  10. ** Copyright (C) 2004 ARM Limited.
  11. ** Written by Deep Blue Solutions Limited.
  12. *
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  27. */
  28. #include <linux/init.h>
  29. #include <linux/module.h>
  30. #include <linux/kernel.h>
  31. #include <linux/list.h>
  32. #include <linux/errno.h>
  33. #include <linux/err.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/sysdev.h>
  36. #include <linux/interrupt.h>
  37. #include <linux/ioport.h>
  38. #include <linux/clk.h>
  39. #include <linux/spinlock.h>
  40. #include <linux/io.h>
  41. #if defined(CONFIG_DEBUG_FS)
  42. #include <linux/debugfs.h>
  43. #endif
  44. #include <mach/hardware.h>
  45. #include <asm/irq.h>
  46. #include <plat/cpu-freq.h>
  47. #include <plat/clock.h>
  48. #include <plat/cpu.h>
  49. #include <linux/serial_core.h>
  50. #include <plat/regs-serial.h> /* for s3c24xx_uart_devs */
  51. /* clock information */
  52. static LIST_HEAD(clocks);
  53. /* We originally used an mutex here, but some contexts (see resume)
  54. * are calling functions such as clk_set_parent() with IRQs disabled
  55. * causing an BUG to be triggered.
  56. */
  57. DEFINE_SPINLOCK(clocks_lock);
  58. /* enable and disable calls for use with the clk struct */
  59. static int clk_null_enable(struct clk *clk, int enable)
  60. {
  61. return 0;
  62. }
  63. int clk_enable(struct clk *clk)
  64. {
  65. if (IS_ERR(clk) || clk == NULL)
  66. return -EINVAL;
  67. clk_enable(clk->parent);
  68. spin_lock(&clocks_lock);
  69. if ((clk->usage++) == 0)
  70. (clk->enable)(clk, 1);
  71. spin_unlock(&clocks_lock);
  72. return 0;
  73. }
  74. void clk_disable(struct clk *clk)
  75. {
  76. if (IS_ERR(clk) || clk == NULL)
  77. return;
  78. spin_lock(&clocks_lock);
  79. if ((--clk->usage) == 0)
  80. (clk->enable)(clk, 0);
  81. spin_unlock(&clocks_lock);
  82. clk_disable(clk->parent);
  83. }
  84. unsigned long clk_get_rate(struct clk *clk)
  85. {
  86. if (IS_ERR(clk))
  87. return 0;
  88. if (clk->rate != 0)
  89. return clk->rate;
  90. if (clk->ops != NULL && clk->ops->get_rate != NULL)
  91. return (clk->ops->get_rate)(clk);
  92. if (clk->parent != NULL)
  93. return clk_get_rate(clk->parent);
  94. return clk->rate;
  95. }
  96. long clk_round_rate(struct clk *clk, unsigned long rate)
  97. {
  98. if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
  99. return (clk->ops->round_rate)(clk, rate);
  100. return rate;
  101. }
  102. int clk_set_rate(struct clk *clk, unsigned long rate)
  103. {
  104. int ret;
  105. if (IS_ERR(clk))
  106. return -EINVAL;
  107. /* We do not default just do a clk->rate = rate as
  108. * the clock may have been made this way by choice.
  109. */
  110. WARN_ON(clk->ops == NULL);
  111. WARN_ON(clk->ops && clk->ops->set_rate == NULL);
  112. if (clk->ops == NULL || clk->ops->set_rate == NULL)
  113. return -EINVAL;
  114. spin_lock(&clocks_lock);
  115. ret = (clk->ops->set_rate)(clk, rate);
  116. spin_unlock(&clocks_lock);
  117. return ret;
  118. }
  119. struct clk *clk_get_parent(struct clk *clk)
  120. {
  121. return clk->parent;
  122. }
  123. int clk_set_parent(struct clk *clk, struct clk *parent)
  124. {
  125. int ret = 0;
  126. if (IS_ERR(clk))
  127. return -EINVAL;
  128. spin_lock(&clocks_lock);
  129. if (clk->ops && clk->ops->set_parent)
  130. ret = (clk->ops->set_parent)(clk, parent);
  131. spin_unlock(&clocks_lock);
  132. return ret;
  133. }
  134. EXPORT_SYMBOL(clk_enable);
  135. EXPORT_SYMBOL(clk_disable);
  136. EXPORT_SYMBOL(clk_get_rate);
  137. EXPORT_SYMBOL(clk_round_rate);
  138. EXPORT_SYMBOL(clk_set_rate);
  139. EXPORT_SYMBOL(clk_get_parent);
  140. EXPORT_SYMBOL(clk_set_parent);
  141. /* base clocks */
  142. int clk_default_setrate(struct clk *clk, unsigned long rate)
  143. {
  144. clk->rate = rate;
  145. return 0;
  146. }
  147. struct clk_ops clk_ops_def_setrate = {
  148. .set_rate = clk_default_setrate,
  149. };
  150. struct clk clk_xtal = {
  151. .name = "xtal",
  152. .id = -1,
  153. .rate = 0,
  154. .parent = NULL,
  155. .ctrlbit = 0,
  156. };
  157. struct clk clk_ext = {
  158. .name = "ext",
  159. .id = -1,
  160. };
  161. struct clk clk_epll = {
  162. .name = "epll",
  163. .id = -1,
  164. };
  165. struct clk clk_mpll = {
  166. .name = "mpll",
  167. .id = -1,
  168. .ops = &clk_ops_def_setrate,
  169. };
  170. struct clk clk_upll = {
  171. .name = "upll",
  172. .id = -1,
  173. .parent = NULL,
  174. .ctrlbit = 0,
  175. };
  176. struct clk clk_f = {
  177. .name = "fclk",
  178. .id = -1,
  179. .rate = 0,
  180. .parent = &clk_mpll,
  181. .ctrlbit = 0,
  182. };
  183. struct clk clk_h = {
  184. .name = "hclk",
  185. .id = -1,
  186. .rate = 0,
  187. .parent = NULL,
  188. .ctrlbit = 0,
  189. .ops = &clk_ops_def_setrate,
  190. };
  191. struct clk clk_p = {
  192. .name = "pclk",
  193. .id = -1,
  194. .rate = 0,
  195. .parent = NULL,
  196. .ctrlbit = 0,
  197. .ops = &clk_ops_def_setrate,
  198. };
  199. struct clk clk_usb_bus = {
  200. .name = "usb-bus",
  201. .id = -1,
  202. .rate = 0,
  203. .parent = &clk_upll,
  204. };
  205. struct clk s3c24xx_uclk = {
  206. .name = "uclk",
  207. .id = -1,
  208. };
  209. /* initialise the clock system */
  210. /**
  211. * s3c24xx_register_clock() - register a clock
  212. * @clk: The clock to register
  213. *
  214. * Add the specified clock to the list of clocks known by the system.
  215. */
  216. int s3c24xx_register_clock(struct clk *clk)
  217. {
  218. if (clk->enable == NULL)
  219. clk->enable = clk_null_enable;
  220. /* fill up the clk_lookup structure and register it*/
  221. clk->lookup.dev_id = clk->devname;
  222. clk->lookup.con_id = clk->name;
  223. clk->lookup.clk = clk;
  224. clkdev_add(&clk->lookup);
  225. return 0;
  226. }
  227. /**
  228. * s3c24xx_register_clocks() - register an array of clock pointers
  229. * @clks: Pointer to an array of struct clk pointers
  230. * @nr_clks: The number of clocks in the @clks array.
  231. *
  232. * Call s3c24xx_register_clock() for all the clock pointers contained
  233. * in the @clks list. Returns the number of failures.
  234. */
  235. int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
  236. {
  237. int fails = 0;
  238. for (; nr_clks > 0; nr_clks--, clks++) {
  239. if (s3c24xx_register_clock(*clks) < 0) {
  240. struct clk *clk = *clks;
  241. printk(KERN_ERR "%s: failed to register %p: %s\n",
  242. __func__, clk, clk->name);
  243. fails++;
  244. }
  245. }
  246. return fails;
  247. }
  248. /**
  249. * s3c_register_clocks() - register an array of clocks
  250. * @clkp: Pointer to the first clock in the array.
  251. * @nr_clks: Number of clocks to register.
  252. *
  253. * Call s3c24xx_register_clock() on the @clkp array given, printing an
  254. * error if it fails to register the clock (unlikely).
  255. */
  256. void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
  257. {
  258. int ret;
  259. for (; nr_clks > 0; nr_clks--, clkp++) {
  260. ret = s3c24xx_register_clock(clkp);
  261. if (ret < 0) {
  262. printk(KERN_ERR "Failed to register clock %s (%d)\n",
  263. clkp->name, ret);
  264. }
  265. }
  266. }
  267. /**
  268. * s3c_disable_clocks() - disable an array of clocks
  269. * @clkp: Pointer to the first clock in the array.
  270. * @nr_clks: Number of clocks to register.
  271. *
  272. * for internal use only at initialisation time. disable the clocks in the
  273. * @clkp array.
  274. */
  275. void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
  276. {
  277. for (; nr_clks > 0; nr_clks--, clkp++)
  278. (clkp->enable)(clkp, 0);
  279. }
  280. /* initialise all the clocks */
  281. int __init s3c24xx_register_baseclocks(unsigned long xtal)
  282. {
  283. printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
  284. clk_xtal.rate = xtal;
  285. /* register our clocks */
  286. if (s3c24xx_register_clock(&clk_xtal) < 0)
  287. printk(KERN_ERR "failed to register master xtal\n");
  288. if (s3c24xx_register_clock(&clk_mpll) < 0)
  289. printk(KERN_ERR "failed to register mpll clock\n");
  290. if (s3c24xx_register_clock(&clk_upll) < 0)
  291. printk(KERN_ERR "failed to register upll clock\n");
  292. if (s3c24xx_register_clock(&clk_f) < 0)
  293. printk(KERN_ERR "failed to register cpu fclk\n");
  294. if (s3c24xx_register_clock(&clk_h) < 0)
  295. printk(KERN_ERR "failed to register cpu hclk\n");
  296. if (s3c24xx_register_clock(&clk_p) < 0)
  297. printk(KERN_ERR "failed to register cpu pclk\n");
  298. return 0;
  299. }
  300. #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
  301. /* debugfs support to trace clock tree hierarchy and attributes */
  302. static struct dentry *clk_debugfs_root;
  303. static int clk_debugfs_register_one(struct clk *c)
  304. {
  305. int err;
  306. struct dentry *d, *child, *child_tmp;
  307. struct clk *pa = c->parent;
  308. char s[255];
  309. char *p = s;
  310. p += sprintf(p, "%s", c->devname);
  311. d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
  312. if (!d)
  313. return -ENOMEM;
  314. c->dent = d;
  315. d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usage);
  316. if (!d) {
  317. err = -ENOMEM;
  318. goto err_out;
  319. }
  320. d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
  321. if (!d) {
  322. err = -ENOMEM;
  323. goto err_out;
  324. }
  325. return 0;
  326. err_out:
  327. d = c->dent;
  328. list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
  329. debugfs_remove(child);
  330. debugfs_remove(c->dent);
  331. return err;
  332. }
  333. static int clk_debugfs_register(struct clk *c)
  334. {
  335. int err;
  336. struct clk *pa = c->parent;
  337. if (pa && !pa->dent) {
  338. err = clk_debugfs_register(pa);
  339. if (err)
  340. return err;
  341. }
  342. if (!c->dent) {
  343. err = clk_debugfs_register_one(c);
  344. if (err)
  345. return err;
  346. }
  347. return 0;
  348. }
  349. static int __init clk_debugfs_init(void)
  350. {
  351. struct clk *c;
  352. struct dentry *d;
  353. int err;
  354. d = debugfs_create_dir("clock", NULL);
  355. if (!d)
  356. return -ENOMEM;
  357. clk_debugfs_root = d;
  358. list_for_each_entry(c, &clocks, list) {
  359. err = clk_debugfs_register(c);
  360. if (err)
  361. goto err_out;
  362. }
  363. return 0;
  364. err_out:
  365. debugfs_remove_recursive(clk_debugfs_root);
  366. return err;
  367. }
  368. late_initcall(clk_debugfs_init);
  369. #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */